KR920004936A - 프로그래머블 로직소자의 입력/출력 마크로셀 - Google Patents

프로그래머블 로직소자의 입력/출력 마크로셀 Download PDF

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KR920004936A
KR920004936A KR1019900012258A KR900012258A KR920004936A KR 920004936 A KR920004936 A KR 920004936A KR 1019900012258 A KR1019900012258 A KR 1019900012258A KR 900012258 A KR900012258 A KR 900012258A KR 920004936 A KR920004936 A KR 920004936A
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output
programmable logic
macrocell
logic array
sum data
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KR1019900012258A
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KR930004033B1 (ko
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하창완
문중근
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정몽헌
현대전자산업 주식회사
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Priority to KR1019900012258A priority Critical patent/KR930004033B1/ko
Priority to JP3198106A priority patent/JP2633418B2/ja
Priority to US07/742,605 priority patent/US5136188A/en
Publication of KR920004936A publication Critical patent/KR920004936A/ko
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음.

Description

프로그래머블 로직소자의 입력/출력 마크로셀
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 블럭 구성도.
제 2 도는 본 발명의 세부 회로 구성도.
제 3 도는 디멀티플렉서의 구성도.
제 4 도는 본 발명의 다른 실시예시도.
* 도면의 주요부분에 대한 부호의 설명
10 : 마크로셀 11 : OR 게이트 그룹
12 : 디멀트플렉서 그룹 13 : OR 게이트 그룹

Claims (15)

  1. 다수의 입력신호 및 자체의 저장정보를 통해 "앤드"로직을 구성하여 다수의 출력신호를 제공하는 프로그래머블 로직 어레이(15)에 연결되어 상기의 출력신호(적항)들을 논리합(OR)한 후 입력/출력회로(14)를 거쳐 출력하거나 상기 프로그래머블 로직 어레이(15)로 궤환시키는 마크로셀(Macrocell)에 있어서 ; 다수의 OR게이트로 구성되며 상기 프로그래머블 로직 어레이(15)로부터의 적항을 각각 소정의 수만큼 논리합(OR)하여 출력하는 제 1 논리합수단(11), 상기 제 1 논리합수단(11) 각각의 OR 게이트 출력단에 연결된 다수의 디멀티플렉서로 구성되며, 각각의 1입력 신호에 대해 2이상의 출력 신호를 발생시키는 디멀티플렉스 수단(12), 상기 디멀티플렉스 수단(12)의 각 디멀티플렉서 한 출력단에 연결되어 그 출력들을 논리합(OR)함으로써 하나의 적항의 합 데이타 경로를 형성하는 OR 게이트가 다수개로 구성되는 제 2 논리합 수단(13), 및 상기 제 2 논리합 수단(13)의 다수개 OR 게이트로부터 제공되는 다수의 적항의 합 데이타 경로를 받아서 출력단으로 보내거나 상기의 프로그래머블 로직 어레이(15)로 궤환시키는 입력/출력 수단(14)으로 구성되어 하나의 마크로셀 내에 다수의 적항의 합 데이타 경로를 포함하도록 함을 특징으로 하는 마크로셀.
  2. 제 1 항에 있어서, 상기 제 1 논리합 수단(11)을 구성하는 하나의 OR 게이트가 논리합(OR)하는 적항의 수는 상기 적항의 효율적인 이용을 위해 인위적으로 정하는 임의의 특정 숫자임을 특징으로 하는 마크로셀.
  3. 제 1 항에 있어서, 상기 디멀티플렉스 수단(12)을 구성하는 디멀티플렉서 수는 제 1 논리합 수단(11)을 구성하는 OR 게이트 수와 동일하게 구성함을 특징으로 하는 마크로셀.
  4. 제 3 항에 있어서, 상기 각 디멀티플렉서는 상기 프로그래머블 로직 어레이(15)로부터 오는 또다른 적항들에 의해 제어됨을 특징으로 하는 마크로셀.
  5. 제 3 항에 있어서, 상기 제 1 논리합 수단(11)에 입력되는 다수의 적항은 EPROM 트랜지스터로 구성된 프로그래머블 로직 어레이(15)에 의해 제공됨을 특징으로 하는 마크로셀.
  6. 제 3 항에 있어서, 상기 제 1 논리합 수단(11)에 입력되는 다수의 적항은 EEPRO M 트랜지스터로 구성된 프로그래머블 로직 어레이(15)에 의해 제공됨을 특징으로 하는 마크로셀.
  7. 제 3 항에 있어서, 상기 제 2 논리합 수단(13)을 구성하는 OR 게이트는 상기 각 디멀티플렉서의 출력신호 수와 동일하게 구성함을 특징으로 하는 마크로셀.
  8. 제 1 항에 있어서, 다수의 적항의 합 데이타를 받는 상기 입력/출력 수단(14)은 조합 로직 및 순차로직 동작을 동시에 에뮬레이션 함을 특징으로 하는 마크로셀.
  9. 제 8 항에 있어서, 조합 로직과 순차 로직의 동시 구현시 상기 각 동작은 서로 다른 적항의 합 데이타 경로를 점유하도록 함을 특징으로 하는 마크레셀.
  10. 다수의 입력신호 및 자체의 저장정보를 통해 "앤드"로직을 구성하여 다수의 출력신호를 제공하는 프로그래머블 로직 어레이(15)에 연결되어 상기의 출력신호(적항)들을 논리합(OR)한 후 입력/출력회로(14)를 거쳐 출력하거나 상기 프로그래머블 로직 어레이(15)로 궤환시키는 마크로셀(Macrocell)에 있어서 ; 다수의 OR게이트로 구성되며 상기 프로그래머블 로직 어레이(15)로부터의 적항을 각각 소정의 수만큼 논리합(OR)하여 다수의 적항의 합 데이타를 각기 다른 경로로 출력하는 논리합 수단(11), 및 상기 논리합수단(11)의 다수의 OR 게이트에서 출력되는 다수의 적항의 합 데이타를 각기 다른 경로를 통해 입력하여 출력단으로 보내거나 상기의 프로그래머블 로직 어레이(15)로 궤환시키는 입력/출력수단(14)으로 구성되어 하나의 마크로셀 내에 다수의 적항의 합 데이타 경로를 갖도록 함을 특징으로 하는 마크로셀.
  11. 제10항에 있어서, 상기 논리합 수단(11)을 구성하는 하나의 OR 게이트가 논리합(OR)하는 적항의 수는 상기 적항의 효율적인 이용을 위해 인위적으로 정하는 임의의 특정 숫자임을 특징으로 하는 마크로셀.
  12. 제10항에 있어서, 상기 논리합 수단(11)에 입력되는 다수의 적항은 EPROM 트랜지스터로 구성된 프로그래머블 로직 어레이(15)에 의해 제공됨을 특징으로 하는 마크로셀.
  13. 제10항에 있어서, 상기 논리합 수단(11)에 입력되는 다수의 적항은 EEPROM 트랜지스터로 구성된 프로그래머블 로직 어레이(15)에 의해 제공됨을 특징으로 하는 마크로셀.
  14. 제10항에 있어서, 다수의 적항의 합 데이타를 받는 상기 입력/출력 수단(14)은 조합 로직 및 순차 로직 동작을 동시에 에뮬레이션함을 특징으로 하는 마크로셀.
  15. 제14항에 있어서, 조합 로직과 순차 로직의 동시 구현시 상기 각 동작은 서로 다른 적항의 합 데이타 경로를 점유하도록 함을 특징으로 하는 마크로셀.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900012258A 1990-08-09 1990-08-09 프로그래머블 로직소자의 입력/출력 마크로셀 KR930004033B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019900012258A KR930004033B1 (ko) 1990-08-09 1990-08-09 프로그래머블 로직소자의 입력/출력 마크로셀
JP3198106A JP2633418B2 (ja) 1990-08-09 1991-08-07 プログラマブルロジック素子の入力／出力マクロセル
US07/742,605 US5136188A (en) 1990-08-09 1991-08-08 Input/output macrocell for programmable logic device

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KR1019900012258A KR930004033B1 (ko) 1990-08-09 1990-08-09 프로그래머블 로직소자의 입력/출력 마크로셀

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Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5331227A (en) * 1992-05-15 1994-07-19 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US5394030A (en) * 1992-11-10 1995-02-28 Infinite Technology Corporation Programmable logic device
KR100287538B1 (ko) * 1992-11-10 2001-04-16 다부찌 노리오 프로그램가능로직디바이스및구성가능로직네트워크
JP3313848B2 (ja) * 1992-11-10 2002-08-12 インフィニット テクノロジー コーポレーション ロジックネットワーク
US5357153A (en) * 1993-01-28 1994-10-18 Xilinx, Inc. Macrocell with product-term cascade and improved flip flop utilization
US5311080A (en) * 1993-03-26 1994-05-10 At&T Bell Laboratories Field programmable gate array with direct input/output connection
US5473266A (en) * 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
US5352940A (en) * 1993-05-27 1994-10-04 Altera Corporation Ram convertible look-up table based macrocell for PLDs
US5399922A (en) * 1993-07-02 1995-03-21 Altera Corporation Macrocell comprised of two look-up tables and two flip-flops
US5402014A (en) * 1993-07-14 1995-03-28 Waferscale Integration, Inc. Peripheral port with volatile and non-volatile configuration
US5414376A (en) * 1993-12-28 1995-05-09 Micron Semiconductor, Inc. Programmable logic device macrocell having exclusive lines for feedback and external input, and a node which is selectively shared for registered output and external input
WO1996013902A1 (en) * 1994-11-01 1996-05-09 Virtual Machine Works, Inc. Programmable multiplexing input/output port
US5815003A (en) * 1994-11-04 1998-09-29 Altera Corporation Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals
JP3122589B2 (ja) * 1994-12-29 2001-01-09 株式会社タカトリ パンティストッキング素材の装着方法
US5563529A (en) * 1995-05-26 1996-10-08 Xilinx, Inc. High speed product term allocation structure supporting logic iteration after committing device pin locations
US5969539A (en) * 1995-05-26 1999-10-19 Xilinx, Inc. Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure
US6531890B1 (en) * 1995-06-02 2003-03-11 Lattice Semiconductor Corporation Programmable optimized-distribution logic allocator for a high-density complex PLD
US6028446A (en) * 1995-06-06 2000-02-22 Advanced Micro Devices, Inc. Flexible synchronous and asynchronous circuits for a very high density programmable logic device
US5594367A (en) * 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic
US6127844A (en) * 1997-02-20 2000-10-03 Altera Corporation PCI-compatible programmable logic devices
US6201407B1 (en) * 1997-10-07 2001-03-13 Cypress Semiconductor Corp Circular product term allocations scheme for a programmable device
US6069488A (en) * 1997-11-14 2000-05-30 Xilinx, Inc. Programmable logic device with versatile exclusive or architecture
US6066959A (en) * 1997-12-09 2000-05-23 Intel Corporation Logic array having multi-level logic planes
US6346826B1 (en) * 1998-12-23 2002-02-12 Integrated Logic Systems, Inc Programmable gate array device
US6388464B1 (en) 1999-12-30 2002-05-14 Cypress Semiconductor Corp. Configurable memory for programmable logic circuits
US6864710B1 (en) 1999-12-30 2005-03-08 Cypress Semiconductor Corp. Programmable logic device
US6608500B1 (en) 2000-03-31 2003-08-19 Cypress Semiconductor Corp. I/O architecture/cell design for programmable logic device
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7844437B1 (en) 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
US7770113B1 (en) 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US8103497B1 (en) 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7308608B1 (en) 2002-05-01 2007-12-11 Cypress Semiconductor Corporation Reconfigurable testing system and method
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
US7796464B1 (en) 2003-06-27 2010-09-14 Cypress Semiconductor Corporation Synchronous memory with a shadow-cycle counter
US7295049B1 (en) 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
US8892806B2 (en) * 2007-03-07 2014-11-18 Intel Mobile Communications GmbH Integrated circuit, memory device, method of operating an integrated circuit, and method of designing an integrated circuit
US8516025B2 (en) 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US7737724B2 (en) * 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
US7893772B1 (en) 2007-12-03 2011-02-22 Cypress Semiconductor Corporation System and method of loading a programmable counter
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
US9904646B2 (en) * 2011-09-27 2018-02-27 Microchip Technology Incorporated Virtual general purpose input/output for a microcontroller

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617479B1 (en) * 1984-05-03 1993-09-21 Altera Semiconductor Corp. Programmable logic array device using eprom technology
US4609986A (en) * 1984-06-14 1986-09-02 Altera Corporation Programmable logic array device using EPROM technology
US4593390A (en) * 1984-08-09 1986-06-03 Honeywell, Inc. Pipeline multiplexer
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
US4983959A (en) * 1986-10-01 1991-01-08 Texas Instruments Incorporated Logic output macrocell
US4845496A (en) * 1987-09-24 1989-07-04 Dower Roger G Electro-optical displacement sensor
US4878200A (en) * 1987-12-30 1989-10-31 Intel Corporation Product term sharing/allocation in an EPROM array
US5053647A (en) * 1989-07-17 1991-10-01 Fuji Photo Film Co., Ltd. Programmable logic array having feedback flip-flops connected between a product array's inputs and its outputs
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation

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US5136188A (en) 1992-08-04
JPH04234222A (ja) 1992-08-21

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