KR920003476A - Memory device manufacturing method using self-aligned silicide - Google Patents

Memory device manufacturing method using self-aligned silicide Download PDF

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Publication number
KR920003476A
KR920003476A KR1019900010428A KR900010428A KR920003476A KR 920003476 A KR920003476 A KR 920003476A KR 1019900010428 A KR1019900010428 A KR 1019900010428A KR 900010428 A KR900010428 A KR 900010428A KR 920003476 A KR920003476 A KR 920003476A
Authority
KR
South Korea
Prior art keywords
self
memory device
aligned silicide
device manufacturing
polycrystalline silicon
Prior art date
Application number
KR1019900010428A
Other languages
Korean (ko)
Other versions
KR930005483B1 (en
Inventor
김현종
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900010428A priority Critical patent/KR930005483B1/en
Publication of KR920003476A publication Critical patent/KR920003476A/en
Application granted granted Critical
Publication of KR930005483B1 publication Critical patent/KR930005483B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

자기정열 실리사이드를 이용한 기억소자 제조방법Memory device manufacturing method using self-aligned silicide

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 제조공정을 나타낸 단면도.2 is a cross-sectional view showing a manufacturing process of the present invention.

Claims (1)

실리콘 기판위에 게이트 산화막, 다결정 실리콘을 형성하고 이 다결정 실리콘을 사진 식각법에 의해 선택적으로 제거하는 공정과, 제거된 다결정 실리콘 위에 실리사이드를 적층하고 열처리후 실리사이드화 되지 않은 부분을 제거하는 공정과, 소오스/드레인 영역을 형성하기 위한 이온주입 공정을 차례로 실시함을 특징으로 하는 자기정열 실리사이드를 이용한 기억소자 제조방법.Forming a gate oxide film and polycrystalline silicon on the silicon substrate and selectively removing the polycrystalline silicon by photolithography; laminating silicide on the removed polycrystalline silicon and removing unsilicided portions after heat treatment; A method for manufacturing a memory device using self-aligned silicide, characterized in that the ion implantation step for forming the drain region is performed in sequence. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010428A 1990-07-10 1990-07-10 Memory device manufacturing method using self-alignment siliside KR930005483B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900010428A KR930005483B1 (en) 1990-07-10 1990-07-10 Memory device manufacturing method using self-alignment siliside

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010428A KR930005483B1 (en) 1990-07-10 1990-07-10 Memory device manufacturing method using self-alignment siliside

Publications (2)

Publication Number Publication Date
KR920003476A true KR920003476A (en) 1992-02-29
KR930005483B1 KR930005483B1 (en) 1993-06-22

Family

ID=19301097

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010428A KR930005483B1 (en) 1990-07-10 1990-07-10 Memory device manufacturing method using self-alignment siliside

Country Status (1)

Country Link
KR (1) KR930005483B1 (en)

Also Published As

Publication number Publication date
KR930005483B1 (en) 1993-06-22

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