KR920001732A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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KR920001732A
KR920001732A KR1019910010679A KR910010679A KR920001732A KR 920001732 A KR920001732 A KR 920001732A KR 1019910010679 A KR1019910010679 A KR 1019910010679A KR 910010679 A KR910010679 A KR 910010679A KR 920001732 A KR920001732 A KR 920001732A
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well
conductivity type
conductivity
impurity diffusion
diffusion region
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KR1019910010679A
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Korean (ko)
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KR950009893B1 (en
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겡이찌 야스다
시게루 모리
마나시또 스호
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시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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Priority claimed from JP2172407A external-priority patent/JP2609743B2/en
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Publication of KR920001732A publication Critical patent/KR920001732A/en
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Publication of KR950009893B1 publication Critical patent/KR950009893B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

반도체 기억장치Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 언더슈트의 현상을 설명하는 도면.2 is a diagram for explaining the phenomenon of undershoot.

제3B도는 제3A도에 표시하는 메모리셀의 등가회로도.3B is an equivalent circuit diagram of a memory cell shown in FIG. 3A.

Claims (12)

제1전도율형의 반도체기판(1)에 형성하는 제1전도율형(3a)의 제1웰과 제1전도융(3a)의 제1웰에 인접하는 상기 반도체기판(1)에 형성되는 제2전도율형웰(2b)과, 상기 제2전도율형웰(2b)에 형성되고 제2전도율형웰(3a)에 의해 에워싸이는 주변측벽과 저표면을 가지는 제1전도율형(2b)의 제2웰과 그리고 제1전도율형(3b)의 제2웰상에 형성되는 메모리셀(7b)과 소정의 극성의 전원공급 전압레벨의 전위를 가지는 상기 제2전도율형웰(3a)과 접지레벨의 전위를 가지는 제1전도율형(3b)의 상기 제2웰과 제1전도율형(3a)의 상기 제1웰을 포함하는 반도체 기억장치.A second well formed in the semiconductor substrate 1 adjacent to the first well of the first conductivity type 3a and the first well of the first conductive melt 3a formed in the first conductivity type semiconductor substrate 1 A second well of the first conductivity type 2b having a conductivity well 2b, a peripheral side wall formed in the second conductivity well 2b and surrounded by a second conductivity well 3a, and having a low surface; A first conductivity having a potential of the memory cell 7b formed on the second well of the first conductivity type 3b and the second conductivity well 3a having a potential of a power supply voltage level of a predetermined polarity and a ground level. And said second well of type (3b) and said first well of first conductivity type (3a). 제1항에 있어서, 다른 소자와 분리되어 절연되고 제1전도율형(3a)의 상기 제1웰과 제1전도형(3b)의 상기제2웰표면에 각각 형성되는 제1전도율 불순물 확산영역(5)을 가지고 그 제1전도율형 불순물확산영역(5)은 접지 터미널에 접속되는 반도체 기억장치.2. The first conductivity impurity diffusion region according to claim 1, wherein the first conductivity impurity diffusion region is formed on the first well of the first conductivity type 3a and the second well surface of the first conductivity type 3b, 5) and the first conductivity type impurity diffusion region 5 is connected to the ground terminal. 제1항에 있어서, 다른 소자와 분리되어 절연되고 상기 제2전도율형웰(2b)의 표면상기 형성되는 제2전도율형 불순물확산영역(4)을 가지고 그 제2전도율형 불순물확산영역(4)은 전원공급터미널에 접속되는 반도체 기억장치.2. The second conductivity type impurity diffusion region (4) according to claim 1, having a second conductivity type impurity diffusion region (4) which is separated from and insulated from other elements and formed on the surface of the second conductivity well (2b). A semiconductor memory device connected to a power supply terminal. 제1항에 있어서, 상기 반도체 기판(1)은 더욱 제1전도율형(3a)의 상기 제1웰에 인접하는 또다른 제2전도율형웰(2a)을 포함하고, 제1전도율형체널(6)의 MOSFET는 제2전도율형웰에 형성되고 제2전도율형체널(7a)의 MOSFET는 제1전도율형(3a)의 상기 제1웰에 형성되고 그리고 제1전도율형체널(6)의 상기 MOSFET와 제2전도율형 체널(7a)의 상기 MOSFET는 상보형 MOS회로를 구성하는 반도체 기억장치.The semiconductor substrate (1) of claim 1, wherein the semiconductor substrate (1) further comprises another second conductivity well (2a) adjacent the first well of the first conductivity type (3a), and the first conductivity channel (6). Is formed in the second conductivity type well and the MOSFET of the second conductivity type channel 7a is formed in the first well of the first conductivity type 3a and the MOSFET and the first conductivity type channel 6 are formed in the first well. The MOSFET of the two conductivity type channel 7a constitutes a complementary MOS circuit. 제1전도율형의 반도체기판(1)과 상기 반도체기판(1)의 주표면상에 형성되는 외부입력회로(7c)와 메모리셀(7b)과 그리고 상기 반도체기판(1)의 표면부에서의 제2전도율형웰(2b) 내부에 형성되는 제1전도율형웰(3b)와 제2전도율형웰(2b)을 포함하고 상기 외부입력회로(7c)는 상기 제1전도율형웰(3b)의 영역상에 제공되고 상기 메모리셀(7b)은 상기 전도율형웰(2b)의 영역외부에 제공되고 상기 제2전도율형웰(2b)은 소정의 전원 공급전압 레벨의 전위를 가지고 그리고 상기 제1전도율형웰(3b)은 접지레벨의 전위를 가지는 반도체 기억장치.A first conductivity type semiconductor substrate 1, an external input circuit 7c and a memory cell 7b formed on the main surface of the semiconductor substrate 1, and a first portion at a surface portion of the semiconductor substrate 1; A first conductivity well 3b and a second conductivity well 2b formed inside the second conductivity well 2b, and the external input circuit 7c is provided on an area of the first conductivity well 3b. The memory cell 7b is provided outside the region of the conductivity well 2b and the second conductivity well 2b has a potential of a predetermined power supply voltage level and the first conductivity well 3b has a ground level. A semiconductor memory device having a potential of. 제5항에 있어서, 다른소자와 분리되어 상기 제1전도율형웰의 표면상에 형성되는 제1전도율형 불순물 확산영역(5)을 포함하고 제1전도율형 불순물확산영역은 접지터미널에 접속되는 반도체 기억장치.6. The semiconductor memory according to claim 5, further comprising a first conductivity type impurity diffusion region (5) formed on a surface of said first conductivity well, separate from other elements, wherein said first conductivity type impurity diffusion region is connected to a ground terminal. Device. 제5항에 있어서, 다른소자와 분리되어 절연되고 상기 제2전도율형웰의 표면상에 형성하는 제2전도율형 불순물확산영역(4)을 포함하고 제2전도율형 불순물확산영역(4)은 전원공급터미널에 접속되는 반도체 기억장치.6. The second conductivity type impurity diffusion region (4) according to claim 5, further comprising a second conductivity type impurity diffusion region (4) formed on the surface of the second conductivity type well, insulated from other elements, and the second conductivity type impurity diffusion region (4). A semiconductor memory device connected to the terminal. 제5항에 있어서, 상기 메모리셀(7b)은 상기 제2전도율형웰(2b)외측영역에 형성되는 다른 제1전도율형웰(3a)의 표면상에 형성되는 반도체 기억장치.6. The semiconductor memory device according to claim 5, wherein said memory cell (7b) is formed on the surface of another first conductivity type well (3a) formed in an outer region of said second conductivity type well (2b). 제5항에 있어서, 상기 메모리셀(7b)은 웰이 형성되지 않은 반도체기판(1)의 표면의 상기 제2전도율형웰(2b)와 부제 1전도율 영역에 형성되는 반도체 기억장치.6. The semiconductor memory device according to claim 5, wherein said memory cell (7b) is formed in said second conductivity type well (2b) and subsidiary conductivity region on the surface of a semiconductor substrate (1) in which wells are not formed. 제1전도율형의 반도체기판(1)과 소정의 깊이에 반도체기판(1)의 표면에서 형성되는 제2전도율형웰(2c), 제1전도율형(3b)의 제2웰 그리고 제1전도율형(3a)의 제1웰과, 그리고 고에너지 이온주입에 의해 각 상기웰의 저표면의 깊이에서 소정의 깊이까지에 형성되는 제2전도율형 전도층(2d)과, 상기 반도체(1)과 제1전도율형(3a)의 상기 제1웰과 전기적으로 절연되도록 상기 제2전도율형 전도층(2d)에 의해 덮인 그의 전지표면과 상기 제2전도율형웰(2c)에 의해 에워싸이는 그의 주변측벽의 전표면을 가지는 제1전도율형(3B)의 상기 제2웰을 포함하는 반도체 기억장치.The first conductivity type semiconductor substrate 1 and the second conductivity well 2c formed on the surface of the semiconductor substrate 1 at a predetermined depth, the second well of the first conductivity type 3b, and the first conductivity type ( The first well of 3a), and a second conductivity type conductive layer 2d formed from the depth of the low surface of each well to a predetermined depth by high energy ion implantation, and the semiconductor 1 and the first The cell surface covered by the second conductivity type conductive layer 2d and its peripheral side wall surrounded by the second conductivity type well 2c so as to be electrically insulated from the first well of conductivity type 3a. And a second well of a first conductivity type (3B) having a surface. 제10항에 있어서, 제1전도율형(3b)의 상기 제2웰은 접지레벨의 전위를 가지고 그리고 그의 표면상에 형성되는 메모리셀(7b)을 가지고 그리고 상기 제2율형웰은 전원공급전압레벨의 전위를 가지는 반도체 기억장치.11. The method of claim 10 wherein the second well of the first conductivity type 3b has a potential at ground level and has a memory cell 7b formed on its surface and the second rate well has a power supply voltage level. A semiconductor memory device having a potential of. 제10항에 있어서, 외부입력회로(7c)는 제1전도율형(3b)의 상기 제2웰의 표면상에 형성되고 메모리셀(7b)은 제1전도율형(3a)의 상기 제1웰의 표면상에 형성되고 제1전도율형(3a,3b)의 상기 제1과 제2웰은 접지레벨의 전위를 가지고 그리고 상기 제2전도율형웰(2b)는 전원공급 전압레벨의 전위를 가지는 반도체 기억장치.11. An external input circuit (7c) is formed on the surface of the second well of the first conductivity type (3b) and the memory cell (7b) is formed of the first well of the first conductivity type (3a). A semiconductor memory device formed on a surface and wherein the first and second wells of the first conductivity type 3a, 3b have a potential at ground level and the second conductivity well 2b has a potential at a power supply voltage level. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910010679A 1990-06-28 1991-06-26 Semiconductor memory device KR950009893B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2172407A JP2609743B2 (en) 1990-06-28 1990-06-28 Semiconductor device
JP2-172407 1990-06-28
JP28495990 1990-10-22
JP2-28544 1990-10-22

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KR920001732A true KR920001732A (en) 1992-01-30
KR950009893B1 KR950009893B1 (en) 1995-09-01

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US5281842A (en) 1994-01-25
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DE4121292C2 (en) 1995-02-02
KR950009893B1 (en) 1995-09-01

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