KR920000033Y1 - Analog/ttl multi signal coding circuits for monitor - Google Patents

Abstract

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Description

Analog / TIEL multi-signal coding circuit of monitor

1 is an embodiment circuit diagram of the present invention.

2 is an analog and digital characteristic diagram of the monitor input signal.

* Explanation of symbols for the main parts of the drawings

XR1-XR4: Exclusive logic gate R1-R9: Resistance

Q1-Q3: Transistor NT1, NT2: Inverter

C1-C4: Capacitor D: Diode

SW: switch

The present invention is a multi-mode monitor for using computers connected with signals of different modes connected to one monitor, so as to determine the mode of each signal output from the computer and to have a time constant for the determined mode. The time constant circuit is switched by an electronic switch circuit, and at this time, the present invention relates to an analog / TIEL multi-signal coding circuit configured to discriminate the mode of an input signal and to achieve a mode of each mode for controlling the electronic switch circuit.

Conventionally, there is a method of using a circuit for digitalizing some signals or converting a frequency into a voltage. However, these methods have problems such as complicated circuits and low reliability.

The present invention is designed to distinguish each mode by coordinating each mode according to the frequency and polarity of the synchronization signal in order to solve such a problem. Hereinafter, the configuration and effect of the present invention will be described in detail with reference to the accompanying drawings. Same as

The B + voltage and the ground voltage are applied to the fixed contacts (a) and (b) of the selector switch SW switched by the output of the analog / tiel discrimination circuit, respectively, and the output voltage of the movable contact (c) is corrected according to the respective modes. It is applied to one side control signal input terminal TA of the electronic switch control circuit ESC for switching the number, and the horizontal synchronous signal HS and the vertical synchronous signal VS are applied to the conversion unit 1, respectively. The output of the negative unit 1 is applied to the other control signal input terminal HC VC of the electronic switch control circuit ESC via the inverters NT1 and NT2, and the vertical synchronization signal VS is discriminated. It is applied to the unit 2, and the output of this determination unit 2 is configured to be applied to the output terminal of the inverter NT1.

In the above configuration, the converting unit 1 receives the horizontal synchronizing signal HS and the vertical synchronizing signal VS so that one input is applied to the other input of the exclusive logic sum gate XR1 (XR3) connected to ground, respectively. It is applied to one input of the exclusive logic gates XR2 and XR4, respectively, and the outputs of the exclusive logic gates XR1 and XR3 are inverted through the integrating circuits of the resistors R1, R2 and C1, C2. It is applied to the inputs of the adapters NT1 and NT2, respectively, and connected to the other inputs of the exclusive logic gates XR2 and XR4, respectively, and the discriminating unit 2 is inputted with the vertical synchronization signal VS. It is applied to the base of the transistor Q1 through the capacitor C3 and the bias resistors ER3 and R4, and the emitter output of the transistor Q1 supplies the integrated circuit of the variable resistor VR and the capacitor C4. Is applied to the base of the transistor Q2, and the collector output of the transistor Q2 is inverted through the diode D1. The connection to be applied to the output terminal of the (NT1).

In the unexplained symbols, R5-R9 is a resistor.

In the present invention configured as described above, the frequency and polarity of the horizontal synchronous signal and the vertical synchronous signal of each mode are shown in the diagram of Fig. 2 (a), where CGA mode (Color Graphic Adapter) and MDA mode (Mono Display Adapter). ), The EGA mode (Enhanced Graphic Adapter) is a TI signal, and the VGA (1) (2) (3) (Video Graphic Adapter) mode is an analog signal. First, when the horizontal synchronizing signal HS and the vertical synchronizing signal VS of the CGA mode are input, the movable contact c of the selector switch SW is connected to the fixed contact a by the conventional TI / analog discrimination circuit. As it is connected, the B + voltage is applied to the control signal input terminal TA of the ordinary electronic switch control circuit, while the exclusive horizontal synchronizing signal HS and the vertical synchronizing signal VS are exclusive logic gates in the converting unit 1. When applied to one input of each of (XR1-XR4), the other input of the exclusive logic gate (XR1) (XR3) is connected to ground, so that the exclusive logic gate (XR1) (XR3) functions as a buffer. Therefore, the output of this exclusive logical gate XR1 (XR3) becomes the same waveform as the horizontal synchronizing signal HS and the vertical synchronizing signal VS to integrate the resistors R1 (R2) and the capacitors C1 (C2). In this case, the positive synchronous signal integrates the horizontal synchronous signal (HS) and the vertical synchronous signal (VS) because the width of the regular pulse is much smaller than the width of the reference voltage at the 'low' level. When the output voltage of the low level converter 1 is applied to the inverters NT1 and NT2 and inverted, the outputs of the inverters NT1 and NT2 become the high level. While applied to the control signal input terminals HC and VC of the ordinary electronic switch control circuit, respectively, the low level voltage, which is the integrated circuit output of the resistors R1, R2, and C1, C2, is applied. It is applied to the other input of the exclusive logic gate XR2 and XR4 so that the output of the exclusive logic gate XR2 and XR4 is also the horizontal synchronization signal HS and the vertical synchronization. A horizontal synchronizing signal HS to which the same signal as the arc VS is output, and to which the horizontal synchronizing signal HO and the vertical synchronizing signal VO output from the exclusive logic gate XR2 and XR4 are applied to other circuits, and It is supplied as a vertical synchronization signal VS.

Further, when a positive polarity vertical synchronizing signal VS having a frequency of 60 Hz is applied to the base of the transistor Q1 through the coupling capacitor C3 and the bias resistor R3 and R4 in the discriminating unit 2, the transistor ( The emitter output of Q1) is amplified by the input signal, and this amplified vertical synchronous signal is applied to the integrating circuit of the time constant regulating variable resistor (VR) and the condenser (C4) and integrated. Integrating the amplified negative or positive vertical synchronizing signal is less than or equal to the conduction voltage between the base and emitter of the transistor Q2, and integrating the amplified negative vertical synchronizing signal having a frequency of 50 HZ or less is applied to the transistor Q2. As the time constant adjustment variable resistor VR is set to be equal to or more than the conduction voltage between the base and the emitter, when the 60HZ amplified positive vertical sync signal of the CGS mode is integrated, the transistor is applied to the base of the transistor Q2. The conduction voltage between the emitter Q2 becomes equal to or less than the base-emitter conduction voltage, and the integrated voltage is applied to the base of the transistor Q2 to be applied to the base of the transistor Q2 to turn off the transistor Q2. Accordingly, as the B + power is applied to the base of the transistor Q3 through the resistors R7 and R8 and the transistor Q3 is 'off', the reverse current prevention diode D1 is 'off' and the inverter NT1 is turned off. High level voltage is maintained.

Next, when the horizontal synchronous signal HS and the vertical synchronous signal VS of the MDA mode are input, the MDA mode is also a TI signal, so that the B + voltage is switched by the selection switch SW by the TI / analog discrimination circuit. When applied to the control signal input terminal TA of the control circuit and the positive horizontal synchronous signal HS and the negative vertical synchronous signal VS are respectively input to the converter 1, the resistors are operated in the same circuit operation as described above. The output of the integrating circuit of (R1) and the capacitor (C1) becomes the 'low' level signal, and the negative polarity synchronous signal has the resistance (R2) and the negative pulse width because the width of the negative voltage is much smaller than the width of the reference voltage at the 'high' level. The output of the integrating circuit of the capacitor C2 becomes a 'high' level signal and is applied to the inverters NT1 and NT2, respectively, and the input signals are inverted at the inverters NT1 and NT2, respectively, so that the inverter NT1 is inverted. ) Outputs a 'high' level signal, and an output of inverter NT2 A low 'level signal is output. At this time, if a negative vertical synchronization signal VS of 50HZ is applied to the base of the transistor Q1 through the coupling capacitor C3 in the determination unit 2, the negative vertical synchronization signal ( VS is amplified and output from the emitter of transistor Q1, and when this 50 HZ amplified negative vertical synchronizing signal is integrated by the variable resistor VR1 and capacitor C4, the integral integrated pressure is applied to the base of transistor Q2. When the emitter voltage becomes higher than the conduction voltage between the emitters, the transistor Q2 conducts and the collector potential becomes the ground potential, thereby applying a 'low' level to the base of the transistor Q3, thereby conducting the transistor Q3.

Therefore, the 'high' level signal output from the inverter NT1 flows to the ground through the reverse current prevention diode D1 and the transistor Q3 in the discriminating unit 2, and the output of the inverter NT1 is 'low'. The 'heavy' level signal is applied to the control signal input terminal HC VC of the electronic switch control circuit by being converted to the 'level'.

In addition, when the horizontal synchronization signal HS and the vertical synchronization signal VS of the EGA mode are input and applied to the conversion unit 1, the output of the conversion unit 1 is' low 'level and' The high level signal is output and applied to the inverters NT1 and NT2, respectively. The outputs of the inverters NT1 and NT2 are inverted so that the 'high' level and 'low' level signals On the other hand, the 60HZ negative polarity vertical synchronizing signal VS is amplified by the transistor Q1 through the coupling capacitor C3 in the discriminating unit 2 and integrated in the variable resistor VR1 and the capacitor C4. This integrated voltage is less than the base-emitter conduction voltage of transistor Q2, and this transistor Q2 is 'off'. Thus, the B + voltage is applied to the base of transistor Q3 through resistors R7 and R8, so that transistor Q3 is 'off'. Accordingly, the voltage B + is applied to the cathode of the diode D1 through the resistor R9 so that the diode Q1 is 'off', so that the output of the inverter NT1 and NT2 has a low level signal. 'The level signal is applied to the control signal input terminal HC (VC) of the electronic switch control circuit, respectively, and the B + voltage according to the TI signal is applied to the control signal input terminal TA.

In addition, in the VGA (1) (2) (3) mode, which is an analog signal, the select switch SW is switched to ground, and a 'low' level signal is applied to the control signal input terminal TA of the electronic switch control circuit. The circuit operation of the converting unit 1 and the discriminating unit 2 by the synchronizing signal HS and the vertical synchronizing signal VS is operated in the same manner as described above. Therefore, when the control signals applied to the control signal input terminals TA (HC) VC of the electronic switch control circuit are coded according to the voltage level, the six modes of the codes are different from each other as shown in FIG. The mode of the input signal is determined by the electronic switch control circuit.

As such, the present invention is a useful design having advantages such as improved product quality and cost reduction because the input signal can be accurately identified by converting six analog / digital modes into different digital modes with a simple circuit configuration.

Claims (3)

A switching switch SW operated by a conventional analog / TI signal discrimination circuit, a converting unit 1 for digitizing the polarity of the input horizontal synchronizing signal HS and the vertical synchronizing signal VS, and this converting unit 1 The output level of the inverter NT1 is changed when a negative signal of a specific frequency is inputted by determining whether the inverter NT1, NT2 and the vertical synchronization signal VS have positive or negative polarity and their frequency. An analog / TI multi-multiple signal coding circuit for a monitor, characterized by comprising a discriminating unit (2). 2. The converting unit (1) according to claim 1, wherein the converting unit (1) is input with the horizontal synchronizing signal (HS) and the vertical synchronizing signal (VS) so that one input is applied to the other input of the exclusive logic gate (XR1) (XR3) connected to ground. At the same time, it is applied to one input of the exclusive logic gates XR2 and XR4, respectively, and the outputs of the exclusive logic gates XR1 and XR3 are supplied through the integrating circuits of the resistors R1 (R2) and the capacitors C1 (C2). The analog / ti multiple signal coding circuit of the monitor characterized in that it is configured to be connected to the inputs of the inverters NT1 and NT2 and applied to the other input of the exclusive logic gate XR2 and XR4, respectively. . The transistor of claim 1, wherein the discriminating unit (2) is inputted to the base of the transistor (Q1) through the coupling capacitor (C3) and the bias resistor (R3) and the R4 (R4). The emitter output of Q1 is applied to the base of the transistor Q2 via the integrating circuit of the variable resistor VR and the capacitor C4, and through the collector output resistor R8 of the transistor Q2. It is applied to the base of transistor Q3, and the collector output of this transistor Q3 is connected and applied to the output terminal of inverter NT1 through diode D1. Signal coding circuit.