KR910018918A - How to Program Subprocessors in RAM in Multiprocessor Systems - Google Patents

How to Program Subprocessors in RAM in Multiprocessor Systems Download PDF

Info

Publication number
KR910018918A
KR910018918A KR1019900005588A KR900005588A KR910018918A KR 910018918 A KR910018918 A KR 910018918A KR 1019900005588 A KR1019900005588 A KR 1019900005588A KR 900005588 A KR900005588 A KR 900005588A KR 910018918 A KR910018918 A KR 910018918A
Authority
KR
South Korea
Prior art keywords
ram
program
subprocessors
multiprocessor systems
sub
Prior art date
Application number
KR1019900005588A
Other languages
Korean (ko)
Other versions
KR930003125B1 (en
Inventor
정중연
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019900005588A priority Critical patent/KR930003125B1/en
Publication of KR910018918A publication Critical patent/KR910018918A/en
Application granted granted Critical
Publication of KR930003125B1 publication Critical patent/KR930003125B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

내용 없음No content

Description

멀티 프로세서를 이용한 시스템에서 서브 프로세서의 프로그램을 램에 실장하는 방법A method of mounting a program of a subprocessor in RAM in a multiprocessor system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 서브 프로세서의 구성도, 제4도는 본 발명에 따른 흐름도3 is a configuration diagram of a subprocessor according to the present invention, and FIG. 4 is a flowchart according to the present invention.

Claims (1)

멀티 프로세서를 이용하는 시스템에서 서브 프로세서의 프로그램을 램에 실장하는 방법에 있어서, 시스템을 초기화하는 1과정과, 상기 제1과정 수행 후 서브 프로세서(100)의 리세트 신호를 인에이블시켜 듀얼포트 메모리(300)의 특정 번지에서 데이타를 램(500)에 옮겨 프로그램을 로딩시키는 제2과정과, 상기 제2과정에서 수행후 서브 프로세서(100)와 레시트 신호를 디세이블시켜 듀얼포트 메모리(300)에서 프로그램 데이타를 램이 옮기는 제3과정과, 상기 제3과정 수행후 상기 서브 프로세서(100)가 램(500)에서 프로그램을 변경하여 특정기능을 수정하는 제4과정으로 이루어짐을 특징으로 하는 서브 프로세서에서의 프로그램을 실장시키는 방법.In a method of mounting a program of a subprocessor in a RAM in a system using a multiprocessor, a dual port memory may be configured by enabling a process of initializing the system and enabling a reset signal of the subprocessor 100 after performing the first process. In the dual port memory 300, a second process of loading data by transferring data to the RAM 500 at a specific address of 300) and disabling the sub-processor 100 and the rest signal after performing the second process. In the sub-processor characterized in that the third process of moving the program data to the RAM, and after performing the third process the sub-processor 100 modifies a specific function by changing the program in the RAM 500 To build your own program. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900005588A 1990-04-20 1990-04-20 Method for pregram loading on ram located in subprocessor system KR930003125B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900005588A KR930003125B1 (en) 1990-04-20 1990-04-20 Method for pregram loading on ram located in subprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900005588A KR930003125B1 (en) 1990-04-20 1990-04-20 Method for pregram loading on ram located in subprocessor system

Publications (2)

Publication Number Publication Date
KR910018918A true KR910018918A (en) 1991-11-30
KR930003125B1 KR930003125B1 (en) 1993-04-19

Family

ID=19298195

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900005588A KR930003125B1 (en) 1990-04-20 1990-04-20 Method for pregram loading on ram located in subprocessor system

Country Status (1)

Country Link
KR (1) KR930003125B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392306B1 (en) * 2001-06-04 2003-07-22 주식회사 한단정보통신 A program processing apparatus and method for set-top box
KR100417224B1 (en) * 1996-04-10 2004-04-30 삼성전자주식회사 How to Overlay a Program on a Hard Disk Drive

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417224B1 (en) * 1996-04-10 2004-04-30 삼성전자주식회사 How to Overlay a Program on a Hard Disk Drive
KR100392306B1 (en) * 2001-06-04 2003-07-22 주식회사 한단정보통신 A program processing apparatus and method for set-top box

Also Published As

Publication number Publication date
KR930003125B1 (en) 1993-04-19

Similar Documents

Publication Publication Date Title
KR960032172A (en) Computer systems
KR930001086A (en) CPU with integrated multiplication / accumulation unit
KR890017615A (en) Multiprocessor System with Multiport Cache Memory
JPS54107645A (en) Information processor
KR860700300A (en) Input memory circuit means and its distribution method
KR910018918A (en) How to Program Subprocessors in RAM in Multiprocessor Systems
JPS5731072A (en) Multiprocessor
JPS6481066A (en) Connection system for multi-processor
KR830010423A (en) Data exchange method of data processing system
CA2190119A1 (en) Method and apparatus for accessing a distributed data buffer
KR920010457A (en) Computer system with modem control
KR970049517A (en) Data Transfer Method of ISDN Board in High Speed Medium Computers
JPS6478361A (en) Data processing system
KR960018958A (en) Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System
KR920010472A (en) Tolerant system with multi skin
JPS5498125A (en) Control storage unit of computer
KR960025104A (en) Computer system with multiple processors in master or slave relationship
JPS57199052A (en) Data processing device
KR960024999A (en) Interprocess Communication Method in CHILL Simulation Environment
JPS56121155A (en) Address coincidence detection circuit
JPS5724088A (en) Buffer memory control system
JPS57150180A (en) Data processor
KR930004875A (en) Parallel Processing System by Multiple Processors
JPS54122060A (en) Inter-processor information transfer system
JPS5750046A (en) Data transmission system

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070312

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee