KR910013841A - Encryption and Decryption Circuits of Digital Telephones - Google Patents

Encryption and Decryption Circuits of Digital Telephones Download PDF

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Publication number
KR910013841A
KR910013841A KR1019890019628A KR890019628A KR910013841A KR 910013841 A KR910013841 A KR 910013841A KR 1019890019628 A KR1019890019628 A KR 1019890019628A KR 890019628 A KR890019628 A KR 890019628A KR 910013841 A KR910013841 A KR 910013841A
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KR
South Korea
Prior art keywords
data
input
clock
stage
shift register
Prior art date
Application number
KR1019890019628A
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Korean (ko)
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KR920007079B1 (en
Inventor
서중교
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019890019628A priority Critical patent/KR920007079B1/en
Publication of KR910013841A publication Critical patent/KR910013841A/en
Application granted granted Critical
Publication of KR920007079B1 publication Critical patent/KR920007079B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Facsimile Transmission Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음.No content.

Description

디지탈 전화기의 인크립션과 디크립션회로Encryption and Decryption Circuits of Digital Telephones

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 송신부의 구체회로도,1 is a specific circuit diagram of a transmitter according to the present invention;

제2도는 본 발명에 따른 제1도의 동작 타이밍도,2 is an operation timing diagram of FIG. 1 according to the present invention;

제3도는 본 발명에 따른 수신부의 구체회로도.3 is a detailed circuit diagram of a receiver according to the present invention.

Claims (1)

디지털 전화기의 인크립션과 디크립션 회로에 있어서, 데이터 버스(11)를 통해 입력되는 8비트 데이터를 기입제어단(12)을 통해 입력되는 로드(LD) 신호로부터 전송클럭단(13)의 클럭에 따라 쉬프트하여 키데이타를 발생할 제1쉬프트 레지스터(11)와, 메시지단(14)으로 입력되는 메시지 데이터와 상기 제1쉬프트 레지스터(11)의 출력 데이터를 배타적으로 논리합하는 제1익스클루시브 오아게이트(13)와, 상기 전송클럭단(15)의 클럭신호를 인버터(N1)에서 반전되는 신호에 따라 상기 제1익스크루시브 오아게이트(13)의 출력데이타를 래치하여 채널데이타로 출력하는 제1디플립플롭(14)와, 수신클럭단(32)의 입력 클럭을 인버터(N1)에서 반전하여 채널단(31)의 입력데이타를 래치하는 제2디플립플롭(33)과, 상기 수신클럭단(32)의 클럭을 입력으로 하여 기입제어단(37)의 제어에 따라 데이터 버스(36)상의 데이터를 쉬프트하는 제2쉬프트 레지스터(34)와, 상기 제2디플립플롭(33)의 출력데이타와 상기 제2쉬프트 레지스터(34)의 출력데이타를 배타적으로 논리합하여 메세지 데이터를 출력하는 제2익스클루시브 오아게이트(35)로 구성됨을 특징으로 하는 회로.In an encryption and decryption circuit of a digital telephone, 8-bit data input through the data bus 11 is transferred from a load (LD) signal input through the write control stage 12 to a clock of the transmission clock stage 13. A first exclusive oragate that exclusively ORs the first shift register 11 to generate key data by shifting the key data, the message data input to the message terminal 14, and the output data of the first shift register 11. (13) and a first latching output data of the first exclusive oragate 13 in response to a signal inverted by the inverter N1 in the clock signal of the transmission clock stage 15, and outputting the channel data. A second flip-flop (33) for inverting the flip-flop (14), the input clock of the receiving clock stage (32) at the inverter (N1), and latching the input data of the channel stage (31), and the receiving clock stage. Input of the clock of (32) to the input control stage 37 In other words, the second shift register 34 shifting the data on the data bus 36, the output data of the second flip-flop 33, and the output data of the second shift register 34 are exclusively OR. And a second exclusive oragate (35) for outputting message data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019628A 1989-12-27 1989-12-27 Apparatus for encryption and decryption of digital telephone system KR920007079B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019628A KR920007079B1 (en) 1989-12-27 1989-12-27 Apparatus for encryption and decryption of digital telephone system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019628A KR920007079B1 (en) 1989-12-27 1989-12-27 Apparatus for encryption and decryption of digital telephone system

Publications (2)

Publication Number Publication Date
KR910013841A true KR910013841A (en) 1991-08-08
KR920007079B1 KR920007079B1 (en) 1992-08-24

Family

ID=19293730

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019628A KR920007079B1 (en) 1989-12-27 1989-12-27 Apparatus for encryption and decryption of digital telephone system

Country Status (1)

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KR (1) KR920007079B1 (en)

Also Published As

Publication number Publication date
KR920007079B1 (en) 1992-08-24

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