KR910013822A - Interface device of the test device of the TDX-10 exchanger - Google Patents

Interface device of the test device of the TDX-10 exchanger Download PDF

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Publication number
KR910013822A
KR910013822A KR1019890019581A KR890019581A KR910013822A KR 910013822 A KR910013822 A KR 910013822A KR 1019890019581 A KR1019890019581 A KR 1019890019581A KR 890019581 A KR890019581 A KR 890019581A KR 910013822 A KR910013822 A KR 910013822A
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KR
South Korea
Prior art keywords
control signal
relay
signal generating
decoder
address
Prior art date
Application number
KR1019890019581A
Other languages
Korean (ko)
Other versions
KR920005014B1 (en
Inventor
김영부
이종현
이미혜
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019890019581A priority Critical patent/KR920005014B1/en
Publication of KR910013822A publication Critical patent/KR910013822A/en
Application granted granted Critical
Publication of KR920005014B1 publication Critical patent/KR920005014B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

내용 없음.No content.

Description

TDX-10 교환기의 시험 장치의 인터페이스 장치Interface device of the test device of the TDX-10 exchanger

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성을 나타낸 블록도,1 is a block diagram showing the configuration of the present invention,

제2도는 제1도의 제어 신호 발생기의 구성을 나타낸 블록도,2 is a block diagram showing the configuration of the control signal generator of FIG.

제3도 내지 제1도의 페러렐 인터페이스부의 타이밍도.Fig. 3 is a timing diagram of the parallel interface of Figs.

Claims (2)

어드레스 버퍼(11), 상기 어드레스 버퍼(11)에 연결된 어드레스 디코우더(12), 상기 어드레스 디코우더(12)에 연결된 제어신호 발생 수단(13) 상기 제어 신호 발생 수단(13)에 연결된 데이터 래치 수단(14)으로 구성된 페러렐 인터페이스 수단(1), 상기 페러렐 인터페이스 수단(1)에 연결된 릴레이 디코우더 및 드라이버 수단(15), 상기 릴레이 및 드라이브 수단(15)에 연결된 릴레이 그룹(16)으로 구성된 릴레이 제어수단(2), 상기 페러렐 인터페이스 수단(1)과 릴레이 제어수단(2)에 연결되며, SLM 0(17)과 SLM 1(18), COMBO(19), 및 타임 슬롯 지정수단(20)으로 구성되어 통화 기능 및 감청 기능을 하는 통화 수단(3)으로 구성되는 것을 특징으로 하는 가입자 시험 장치의 인터페이스 장치.An address buffer 11, an address decoder 12 connected to the address buffer 11, a control signal generating means 13 connected to the address decoder 12, and a data connected to the control signal generating means 13. Parallel interface means (1) consisting of latch means (14), relay decoder and driver means (15) connected to the parallel interface means (1), and relay group (16) connected to the relay and drive means (15). It is connected to the configured relay control means 2, the parallel interface means 1 and the relay control means 2, and the SLM 0 17 and the SLM 1 18, the COMBO 19, and the time slot designation means 20. Interface device of a subscriber test device, characterized in that the call means (3) is configured to have a call function and an interception function. 제1항에 있어서, 제어신호 발생 수단(13)은 통신 시작 신호인 스토로우브와 수신한 어드레스(A3)를 트리거로 하는 D타입 플립플롭(21), 상기 D타입 플립플롭(21)의 출력을 인에이블 신호로 하는 16진 카운터 수단(22), 상기 16진 카운터 수단(22)에 연결되어 실질적인 제어신호를 발생하는 3/8디코우더(23)로 구성되는 것을 특징으로 하는 가입자 시험 장치의 인터페이스 장치.The control signal generating means (13) according to claim 1, characterized in that the control signal generating means (13) outputs the D-type flip-flop (21) and the outputs of the D-type flip-flop (21), which are triggered by the stove and the received address (A3). A hexadecimal counter means 22 serving as an enable signal, and a 3/8 decoder 23 connected to the hexadecimal counter means 22 to generate a substantial control signal. Interface device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019581A 1989-12-27 1989-12-27 Intuterface system of tdx-10 switching centre KR920005014B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019581A KR920005014B1 (en) 1989-12-27 1989-12-27 Intuterface system of tdx-10 switching centre

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019581A KR920005014B1 (en) 1989-12-27 1989-12-27 Intuterface system of tdx-10 switching centre

Publications (2)

Publication Number Publication Date
KR910013822A true KR910013822A (en) 1991-08-08
KR920005014B1 KR920005014B1 (en) 1992-06-22

Family

ID=19293712

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019581A KR920005014B1 (en) 1989-12-27 1989-12-27 Intuterface system of tdx-10 switching centre

Country Status (1)

Country Link
KR (1) KR920005014B1 (en)

Also Published As

Publication number Publication date
KR920005014B1 (en) 1992-06-22

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