KR970049502A

KR970049502A - Register Access Circuit Reduces Access Time

Info

Publication number: KR970049502A
Application number: KR1019950057013A
Authority: KR
Inventors: 김관영
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-26
Filing date: 1995-12-26
Publication date: 1997-07-29

Abstract

본 발명은 컴퓨터에서 인덱스를 이용해 레지스터를 액세스하는 레지스터 액세스 회로에 관한 것으로, 마이크로프로세서로부터의 어드레스신호를 디코딩하는 어드레스 디코딩수간과 상기 어드레스 디코딩수단에서 디코딩된 결과에 따라 옵션 환경변수를 저장하는 옵션 환경변수저장용 레지스터를 구비하는 인덱스를 이용한 인덱스를 이용한 레지스터 액세스 회로에 있어서, 상기 어드레스 디코딩수단과 상기 옵션 환경변수저장용 레지스터 사이에 접속되어 인덱스 사이클에서 인덱스 값이 래치되자마자 즉시 상기 마이크로프로세서에 준비신호를 인가하여 상기 마이크로프로세서가 바로 다음 사이클을 수행하도록 하는 준비신호 발생수단을 구비하여 레지스터의 액세스 시간을 줄일 수 있는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register access circuit for accessing a register using an index in a computer, wherein the option environment stores an option environment variable between an address decoding number for decoding an address signal from a microprocessor and a result decoded by the address decoding means. A register access circuit using an index using an index having a register for storing a variable, said register access circuit being connected between said address decoding means and said optional environment variable storing register and immediately ready to the microprocessor as soon as an index value is latched in an index cycle. There is an advantage that the access time of the register can be reduced by providing a signal preparation means for applying a signal to cause the microprocessor to perform the next cycle immediately.

Description

Register Access Circuit Reduces Access Time

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 실시예에 의한 액세스 시간을 줄일 레지스터 액세스 회로의 블럭도이다,1 is a block diagram of a register access circuit to reduce access time according to an embodiment of the present invention.

제2도는 제1도에 있는 블록도의 동작을 설명하기 위한 타이밍도이다.FIG. 2 is a timing diagram for explaining the operation of the block diagram in FIG.

Claims

A register access circuit using an index having an address decoding means for decoding an address signal from a microprocessor and an option environment variable storage register for storing an option environment variable in accordance with a result decoded by the address decoding means, wherein the address decoding is performed. Means and a ready signal generating means connected between said optional environment variable storage register and immediately applying a ready signal to said microprocessor as soon as an index value is latched in an index cycle to cause said microprocessor to perform the next cycle immediately. A register access circuit with reduced access time, characterized in that.

※ Note: The disclosure is based on the initial application.