KR910013476A - Transistor having triple base structure and manufacturing method thereof - Google Patents

Transistor having triple base structure and manufacturing method thereof Download PDF

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Publication number
KR910013476A
KR910013476A KR1019890018568A KR890018568A KR910013476A KR 910013476 A KR910013476 A KR 910013476A KR 1019890018568 A KR1019890018568 A KR 1019890018568A KR 890018568 A KR890018568 A KR 890018568A KR 910013476 A KR910013476 A KR 910013476A
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South Korea
Prior art keywords
base
manufacturing
transistor
epitaxial layer
base structure
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KR1019890018568A
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Korean (ko)
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KR0141962B1 (en
Inventor
윤기완
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019890018568A priority Critical patent/KR0141962B1/en
Publication of KR910013476A publication Critical patent/KR910013476A/en
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Publication of KR0141962B1 publication Critical patent/KR0141962B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음.No content.

Description

트리플 베이스 구조를 가지는 트랜지스터 및 그 제조방법Transistor having triple base structure and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 트랜지스터의 단면구조도,3 is a cross-sectional structure diagram of a transistor according to the present invention;

제4도 (가)(나)는 종래기술과 본 발명에 의한 소자의 접합 길이에 따른 농도구배 그래프.Figure 4 (a) (b) is a graph of concentration gradient according to the junction length of the device according to the prior art and the present invention.

Claims (2)

바이폴라 트랜지스터에 있어서, n 에피텍셜층위에 P베이스가 농도구배가 점차 증가되는 제1베이스, 제2베이스, 제3베이스의 3층 구조로 형성되고, 그위 n+에미터가 형성되며, 베이스 접합깊이가 5-7㎛, 에피텍셜층의 두께가 19㎛이상의 영역에 유지되게 형성되어 구성됨을 특징으로 하는 트리플 베이스 구조를 가지는 트랜지스터.In the bipolar transistor, the P base is formed on the n epitaxial layer in the three-layer structure of the first base, the second base, and the third base, the concentration gradient of which is gradually increased, and the n + emitter is formed thereon, and the base junction depth is formed. Is 5-7 μm, and the epitaxial layer is formed such that the thickness is maintained in a region of 19 μm or more. 바이폴라 트랜지스터의 제조방법에 있어서, 서브스트 레이트위에 n에피텍셜층을 형성한 후, 제1베이스는 에피텍셜층위에 보론 임플랜테이션 시킨 후 드라이브 인하고, 제3베이스는 보론을 디포지트한후 드라이브 인하며, 제3베이스는 보론 임플랜테이션시킨후 드라이브 인시키어 농도가 제1베이스<제2베이스<제3베이스인 3층 구조의 P베이스를 형성하고 이후에 n+에미터를 형성함을 특징으로 하는 트리플 베이스 구조를 가지는 트랜지스터의 제조방법.In the method of manufacturing a bipolar transistor, after forming the n epitaxial layer on the substrate, the first base is driven in after boron implantation on the epitaxial layer, and the third base is deposited after boron is deposited. The third base is boron-implanted and drive-in to form a three-layered P-base having a concentration of first base <second base <third base and then forming n + emitter. A method of manufacturing a transistor having a triple base structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890018568A 1989-12-14 1989-12-14 Transistor having triple base structure and manufacturing method thereof KR0141962B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890018568A KR0141962B1 (en) 1989-12-14 1989-12-14 Transistor having triple base structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890018568A KR0141962B1 (en) 1989-12-14 1989-12-14 Transistor having triple base structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR910013476A true KR910013476A (en) 1991-08-08
KR0141962B1 KR0141962B1 (en) 1998-07-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890018568A KR0141962B1 (en) 1989-12-14 1989-12-14 Transistor having triple base structure and manufacturing method thereof

Country Status (1)

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Publication number Publication date
KR0141962B1 (en) 1998-07-15

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