KR910008726Y1 - Frequency vehicle circuit by mode switching of pcm voice signal - Google Patents

Abstract

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Description

Divider circuit by mode switching of PCM audio signal

1 is a circuit diagram according to the present invention.

2 is a waveform diagram of FIG. 2 in B mode.

3 is a waveform diagram of FIG. 2 in A mode.

* Explanation of symbols for main parts of the drawings

15: counter 12: clear stage control circuit

20: D flip-flop 23: pulse shaping circuit

25: division control circuit

The present invention relates to a frequency divider circuit by mode switching of a PCM voice signal, and more particularly, to a frequency divider circuit by mode switching of a PCM voice signal for use in a PCM decoder interface required for receiving a PCM voice signal.

Pulse code modulation (hereinafter referred to as PCM) refers to a pulse amplitude modulation signal by sampling the original input signal at the transmitting side, and quantizing each sampling pulse thereof to convert it into a code (usually binary code of 1.0). In this case, the reception side decodes the quantized negative hole, modulates the pulse amplitude, and interpolates with a filter to obtain an original input signal.

In general, the PCM voice sampling frequency (fs) is 32 kHz in A mode and 48 kHz in B mode. Therefore, in order to decode at the frequency as described above, 128 times the sampling frequency (fs) (A mode: 4.096GMHz, B mode: 6.14GMHz) or 64 times (A mode: 2.048GMHz, B mode: 3.072 GMHz) is required.

In order to sample the PCM voice signal having the frequency as described above, the frequency should be separated by using a divider circuit.

Conventional frequency divider circuits have various methods such as using programmable frequency divider circuits and JK flip-flops and gates. However, when the frequency of the input signal is high, the output signal is synchronized by the delay time of the gate. There may be a shift. A synchronous frequency divider is used to prevent synchronous deviation as described above. The combination of the JK flip-flop and the gate constitutes a synchronous frequency divider, which increases the complexity of the number of series connection terminals of the flip-flop. There was a problem being dispensed.

Accordingly, an object of the present invention is to provide a frequency divider circuit by mode switching of a PCM audio signal that can perform clock frequency 2N and 3N division by mode switching.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, in a mode switching frequency division circuit having a counter 15, after controlling a mode by a mode control signal input to a terminal 5, feedback of the counter 15 is shown. Clear stage of the counter 15 by signal A pulse shaping circuit 23 for shaping a pulse by inputting a clear stage control circuit 2 for controlling the control signal and a delayed feedback signal by inputting a feedback signal and an inverted clock pulse of the counter 15. And a division control circuit 25 for controlling the division state of the clock pulse by the mode control signal.

2 is an operation waveform diagram in the B mode, and FIG. 3 is an operation waveform diagram in the A mode, and FIGS. 2a and 3a are control signals in the "high" state input to the terminal 5, and FIG. And 3b are clock pulses input to the terminal 10, 2c and 3c are signals output from the first output terminal Q1 of the counter 15, and 2d and 3d are counters 15, respectively. 2e and 3e are the outputs of the second inverter I2, and 2f and 3f are the outputs of the D flip-flop 20, and 2g is also a signal output from the second output terminal Q12. And 3g are the outputs of the oragate OR, 2h and 3h are the outputs of the noate NO, and 2i and 3i are the outputs of the T flip-flop 30. FIG.

Hereinafter, the operation of FIG. 1 will be described in detail with reference to FIGS. 2 and 3.

In the B mode, the mode control signal in the " high " state as shown in FIG.

The mode control signal is input to one input terminal of the NAND gate NA in a "low" state through the first butter I1 so that the output of the NAND gate NA is always in a "high" state.

The "high" signal output from the NAND gate NA is cleared from the 4-bit binary counter 15. Inputted to cause the counter 15 to be enabled. In addition, a clock pulse CLK as shown in FIG. 2B input through the terminal 10 is input to the counter 15 through the clock terminal CK, and the input terminals F1, F2, F3, and F4 of the counter 15 are input. ) Is grounded.

The clock pulse CLK has a period of 12.288 MHz. At this time, when the clock pulse CLK reaches the first output terminal Q1 of the counter 15 at the rising edge, the clock pulse CLK transitions to the “high” state when the rising edge of the next period is reached. (6.144 MHz) is outputted. At this time, the second output stage Q2 transitions to the "high" state when the signal output from the first output terminal Q1 is the falling edge, and transitions to the "low" state when the rising edge of the next period is as shown in 2d. A clock pulse divided by 4 (3.072MHz) is output. The signal output from the second output terminal Q2 is input to the D flip-flop 20 via the D stage. In addition, the clock pulse CLK input through the terminal 10 is input to the clock terminal CL of the D flip-flop 20 in a low state through the inverter I2 as shown in FIG. 2E.

Accordingly, the D flip-flop 20 outputs a signal such as a second f degree in which the output of FIG. 2d is shifted by the residual of the clock pulse CLK through the output terminal Q, and is input to one end of the orcate OR. do. In addition, since the signal of FIG. 2d is input to the other end of the oragate OR, the oragate OR outputs the same signal as the 2g diagram of the 2d and 2f degrees. The signal of FIG. 2g is input to one end of the first and gate AN1, and the signal of the "low" state output from the first inverter I1 is input to the other end.

In addition, the signal of the "low" state output from the first butter I1 is input to one end of the second and gate AN2 in the "high" state through the third inverter I3, and the second and gate ( The signal of FIG. 2c output from the first output terminal Q1 of the counter 15 is input to the other end of AN2).

Therefore, the first end gate AN1 outputs a signal in a "low" state, and the second end gate AN2 outputs the same signal as that of the second c. Thus, in the second NOA gate NO2, the outputs of the first and second end gates AN1 and AN2 are input, respectively, to output the signals of the second c degree and the inverted second h degree, and the signals of the second h degree are It is divided through the T flip-flop 30 which is toggled and output as shown in FIG. 2i. The signals in Figs. 2h and 2i are input to a digital voice interface IC (not shown), wherein the clock pulses (12.288 MHz) are divided into two (6.144 MHz) and four (3.072 MHz), respectively.

In mode A, when the mode control signal as shown in FIG. 3a is input to the "low" state through the terminal 5, it is input to the "high" state to one end of the NAND gate NA via the first inverter I1. . In addition, the clock pulse CLK shown in FIG. 3B input through the terminal 10 is input to the counter 15 through the clock terminal CK. At the first output terminal Q1, the clock pulse CLK transitions to the "high" state when the rising edge is at the rising edge and to the "low" state when the rising edge of the next cycle is reached. If the output signal is outputted, the second output terminal Q2 outputs a signal transitioned to the "high" state when the signal output from the first output terminal Q1 is a falling edge. When the signal transitioned to the "high" state is input to the NAND gate NA in the "high" state at the other end, the NAND gate NA is output in the "low state" so that the clear end of the counter 15 ( CLR), so that the counter 15 is cleared when the next period of the clock pulse CLK is rising edge.

When the counter 15 is cleared, the signal output from the second output terminal Q2 is " low " transitioned to the NAND gate NA, so that the output of the NAND gate NA is in a high state. At the first output terminal Q1, a signal as shown in FIG. 3c is generated. Whenever one cycle of the signal output from the first output terminal Q1 ends, the second output terminal Q2 maintains a "high" state for half the period of the signal output from the first output terminal Q1. Same as shown in The signal output from the second output terminal Q2 is input to the D flip-flop 20 via the D stage. In addition, the clock pulse input through the terminal 10 Is the inverted clock pulse through the inverter I _{2 as} shown in FIG. Is inputted to the clock stage CLK of the D flip-flop 20 in a "low" state. Accordingly, the D flip-flop 20 inputs a signal, such as a third f degree signal, in which the signal of FIG. In addition, since the signal of FIG. 3d is input to the other end of the oragate OR, the oragate OR outputs the same signal of FIG. 3g where the 3d and 3f degrees are combined.

The third g degree signal is a signal shaped into three divisions (4.096 MHz). The signal of FIG. 2g is input to one end of the first and gate AN1, and the signal of the “high” state output from the first inverter I1 is input to the other end of the and gate AN1. In addition, a signal of the "low" state output from the first inverter I1 is input to the one end of the second end gate AN2 in a "low" state via the third inverter I3, and the counter to the other end thereof. The signal of FIG. 3c output from the first output terminal Q1 of (15) is input.

Accordingly, the second end gate AN2 is disabled to output a signal of the "low" state, and the first end gate AN1 outputs the output of the ora gate OR as it is. Since the output signals of the first and second end gates AN1 and AN2 are respectively input to the NOA gate NO, the NOA gate NO outputs a signal as shown in FIG. 3H. The signal of FIG. 3h is a waveform divided in three divisions (4.096 MHz) since the signal of FIG. 3g output from the oragate OR is inverted.

The signal of FIG. 3h divided by the third outputs a signal similar to that of FIG. 3i via the T flip-flop 30 performing the toggle operation. In the signal of FIG. 3i, a clock pulse (12.288 MHz) input through the terminal 10 is divided into six divisions (2.048 MHz). The signals in FIGS. 3H and 3I are input to the digital voice interface IC.

As described above, the present invention has the advantage that the clock frequency can be divided into 2N and 3N by automatic mode switching without using a separate division circuit.

Claims (1)

In the mode switching frequency division circuit provided with the counter 15, the mode is controlled by the mode control signal input to the terminal 5, and then the counter 15 is cleared by the feedback signal of the counter 15. only A pulse shaping circuit 23 for shaping a pulse by inputting a clear stage control circuit 2 for controlling the control signal and a delayed feedback signal by inputting a feedback signal and an inverted clock pulse of the counter 15. And a division control circuit (25) for controlling the division state of the clock pulse by the mode control signal.