KR910007475B1 - Multi - printed circuit board method - Google Patents
Multi - printed circuit board method Download PDFInfo
- Publication number
- KR910007475B1 KR910007475B1 KR1019890012204A KR890012204A KR910007475B1 KR 910007475 B1 KR910007475 B1 KR 910007475B1 KR 1019890012204 A KR1019890012204 A KR 1019890012204A KR 890012204 A KR890012204 A KR 890012204A KR 910007475 B1 KR910007475 B1 KR 910007475B1
- Authority
- KR
- South Korea
- Prior art keywords
- copper foil
- washed
- printed circuit
- predetermined
- circuit board
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
첨부된 도면은 종래기술에 따른 다층인쇄회로 기판의 제조시 그의 내층에 형성되는 핑크링의 예시도이다.The accompanying drawings are illustrations of pink rings formed on the inner layers thereof in the manufacture of multilayer printed circuit boards according to the prior art.
본 발명은 라디오, 텔레비젼, 컴퓨터 또는 전자교환기와 같은 전자기기에 이용되는 다층인쇄회로 기판(Multi Layer Printed Circuit Board) 분야에 관한 것으로서 특히, 다층 인쇄회로 기판의 도금공정시 산(HCl 및 H2SO4)의 침투로 인하여 홀주변에 있는 산화동박의 박리현상(이하 핑크링-Pink Ring이라한다)을 효율적으로 예방하기 위한 다층 인쇄회로기판의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of multi-layer printed circuit boards used in electronic devices such as radios, televisions, computers or electronic exchangers. In particular, the present invention relates to acid (HCl and H 2 SO) in the plating process of multi-layer printed circuit boards. 4 ) The present invention relates to a method for manufacturing a multilayer printed circuit board for effectively preventing the peeling phenomenon (hereinafter referred to as a pink ring) of copper oxide foil around a hole due to penetration.
현재 생산, 시판되고 있는 인쇄회로 기판에는 한쪽면 기판과 양면기판 및 다층기판이 있는바, 한쪽면 인쇄회로 기판은 절연체로 이루어진 후판(Backboard)을 표면처리하여 접착제를 도포한 뒤, 별도의 공정에 의해 제조된 도전체인 얇은 동박막을 후판에 접착하여 열간 압착시켜 인쇄회로 원판을 제조하고, 이렇게 제조된 인쇄회로 원판에서 회로를 구성하는 부분위에 애칭액을 도포하여 스크린 인쇄를 하여 용해액에 넣은뒤회로부분 이외의 부분을 부식시켜 회로판 부분만 남게한다음 세척한 뒤 부품의 리드선 삽입용 자동구멍뚫기와 같은 마무리공정을 함으로써 제조되었었다. 그리고, 양면 인쇄회로 기판은 절연기판의 양면에 동박을 부착한 것으로서 복잡한 배설을 할 때 사용되는 것이다. 또한, 다층 인쇄회로 기판은 한쪽면 기판을 여러겹으로 겹친 구조로서 중간의 각층에 특정한 도체를 매설하여 전자부품의 실장밀도를 높임과 동시에 전기적 특성변화의 향상을 꾀하기 위한 것인바, 종래의 다층 인쇄 회로기판의 제조공정을 간략히 설명한다.Printed circuit boards currently produced and marketed include single-sided boards, double-sided boards and multi-layered boards. One-side printed circuit boards are coated with an adhesive by surface-treating a backboard made of an insulator and then The thin copper thin film, which is a conductor, is bonded to a thick plate and hot-pressed to manufacture a printed circuit disc.The printed circuit disc is coated with a etch solution on a portion constituting the circuit. It was manufactured by corroding parts other than the circuit part so that only the circuit board part was left and washed, followed by a finishing process such as automatic perforation for inserting the lead wire of the part. In addition, the double-sided printed circuit board is a copper foil attached to both sides of the insulated substrate, which is used when complex excretion. In addition, the multilayer printed circuit board is a structure in which one side substrate is stacked in multiple layers to embed specific conductors in each intermediate layer to increase the mounting density of the electronic component and to improve the electrical characteristic change. The manufacturing process of the circuit board will be briefly described.
종래의 다층 인쇄회로 기판은 우선 필요한 칫수로서 인쇄회로 원판의 동박면에 레지스트에 의한 배선패턴을 형성하여 동박면 전면에 적당한 수단에 의해 감광제를 도포한다. 이렇게 감광제가 도포된 것을 적외선 전구와 같은 것을 이용하여 건조 및 노광시킨다. 기판에 감광제에 의한 레지스트 피막의 배선패턴이 형성되면 이것을 에칭액에 담궈서 불필요한 동박을 화학적으로 깍아내고 최후에 레지스트 피막을 박리하여 소정의 배선도체를 형성하게 된다.Conventional multilayer printed circuit boards first form a wiring pattern by resist on the copper foil surface of the printed circuit disc as a necessary dimension and apply a photosensitive agent to the entire copper foil surface by appropriate means. The photosensitive agent is applied and dried and exposed using an infrared light bulb. When the wiring pattern of the resist film by the photosensitive agent is formed in a board | substrate, it immerses this in an etching liquid, chemically scrapes away unnecessary copper foil, and finally, a resist film is peeled off and a predetermined wiring conductor is formed.
에칭이 끝난 기판은 물로 깨끗이 씻어내어 레지스트 피막을 박리한다. 만약 도금이 필요하다면 계속해서 도금탕에 담궈서 도금을 한뒤 세척한다. 이상과 같이 일단 배선패턴이 완성되었으면 다음에는 부품의 리드선 삽입용인 구멍뚫기 가공을 하여 다시 세척한다. 이러한 세척이 끝난 배선패턴을 소정의 압력하에서 가압하여 적층시키게 되면 다층기판이 완성된다.The etched substrate is washed off with water to remove the resist film. If plating is required, continue to soak in the plating bath to coat and clean. As described above, once the wiring pattern is completed, the process is performed again by drilling a hole for inserting the lead wire of the component and washing again. When the washed wiring pattern is pressed under a predetermined pressure to be laminated, a multilayer board is completed.
그러나, 이와 같은 다층기판은 제 1 도에 도시한 바와 같이, 도금공정시 내층(1)에서 B-스테이지(에폭시수지의 경화반응의 중간단계로서 에폭시수지는 가열에 의해 연화하지만 용융하지 않는 단계)와 블랙산화된 구리사이에 산(HCl, H2SO4)이 침투되어 내층의 구멍(2) 주위가 박리되는 소위 핑크링(3) 현상이 발생되므로 전기적특성의 변화를 야기시켜 컴퓨터 및 산업용기기에 많은 에러를 유발시키는 결점이 있었다.However, as shown in FIG. 1, the multi-layer substrate has a B-stage in the inner layer 1 during the plating process (the step of epoxy resin softening by heating but not melting) as an intermediate step of curing reaction of epoxy resin. Acid (HCl, H 2 SO 4 ) penetrates between the black and the black oxidized copper, causing the so-called pink ring (3) to peel off around the hole (2) in the inner layer. Has a flaw that causes many errors.
따라서, 본 발명은 이러한 사정을 감안하여 블랙산화된 산화동표면을 환원 처리함으로써 내층에서 발생되는 핑크링을 제거하기 의한 다층 인쇄회로 기판의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a multilayer printed circuit board by removing the pink ring generated in the inner layer by reducing the black oxidized copper oxide surface in view of such circumstances.
이러한 목적을 달성하기 의한 본 발명은 블랙산화된 동박표면을 소정의 온도로 수세하고, 이렇게 수세된 동박을 소정의 환원제로서 소정의 시간과 온도에서 1차 환원시키며, 1차 환원된 동박을 소정의 온도와 시간동안 수세하고, 수세된 동박을 소정의 환원제로 소저의 시간과 온도에서 2차 환원시키며, 이러한 동박을 소저의 온도로서 수세시키는 단계로 구성된다.According to the present invention, the surface of the black oxidized copper foil is washed at a predetermined temperature, the washed copper foil is first reduced as a predetermined reducing agent at a predetermined time and temperature, and the primary reduced copper foil is It washes for temperature and time, and wash | cleans the washed copper foil with a predetermined | prescribed reducing agent at the time and temperature of an reducer, and wash | cleans this copper foil as the temperature of a sour.
본 발명에 따르면, 동박면의 1차 환원조건은 NaBH4와 수산화나트륨을 사용하여 동박표면을 2분동안 45℃로 환원시키는 단계로 구성된다.According to the present invention, the primary reducing conditions of the copper foil surface consist of reducing the copper foil surface to 45 ° C. for 2 minutes using NaBH 4 and sodium hydroxide.
또한, 1차환원된 동박을 수세하기 위한 조건은 50℃에서 30초동안 물로 씻어내는 것이 가장 바람직스러우며, 2차환원 조건은 수세된 동박표면을 포르말린과 수산화 나트륨으로 30초동안 62℃∼72℃의 온도에서 환원시키는 것이 바람직스럽다.In addition, the conditions for washing the primary reduced copper foil is most preferably washed with water at 50 ℃ for 30 seconds, the secondary reduced condition is 62 ℃ to 72 ℃ for 30 seconds to wash the surface of the washed copper foil with formalin and sodium hydroxide It is preferable to reduce at a temperature of.
이하, 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail.
일반적으로 핑크링은 내층의 블랙산화된 동박면과 B-스테이지간의 충격변화로 인해 도금공정에서 산(HCl과 H2SO4)의 침투로 일어난다. 여기에서 동박면의 블랙산화 반응식은 다음과 같다.In general, the pink ring is caused by the penetration of acid (HCl and H 2 SO 4 ) in the plating process due to the impact change between the black oxidized copper foil surface of the inner layer and the B-stage. Here, black oxidation reaction of copper foil surface is as follows.
여기에서 Cu2O는 갈색이고, CuO는 흑색이다.Cu 2 O is brown and CuO is black.
이렇게 블랙산화된 산화동표면(Na2CuO,Na2Cu2O)을 70℃의 물로 2단 탕세한후 환원처리하게 되면 도금공정에서의 산(HCl,H2SO4)의 침투를 사전에 예방할 수가 있다. 따라서 NaBH41.5g/ℓ 과 수산화나트륨 5g/ℓ 을 1차환원제로 사용하였는바, 이러한 1차환원 조건은 2분동안 45℃로 가열하였다. 즉The black oxide oxidation surface (Na 2 CuO, Na 2 Cu 2 O) is washed in two stages with 70 ° C water and reduced to prevent penetration of acid (HCl, H 2 SO 4 ) in the plating process. There is a number. Thus, 1.5 g / l NaBH 4 and 5 g / l sodium hydroxide were used as primary reducing agents. The primary reducing conditions were heated to 45 ° C. for 2 minutes. In other words
이렇게 1차환원된 동박을 50℃의 물로 씻어낸다음 포르말린 2.5%와 5g/ℓ을 온도(67±5℃)와 시간(30초)동안 2차환원 시켰는바, 그에대한 반응식은 다음과 같다.The primary reduced copper foil was rinsed with water at 50 ° C., and 2.5% of formalin and 5 g / l were secondary reduced at a temperature (67 ± 5 ° C.) and for a time (30 seconds). The reaction formula is as follows.
이렇게 2차환원된 동박을 70±50℃의 물로 씻어낸 결과 내층에서 발생되는 핑크링은 종래의 300∼900㎛에서 30∼180㎛로 현저하게 감소되었다.As a result of washing the secondary reduced copper foil with water of 70 ± 50 ° C., the pink ring generated in the inner layer was significantly reduced from 300 to 900 μm to 30 to 180 μm.
따라서, 본 발명에 의해 제조된 다층 인쇄회로 기판은 납땜 및 고온의 열충격을 받더라도 내층의 동박면이 박리 또는 들뜨는 현상이 유발되지 않으므로 전기적특성 변화가 일어나지 않아 전자기기의 품질보증을 기할 수 있는 특징을 지닌 것이다.Therefore, the multilayer printed circuit board manufactured by the present invention does not cause peeling or lifting of the copper foil surface of the inner layer even when subjected to soldering and high temperature thermal shock, so that the electrical property does not change, which can guarantee the quality of the electronic device. I have it.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890012204A KR910007475B1 (en) | 1989-08-26 | 1989-08-26 | Multi - printed circuit board method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890012204A KR910007475B1 (en) | 1989-08-26 | 1989-08-26 | Multi - printed circuit board method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910005739A KR910005739A (en) | 1991-03-30 |
KR910007475B1 true KR910007475B1 (en) | 1991-09-26 |
Family
ID=19289284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890012204A KR910007475B1 (en) | 1989-08-26 | 1989-08-26 | Multi - printed circuit board method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR910007475B1 (en) |
-
1989
- 1989-08-26 KR KR1019890012204A patent/KR910007475B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR910005739A (en) | 1991-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3742597A (en) | Method for making a coated printed circuit board | |
US20060255009A1 (en) | Plating method for circuitized substrates | |
KR100522377B1 (en) | Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus | |
US6742250B2 (en) | Method of manufacturing wiring substrate | |
US3483615A (en) | Printed circuit boards | |
KR20010009975A (en) | Method of producing a multi-layer printed-circuit board | |
US6651324B1 (en) | Process for manufacture of printed circuit boards with thick copper power circuitry and thin copper signal circuitry on the same layer | |
EP0476065B1 (en) | Method for improving the insulation resistance of printed circuits | |
JPS59215793A (en) | Method of reproducing copper conductor with defect on outer surface of outer layer circuit | |
KR910007475B1 (en) | Multi - printed circuit board method | |
JP2005354030A (en) | Manufacturing method of circuit board | |
JPH05327224A (en) | Manufacture of multilayer wiring board and multi-layer wiring board manufactured by the manufacture | |
JP4589519B2 (en) | Manufacturing method of semiconductor circuit components | |
JP2003115662A (en) | Method of manufacturing semiconductor device substrate | |
JPH1187886A (en) | Production of printed wiring board | |
JP3304061B2 (en) | Manufacturing method of printed wiring board | |
JPH06132630A (en) | Manufacture of flexible circuit board | |
KR100319819B1 (en) | Method of producing a multi-layer printed-circuit board for a RF power amplifier | |
KR100403761B1 (en) | Fabrication method of high reliability printed circuit board | |
TWI700022B (en) | Metal etchback process for circuit board and metal-etchback-treated circuit board | |
JP2002271026A (en) | Multi-layer printed wiring board and manufacturing method therefor | |
JP2002009436A (en) | Manufacturing method for printed wiring board | |
KR930000639B1 (en) | Manufacturing method of multi layer printed circuit board | |
JP2712997B2 (en) | Solder resist processing method in manufacturing printed wiring board | |
KR930000640B1 (en) | Manufacturing method of multi layer printed circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20000920 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |