KR910007116B1 - Mosfet device - Google Patents

Mosfet device Download PDF

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KR910007116B1
KR910007116B1 KR1019890001767A KR890001767A KR910007116B1 KR 910007116 B1 KR910007116 B1 KR 910007116B1 KR 1019890001767 A KR1019890001767 A KR 1019890001767A KR 890001767 A KR890001767 A KR 890001767A KR 910007116 B1 KR910007116 B1 KR 910007116B1
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oxide film
metal
film
gate electrode
silicide
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KR1019890001767A
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KR900013646A (en
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김재갑
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현대전자산업 주식회사
정몽헌
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The MOSFET oxidizes the metal having no silicide selectively without etching so that the characteristic is improved. The metal oxide layer (9) is formed on the side wall of the spacer oxide layer (6) and the upper side of the element isolation oxide layer (2). The metal oxide is an insulator oxidized the metal layer.

Description

MOSFET 소자MOSFET device

제1도는 종래기술에 의한 실리사이드가 형성되고 금속층은 제거시킨 상태의 단면도.1 is a cross-sectional view of a state in which silicide is formed according to the prior art and a metal layer is removed.

제2도 내지 제5도는 본 발명의 공정과정을 나타낸 단면도.2 to 5 are cross-sectional views showing the process of the present invention.

제2도는 실리콘 기판 상부에 소자분리 산화막과 게이트 전극이 형성된 상태의 단면도.2 is a cross-sectional view of a device isolation oxide film and a gate electrode formed on a silicon substrate.

제3도는 게이트 전극, 소자분리산화막 및 실리콘 기판 상부에 금속막 및 산화막을 각각 형성시킨 상태의 단면도.3 is a cross-sectional view of a metal film and an oxide film formed on the gate electrode, the device isolation oxide film, and the silicon substrate, respectively.

제4도는 열처리 공정으로 실리사이드를 형성시킨 상태의 단면도.4 is a cross-sectional view of the silicide formed by the heat treatment step.

제5도는 산화막을 제거한 상태의 최종공정 단면도.5 is a final cross-sectional view of the state in which the oxide film is removed.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 소자분리 산화막1 silicon substrate 2 device isolation oxide film

3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode

5 : 소오스 및 드레인영역 6 : 스페이서용 산화막5: source and drain region 6: oxide film for spacer

7 : 금속막 8 : 실리사이드7: metal film 8: silicide

9 : 금속산화막 10 : 산화막 또는 질화막9: metal oxide film 10: oxide film or nitride film

본 발명은 고집적 반도체 소자의 MOSFET에 관한 것으로, 특히 자기정렬된 실리사이드 구조를 가지는 MOSFET 그 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MOSFETs of highly integrated semiconductor devices, and more particularly to MOSFET devices having self-aligned silicide structures.

MOSFET의 소오스 및 드레인영역 상부에 실리사이드 구조를 형성하고 비트선용 금속을 접속시키는 경우, 금속과 소오스 및 드레인영역을 직접 연결하였을 때 보다 접촉저항을 1/10 이하로 낮출 수 있어서 회로의 ＲＣ 지연시간을 단축시키고 전류의 전달능력을 향상시킬 수 있다.When the silicide structure is formed on the source and drain regions of the MOSFET and the bit line metal is connected, the contact resistance can be lowered to 1/10 or less than when the metal and the source and drain regions are directly connected. It can shorten and improve the current carrying capacity.

종래에는 실리사이드 구조를 형성하기 위하여, 게이트 전극 주위에 스페이서 산화막을 형성하고 소자분리 산화막, 소오스 및 드레인영역 및 게이트 전극 상부에 금속막을 일정두께로 침착하고 열처리하게 되면, 실리콘 기판 상부와 게이트 전극 상부에 실리사이드가 형성되고 스페이서용 산화막 측면과 소자분리 산화막 상부에는 실리사이드가 형성되지 않게 되며, 실리사이드가 형성되지 않은 금속은 식각공정을 이용하여 식각시켰는데, 이러한 공정방법을 실시할때에 선택적으로 금속막이 식각되는 경우에만 가능하며 또한 선택적으로 식각되는 금속의 경우, 그 금속 실리사이드가 고온에서 열적 불안정성 또는 강한 스트레스를 가지고 있어 소자의 특성이 좋지 못하였다.Conventionally, in order to form a silicide structure, a spacer oxide film is formed around the gate electrode, and a metal film is deposited to a predetermined thickness on the device isolation oxide film, the source and drain regions, and the gate electrode, and heat treated. Silicide is formed and silicide is not formed on the side of the oxide layer for the spacer and the upper part of the isolation oxide layer, and the metal without silicide is etched by using an etching process. In this process, the metal layer is selectively etched. In the case of a metal which is only possible and selectively etched, the metal silicide has thermal instability or strong stress at high temperature, which causes poor device properties.

따라서, 본 발명은 실리사이드가 형성되지 않은 금속을 식각처리하지 않고 선택적으로 산화시켜 금속산화막으로 변화시킴으로서 종래의 선택적으로 식각되지 않는 금속을 이용할 수 있으며 소자의 특성을 향상시킨 소자를 제공하는데 그 목적이 있다.Accordingly, the present invention can provide a device that can use a conventionally non-etched metal by selectively oxidizing the metal without the silicide is formed into an oxidized film without etching, thereby improving the characteristics of the device. have.

이하 본 발명을 첨부된 도면을 참고하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 종래 공정방법으로 실리사이드(8)가 게이트 전극(4), 소오스 및 드레인영역(5) 상부에 형성되고, 스페이서 산화막(6)측면과 소자분리 산화막(2) 상부에 금속막(9)을 제거시킨 상태의 단면도로서, 그 공정과정을 살펴보면, 실리콘 기판(1) 상부에 게이트 산화막(3)과 소자분리 산화막(2)를 형성하고, 게이트 전극(4)을 게이트 산화막(3) 상부에 선택적으로 일정부분 형성한 다음, 이온주입공정으로 소오스 및 드레인 영역(5)을 형성하고 게이트 전극(4)의 측면에 스페이서 산화막(6)을 형성한 후, 금속막(7)을 소오스 및 드레인영역(5)을 형성하고 게이트 전극(4) 및 소자분리 산화막(2) 상부에 침착한 후, 금속막(7) 상부에 산화막을 얇게 형성하고 열을 인가하여 금속막이 소오스 및 드레인영역(5) 상부와 게이트 전극(4) 상부에 스며들어 실리사이드(8)를 형성시킨 다음, 산화막을 제거하고 소자분리 산화막(2)과 스페이서용 산화막(6) 측면의 실리사이드가 형성되지 않은 금속막(7)을 제거한 상태의 단면도이다.1 shows a silicide 8 formed on the gate electrode 4, the source and drain regions 5, and the metal film 9 on the side of the spacer oxide film 6 and the device isolation oxide film 2 by a conventional process method. Is a cross-sectional view of the semiconductor substrate 1, in which the gate oxide film 3 and the device isolation oxide film 2 are formed on the silicon substrate 1, and the gate electrode 4 is disposed on the gate oxide film 3. After selectively forming a portion, the source and drain regions 5 are formed by an ion implantation process, and the spacer oxide layer 6 is formed on the side of the gate electrode 4, and then the metal layer 7 is formed on the source and drain regions. (5) and deposited on the gate electrode 4 and the device isolation oxide film 2, then a thin oxide film is formed on the metal film 7 and heat is applied to the metal film to the top of the source and drain regions 5. And soaking into the gate electrode 4 and forming the silicide 8 Next, a cross-sectional view of the state removing the oxide film and removal of the device isolation oxide film 2 and a spacer oxide film 6 is not formed a metal silicide film on the side (7).

제2도 내지 제5도는 본 발명의 공정과정을 순차적으로 나타낸 것으로, 상세히 설명하기로 한다.2 to 5 are shown sequentially the process of the present invention, it will be described in detail.

제2도는 실리콘 기판(1) 상부에 게이트 산화막(3)과 소자분리 산화막(2)를 형성하고 게이트 전극(4)을 게이트 산화막(3) 상부에 선택적으로 일정부분 형성한 다음, 이온주입으로 소오스 및 드레인영역(5) 형성하고 게이트 전극(4) 측면에 스페이서용 산화막(6)을 형성한 것이다.2 shows a gate oxide film 3 and a device isolation oxide film 2 formed on the silicon substrate 1, and a portion of the gate electrode 4 is selectively formed on the gate oxide film 3, and then sourced by ion implantation. And the drain region 5 and the spacer oxide film 6 is formed on the side of the gate electrode 4.

제3도는 소자분리 산화막(2), 소오스 및 드레인 영역(5) 및 게이트 전극(4) 상부에 금속막(7)과 산화막 또는 질화막(10)을 각각 소정의 두께로 형성한 것으로, 금속막(7) 상부에 산화막 또는 질화막(10)을 일정두께 형성하여 후공정에서 열공정으로 금속막(7)이 분위기 개스와 반응하지 못하도록 한 상태의 단면도이다.3 shows a metal film 7 and an oxide film or nitride film 10 formed on the device isolation oxide film 2, the source and drain regions 5, and the gate electrode 4, respectively, to a predetermined thickness. 7) It is a sectional view of the state which formed the oxide film or nitride film 10 in the upper part so that the metal film 7 may not react with an atmospheric gas by a thermal process in a later process.

제4도는 예를들어 400-800℃의 온도에서 열처리하여 금속막(7)이 소오스 및 드레인영역(5)내로 침투되어 실리사이드(10)가 형성된 상태의 단면도이다.4 is a cross-sectional view of a state in which the silicide 10 is formed by infiltrating the metal film 7 into the source and drain regions 5 by performing heat treatment at a temperature of, for example, 400-800 ° C.

제5도는 상기 산화막 또는 질화막(10)을 완전히 제거하고 실리사이드가 형성되지 않은 상기 금속막(7)을 산화시켜 절연체로 작용하는 산화금속막(9)을 형성한 상태의 단면도이다. 이때 금속막(7)을 산화시키는 공정방법으로는 산소분위기에서 600-950℃ 정도의 온도를 인가하여 산화시키는 방법으로 한다.5 is a cross-sectional view of a state in which the oxide film or nitride film 10 is completely removed and the metal film 7 without silicide is oxidized to form a metal oxide film 9 serving as an insulator. At this time, a method of oxidizing the metal film 7 is to oxidize by applying a temperature of about 600-950 ℃ in the oxygen atmosphere.

상기와 같은 본 발명에 의하면, 금속막을 선택적으로 식각할 수 없는 경우에 이 금속을 산화막으로 변화시켜 절연체로서 작용하여 특성이 양호한 MOSFET 소자를 얻을 수 있는 커다란 효과가 있다.According to the present invention as described above, in the case where the metal film cannot be selectively etched, the metal is changed into an oxide film, which acts as an insulator, thereby producing a MOSFET device having good characteristics.

Claims (2)

실리콘 기판 상부에 소오스 및 드레인영역과 소자분리 산화막이 일정부분에 형성되고, 소오스 및 드레인영역 상부에 게이트 전극이 형성되며, 상기 게이트 전극 측면에 스페이서용 산화막이 형성되고 소오스 및 드레인 전극과 게이트 전극 상부에 실리사이드가 형성된 MOSFET 소자에 있어서, 스페이서 산화막 측면과 소자분기 산화막 상부에 금속산화막을 형성시킨 것을 특징으로 하는 MOSFET 소자.A source and drain region and a device isolation oxide film are formed on a portion of the silicon substrate, a gate electrode is formed on the source and drain regions, an oxide film for spacers is formed on the side of the gate electrode, and an upper portion of the source and drain electrodes and the gate electrode are formed. A MOSFET device having a silicide formed therein, wherein a MOSFET is formed on the side of the spacer oxide film and on the device branch oxide film. 제1항에 있어서, 스페이서 산화막 측면과 소자분리 산화막 상부의 금속산화막은 금속막이 산화된 절연체인 것을 특징으로 하는 MOSFET 소자.The MOSFET device according to claim 1, wherein the metal oxide film on the spacer oxide film side and the device isolation oxide film is an insulator in which the metal film is oxidized.
KR1019890001767A 1989-02-16 1989-02-16 Mosfet device KR910007116B1 (en)

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