KR910006745B1 - Contact window filling - up method - Google Patents

Contact window filling - up method Download PDF

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KR910006745B1
KR910006745B1 KR1019880009159A KR880009159A KR910006745B1 KR 910006745 B1 KR910006745 B1 KR 910006745B1 KR 1019880009159 A KR1019880009159 A KR 1019880009159A KR 880009159 A KR880009159 A KR 880009159A KR 910006745 B1 KR910006745 B1 KR 910006745B1
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layer
metal
connection window
intermediate layer
window
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KR1019880009159A
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KR900002401A (en
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박한수
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음.No content.

Description

[리프트오프 공정을 사용한 접속창 채움방법][Filling Connection Window Using Lift-Off Process]

[도면의 간단한 설명][Brief Description of Drawings]

제1도는 종래에 접속창을 형성하여 급속을 채우는 순서를 나타낸 공정도.1 is a process chart showing a procedure of filling a rapid by forming a connection window in the prior art.

제2도는 본 발명에 의하여 접속창을 형성한 후 금속을 채우는 순서를 나타낸 공정도이다.제2 is a process chart showing a procedure of filling a metal after forming a connection window according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 2, 3 : 도체 4,5,6 : 부도체1, 2, 3: conductor 4,5,6: insulator

7 : 포토리지스트 8 : 도체7: photoresist 8: conductor

9, 10 : 부분 11 : 평탄화층9, 10: part 11: planarization layer

12 : 중간층 13 : 포토리지스트12: middle layer 13: photoresist

14, 15 : 금속14, 15: metal

[발명의 상세한 설명]Detailed description of the invention

본 발명은 반도체 제조공정중 사진공정에 관한 것으로 특히, 다층포토리지스트 및 리프트업 공정을 이용하여 접속창(CONTACT)을 형성시킨 후 금속을 채우는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photographic process in a semiconductor manufacturing process, and more particularly, to a method of filling a metal after forming a contact window using a multilayer photoresist and a lift-up process.

반도체 공정이 진행되어 여러 가지 층과 패턴이 형성됨에 따라 실리콘기판상에 여러 가지 공정이 생기게 되는 것으로, 복잡한 회로의 초고밀도를 요하는 집적회로(VLSI)의 경우에 더 많은 공정이 필요해서 층도 많이 생기고 표면의 굴곡도 심해지게 된다.As the semiconductor process proceeds to form various layers and patterns, various processes are formed on the silicon substrate. In the case of an integrated circuit (VLSI) that requires extremely high density of complex circuits, more layers are required. There is a lot of surface curvature.

이러한 공정은 소자의 전기적 연결을 위하여 접속창을 형성시킨 후 금속과 연결시키기 위한 금속증착공정시 커다란 문제점을 야기시키게 된다.This process causes a big problem in the metal deposition process for connecting the metal after forming the connection window for the electrical connection of the device.

금속증착공정의 주요목적은 균일한 막의 적층에 있으며 표면에 굴곡이 생기는 경우 박막증착이 더욱 어려워지나, 균일한 막의 적층을 순조로운 전자이동과 높은 저항을 방지하기 위하여 필수적이다. 그러나 굴곡이 형성된 층에 접속창을 형성하여 금속박막을 덮은 경우 끊어짐현상이 발생되는 것으로 제1도에 의하여 설명하면 다음과 같다.The main purpose of the metal deposition process is to deposit a uniform film, and thin film deposition becomes more difficult when bending occurs on the surface. However, the deposition of a uniform film is essential to prevent smooth electron migration and high resistance. However, when the connection window is formed on the bent layer to cover the metal thin film, breakage may occur. Referring to FIG.

종래이 금속박막의 증착방법은 도체층(1)(2)(3)들과 부도체층(4)(5)위에 부도체층(6)을 도포할 때 굴곡이 형성된다. 즉, 도체층(1)과 도체층(2) 및 도체층(3)위에 부도체층(6)의 두께가 상이하게 되므로 그 위헤 도포되는 포토리지스트층(7)의 두께도 차이가 생기게 된다.In the conventional method of depositing a metal thin film, a bend is formed when the insulator layer 6 is applied on the conductor layers 1, 2, 3 and the insulator layers 4, 5. That is, since the thickness of the non-conductor layer 6 is different on the conductor layer 1, the conductor layer 2, and the conductor layer 3, the thickness of the photoresist layer 7 applied thereon also becomes different.

이 포토리지스트층(7)을 마스크로하여 식각공정을 행하면 (B)도와 같이 된다. 식각공정을 수행후 포톨지스트층(7)을 제거하게 되면 부도체층(6)의 두께(t1)(t2)(t3)의 차이로 인하여 접속창(W4)(W5)(W6)들의 종횡비가 달라지게 되므로 (C)도와 같이 금속증착시 금속이 끊어지는 부분(9)과 지나치게 두껍게 형성되는 부분(10)이 발생되어 균일한 층(스텝커버리지)가 나쁘게되는 원인이 되는 것이다.When the etching process is performed using the photoresist layer 7 as a mask, it is as shown in (B). When the potolst layer 7 is removed after the etching process, the aspect ratios of the connection windows W4, W5, and W6 are different due to the difference in the thicknesses t1, t2, and t3 of the insulator layer 6. As a result, as shown in (C), a portion 9 in which the metal is broken and a portion 10 formed too thick are generated, causing a uniform layer (step coverage) to be bad.

본 발명은 이와같은 문제점을 해결하기 위한 것으로 본 발명의 목적은 사진공정에서 다층 포토리지스트공정을 사용하여 기판상에 굴곡이 있는 곳에서도 사진공정 수행후 접속창으 크기변화를 최소화시키는 접속창 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to use a multilayer photoresist process in a photo process, a method for forming a splice window for minimizing the size change of a splice window after performing a photo process even in a curved area on a substrate. In providing.

본 발명의 또다른 목적은 금속막으 증착이 균일하게 증착시키기 위하여 자체정력 접속창 채움공정을 리프트오프공정으로 사용하여 금속막의 스텝커버리지를 향상시키는데 있다.Another object of the present invention is to improve the step coverage of the metal film by using the self-energetic access window filling process as a lift-off process in order to deposit the metal film uniformly.

이와 같은 목적은 포토리지스트층을 마스크로 하여 식각한 후 접속창이 형성되게 하고 미리 접속창내에 리프트오프공정을 사용하여 콘택트필링(Contact filling)을 시킨후 금속을 도포함으로써 달성될 수 있다.This object can be achieved by etching the photoresist layer as a mask to form a connection window and applying a metal after contact filling using a lift-off process in the connection window in advance.

본 발명의 특징은 굴곡이 형성된 부도체층위에 평탄화층 및 중간층을 형성하는 공정과, 상기 중간층위에 포토리지스트를 도포하여 접속창 패턴을 형성하는 공정과, 사아기 패턴에 따라 중간층 및 평탄화층을 식각시켜 접속창을 형성시키는 공정과, 포토리지스트층 제거후 금속층을 다중도포하는 공정과, 상기 평탄화층, 중간층, 중간층위의 금속을 리프트오프 방법으로 제거시키는 공정과, 상기 부도체층 및 금속이 채워진 접속창위에 금속을 도포시키는 공정으로 된것에 있다.Features of the present invention include the steps of forming a planarization layer and an intermediate layer on the insulator layer having the bending, forming a connection window pattern by applying a photoresist on the intermediate layer, and etching the intermediate layer and the planarization layer according to the frying pattern Forming a connection window; removing the photoresist layer; multi-coating the metal layer; removing the metal on the planarization layer, the intermediate layer, and the intermediate layer by a lift-off method; It is a process of applying metal on the connection window.

이하 본 발명의 실시예를 첨부된 도면에 따라서 상세하게 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제2도는 본 발명에 의하여 접속창을 형성한 후 금속을 채우는 순서를 나타내고 있다. 종래의 방법을 나타낸 제1도의 (A)(B)와 같이 도체층(1)(2)(3)과 부도체층(4)(5)을 형성시킨 후 부도체층(6)과 포토리지스트층(7)이 형성되게 한다.2 shows the procedure of filling the metal after the connection window is formed according to the present invention. After forming the conductor layers (1) (2) (3) and the insulator layers (4) (5) as shown in FIG. 1 (A) (B) of the conventional method, the insulator layer 6 and the photoresist layer are formed. (7) is formed.

그리고 (A)에 도시된 바와같이 굴곡이 형성된 부도체층(6)위에 포토리지스트를 도포시켜 평낱화층(11)이 형성되게 한후 상기 평탄화층위에 부도체인 중간층(12)을 형성시킨다. 여기서 중간층(12)을 형성하는 것은 후술한 바와같이 좋은 선택성을 얻고자 한다.Then, as shown in (A), a photoresist is applied on the insulator layer 6 having the bend to form the flattening layer 11, and then an intermediate layer 12, which is a nonconductor, is formed on the planarization layer. Forming the intermediate layer 12 here seeks to obtain good selectivity as described below.

다음에 포토리지스트층(13)을 형성하고 (B)에 도시된 바와같이 접속창 패턴을 형성한 후 상기 패턴을 중간층(12)과 평탄화층(11)을 식각시키면 (C)와 같이 접속창이 형성하게 된다.Next, after forming the photoresist layer 13 and forming the connection window pattern as shown in (B), the pattern is etched by the intermediate layer 12 and the planarization layer 11, and the connection window is formed as shown in (C). To form.

여기서 식각은 반응성 이온 식각(Teactive Ion Etching)공정을 사용하여 정밀한 언더컷트를 유지할 수 있게 gs다. 그후 포토리지스트층(13)을 제거하면 도면(C)와 같이 된다. 여기서 중간층(12)은 언더컷트된 평탄화층(11)에 대해 오우버행으로 이용되므로 (D)도와 같이 금속(14)을 도포후 리프트오프공정에 의하여 불필요한 부위를 제거하였을 때 부도체층(6)위에 금속이 남아있게되는 현상을 제거할 수 있는 좋은 선택성을 얻게된다.Etching here is gs to maintain precise undercut using a reactive ion etching process. Thereafter, the photoresist layer 13 is removed, as shown in the drawing (C). Since the intermediate layer 12 is used as an overhang for the undercut planarization layer 11, when the unnecessary portion is removed by the lift-off process after applying the metal 14 as shown in (D), the intermediate layer 12 is disposed on the insulator layer 6. Good selectivity to eliminate the phenomenon of metal remaining is obtained.

다음 공정으로 (D)에 도시된 바와같이 접속창 및 중간층위에 금속을 다중 도포한 후 평탄화층(11)과 중간층(12)과 중간층위의 금속(14)을 리프트오프공정으로 완전 제거하면 제2도(G)와 같이 되고, 이패턴위에 급속(15)을 도포하게 되면 제2도(F)에 도시된 바와같이 좋은 접속이 형성되고 금속의 스텝커버리지가 개선됨을 알 수 있다.In the following process, as shown in (D), the metal is multi-coated on the connection window and the intermediate layer, and then the planarization layer 11, the intermediate layer 12, and the metal 14 on the intermediate layer are completely removed by the lift-off process. As shown in Fig. G, the application of the rapid 15 over this pattern shows that a good connection is formed as shown in Fig. 2F and the step coverage of the metal is improved.

이상에서와 같이 본 발명은 종래의 기술에서 문제가 되었던 접속창의 종횡비창에 의한 금속연결이 끊어지는 현상을 다층 포토리지스트 및 자체정렬 접속창 채움을 이용한 리프트오프공정을 사용하여 제거할 수 있으며, 균일한 두께로 금속간의 연결을 기할 수가 있는 것이다. 따라서 비교적 공정의 단순화를 기하는 동시에 스텝커버리지가 우수하여 반도체 생산시 수율을 증가시킬 수 있는 효과가 있는 것이다.As described above, the present invention can eliminate the phenomenon of disconnection of the metal by the aspect ratio window of the connection window, which has been a problem in the prior art, by using a lift-off process using a multilayer photoresist and self-aligning connection window filling. It is possible to connect metals with a uniform thickness. Therefore, while relatively simplifying the process and excellent step coverage, there is an effect that can increase the yield in semiconductor production.

Claims (2)

다층 포토리스트 및 리프트오프 공정을 사용하여 균일한 접속창의 형성과 그 접속창에 금속을 채우는 연결방법에 있어서, 굴곡이 형성된 부도체층(6)위에 평탄화층(11) 및 중간층(12)을 형성시키는 공정과, 중간층(12)위에 포토리지스트(13)층을 도포하여 접속창 패턴을 형성시키는 공정과, 상기 패턴을 따라 중간층(12) 및 평탄화층(11)을 식각시켜 접속창을 형성시키는 공정과, 포토리지스트(13)층 제거후 금속층(14)을 다중도포하는 공정과, 상기 평탄화층(11), 중간층(12), 중간층위의 금속(14)을 리프트오프 방법으로 제거시키는 공정과, 상기 부도체층(6) 및 금속(14)이 채워진 접속창위에 금속(15)을 도포시키는 공정으로된 리프트오프 공정을 사용한 접속창 채움방법.In the method of forming a uniform connection window and a metal filling method for the connection window using a multilayer photolist and a lift-off process, the planarization layer 11 and the intermediate layer 12 are formed on the insulator layer 6 on which the bending is formed. Forming a connection window pattern by applying a layer of photoresist 13 on the intermediate layer 12; and forming a connection window by etching the intermediate layer 12 and the planarization layer 11 along the pattern. And multi-coating the metal layer 14 after removing the photoresist layer 13, removing the planarization layer 11, the intermediate layer 12, and the metal 14 on the intermediate layer by a lift-off method. And a method of filling a splice window using a lift-off process in which a metal (15) is applied onto the splice window filled with the insulator layer (6) and the metal (14). 제1항에 있어서, 상기 패턴을 따라 중간층(12) 및 평탄화층(11)을 식각시켜 접속창을 형성시키는 공정은 반응성 이온에칭(Reactive Ion Etching)공정으로 정밀도를 요하는 식각을 하여 접속창에 매몰될 금속층이 일정한 두께로 유지될 수 있게한 리프트오프 공정을 사용한 접속창 채움방법.The method of claim 1, wherein the process of forming the connection window by etching the intermediate layer 12 and the planarization layer 11 along the pattern is performed using a reactive ion etching process to perform an etching requiring precision on the connection window. A method of filling junction windows using a lift-off process that allows the metal layer to be buried to be maintained at a constant thickness.
KR1019880009159A 1988-07-21 1988-07-21 Contact window filling - up method KR910006745B1 (en)

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