KR910001562A - Multiplex Processor Communication Control Circuit Using Multiport Memory - Google Patents

Multiplex Processor Communication Control Circuit Using Multiport Memory Download PDF

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Publication number
KR910001562A
KR910001562A KR1019890009070A KR890009070A KR910001562A KR 910001562 A KR910001562 A KR 910001562A KR 1019890009070 A KR1019890009070 A KR 1019890009070A KR 890009070 A KR890009070 A KR 890009070A KR 910001562 A KR910001562 A KR 910001562A
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KR
South Korea
Prior art keywords
processors
multiplexed
control circuit
port memory
mux4
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Application number
KR1019890009070A
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Korean (ko)
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KR910008416B1 (en
Inventor
한상천
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정용문
삼성전자 주식회사
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Priority to KR1019890009070A priority Critical patent/KR910008416B1/en
Publication of KR910001562A publication Critical patent/KR910001562A/en
Application granted granted Critical
Publication of KR910008416B1 publication Critical patent/KR910008416B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Abstract

내용 없음No content

Description

멀티포트 메모리를 이용한 다중화 프로세서간 통신 제어회로Multiplex Processor Communication Control Circuit Using Multiport Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 본 발명에 따른 회로도,1 is a circuit diagram according to the invention,

제 2도는 본 발명에 따른 제 1도의 멀티포트 메모리제어부(100)의 구체회로도.2 is a detailed circuit diagram of the multi-port memory control unit 100 of FIG. 1 according to the present invention.

Claims (2)

다중화된 제1,2프로세서간 데이터 통신 제어회로에 있어서, 상기 다중화된 제1,2프로세서(CPU1-CPU2)에서 출력되는 어드레스 및 제어신호를 멀티플렉싱하는 제1-4멀티플렉셔(MUX1-MUX4)와, 상기 제1-4멀티플렉셔(MUX1-MUX4)에서 발생되는 어드레스(A0-A1)와 제어신호에 의해 제어되어 상기 다중화된 제1,2프로세서(CPU1-CPU2)간의 데이터 전송을 위한 창구역할을 하는 멀티포트 메모리(MMR)와, 상기 멀티포트 메모리(MMR)로부터 출력되는 데이터를 설정되는 방향에 따라 상기 다중화 프로세서(CPU1, CPU2)로 전달하는 제1,2전송 드라이버(TVR1,TVR2)와, 상기 다중화된 PW1,2프로세서(CPU1,CPU2)로부터 발생되는 상기 멀티 포트 메모리(MMR)의 억세스 신호에 의해 상기 멀티플렉서(MUX1-MUX4)의 선택신호 및 상기 제1,2전송드라이버(VTR1,VTR2)의 인에이블 및 데이터 전송 방향을 결정하는 선택 제어신호를 발생하는 멀티포트 메모리 제어부(100)로 구성됨을 특징으로 하는 멀티포트 메모리를 이용한 다중화 프로세서간 통신 제어회로.A data communication control circuit between multiplexed first and second processors, comprising: a first to fourth multiplexer (MUX1 to MUX4) for multiplexing an address and a control signal output from the multiplexed first and second processors (CPU1 to CPU2); And the address A0-A1 and the control signal generated in the first to fourth multiplexers MUX1 to MUX4. Controlled by the multi-port memory (MMR) to control the window area for data transfer between the multiplexed first and second processors (CPU 1-CPU 2) and the data output from the multi-port memory (MMR) in a direction to be set. Accordingly, access signals of the first and second transmission drivers TVR1 and TVR2 to the multiplexing processors CPU1 and CPU2 and the multi-port memory MMR generated from the multiplexed PW1 and 2 processors CPU1 and CPU2. The multiport memory controller 100 generates a selection signal of the multiplexers MUX1 to MUX4 and a selection control signal for determining the enable and data transfer directions of the first and second transfer drivers VTR1 and VTR2. Multiplex processor communication control circuit using a multi-port memory characterized in that. 제 1항에 있어서, 멀티포트 메모리제어부(100)가 상기 다중화된 제1,2프로세서(CPU1,CPU2)의 억세스 제어단(PAA,PBA)이 플립플롭(F/F)의 세트(S) 및 리세트(R)에 연결됨과 동시에 오아게이트(OR1-OR2)의 입력단에 연결되고, 상기 클립플롭(F/F)의 출력단(Q)이 상기 오아게이트(OR1-OR2)의 입력단에 연결함과 동시에 상기 제1,2전송 드라이버(VTR1,VTR2)의 인에이블단과 상기 멀티플렉셔(MUX1-MUX4)의 칩 선택단에 연결하고, 상기 오아게이트(OR1,OR2)의 출력단이 상기 제1,2전송 드라이버(TVR1,TVR2)의 데이터 전송방향 결정단(DIR)에 연결되도록 구성됨을 특징으로 하는 멀티포트 메모리를 이용한 다중화 프로세서간 통신 제어회로.The multi-port memory control unit 100 of claim 1, wherein the access control stages (PAA, PBA) of the multiplexed first and second processors (CPU1, CPU2) is a set (S) of flip-flop (F / F) and Is connected to the reset (R) and at the same time the input terminal of the oragate (OR1-OR2), the output terminal (Q) of the clip-flop (F / F) is connected to the input terminal of the oragate (OR1-OR2) and Simultaneously enable the first and second transfer drivers VTR1 and VTR2 And chip select stages of the multiplexer (MUX1-MUX4) Multiplexing using a multiport memory, wherein the output terminals of the OR gates OR1 and OR2 are connected to the data transmission direction determining terminal DIR of the first and second transmission drivers TVR1 and TVR2. Interprocessor communication control circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890009070A 1989-06-29 1989-06-29 Circuit for controlling communication among multi-processors using multiport memory KR910008416B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890009070A KR910008416B1 (en) 1989-06-29 1989-06-29 Circuit for controlling communication among multi-processors using multiport memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890009070A KR910008416B1 (en) 1989-06-29 1989-06-29 Circuit for controlling communication among multi-processors using multiport memory

Publications (2)

Publication Number Publication Date
KR910001562A true KR910001562A (en) 1991-01-31
KR910008416B1 KR910008416B1 (en) 1991-10-15

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KR1019890009070A KR910008416B1 (en) 1989-06-29 1989-06-29 Circuit for controlling communication among multi-processors using multiport memory

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KR (1) KR910008416B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100310298B1 (en) * 1999-07-09 2001-11-03 오길록 Data transmission control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100310298B1 (en) * 1999-07-09 2001-11-03 오길록 Data transmission control circuit

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Publication number Publication date
KR910008416B1 (en) 1991-10-15

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