KR900015371A - Double-gate amorphous silicon thin film transistor and its manufacturing method - Google Patents

Abstract

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Description

Double-gate amorphous silicon thin film transistor and its manufacturing method

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2 is a cross-sectional view of the present invention dual gate type amorphous silicon thin film transistor.

Claims (2)

After the lower gate electrode 12 and the lower gate insulating layer 13 are formed on the glass substrate 11, the drain electrode 15a, the source electrode 15b, and the n ⁺ amorphous silicon layer 14 are sequentially stacked. And the upper gate electrode 18 of the amorphous silicon layer 16 and the upper gate insulating layer 17 are sequentially formed on the lower gate insulating layer 13 and the n ⁺ amorphous silicon layer l4 at the central portion. A double gate amorphous silicon thin film transistor. After the lower gate electrode 12 and the lower gate insulating layer 13 are stacked on top of the glass period, chromium is deposited by an electron beam method, and Si ⁺ ₄ and PH ₃ gases are decomposed by PE-CVD at high frequency to n ⁺ amorphous. After forming the silicon layer 14 and dry etching the n ⁺ amorphous silicon layer 14 by the RIE method, the chromium is etched by the wet etching method to extract the drain electrode 15a and the source electrode 15b, High-frequency decomposition of SiH ₄ by PE-CVD on the n ⁺ amorphous silicon layer 14 and the lower gate insulating layer 13 to deposit a silicon silicon layer 16 by PE-CVD, and again SiH ₄ and NH ₃ by PE-CVD. The double-gate amorphous silicon thin film is formed by a process of forming a top gate insulating layer 17 by high-frequency decomposition and depositing amorphous silicon nitride, and forming an upper gate electrode 18 by depositing AI with an electron beam. Fabrication of transistors Law. ※ Note: This is to be disclosed based on the first application.