KR900013388A - 신경회로망을 이용한 곱셈기 회로 - Google Patents

신경회로망을 이용한 곱셈기 회로 Download PDF

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Publication number
KR900013388A
KR900013388A KR1019890001368A KR890001368A KR900013388A KR 900013388 A KR900013388 A KR 900013388A KR 1019890001368 A KR1019890001368 A KR 1019890001368A KR 890001368 A KR890001368 A KR 890001368A KR 900013388 A KR900013388 A KR 900013388A
Authority
KR
South Korea
Prior art keywords
neural network
multiplier circuit
circuit
multiplier
output
Prior art date
Application number
KR1019890001368A
Other languages
English (en)
Other versions
KR920007505B1 (ko
Inventor
정호선
Original Assignee
정호선
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정호선 filed Critical 정호선
Priority to KR1019890001368A priority Critical patent/KR920007505B1/ko
Priority to US07/473,633 priority patent/US5095457A/en
Publication of KR900013388A publication Critical patent/KR900013388A/ko
Application granted granted Critical
Publication of KR920007505B1 publication Critical patent/KR920007505B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/40—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
    • G06F7/44—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

내용 없음

Description

신경회로망을 이용한 곱셈기 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 회로도,
제2도는 제1도에 있어서, 7-입력 1′s카운터 회로.

Claims (1)

  1. 승수(A0-A4)와 피승수(B0-B4)와 각 비트의 곱셈을 위한 AND 게이티와 NMOS와 PMOS어레이 회로와 두개인 인버터와 1′s COUNTER CIRCUIT의 출력(A0-A2)과 곱셈회로의 출력(P0-P9)을 포함하여 이루어지는 것을 특징으로 하는 신경회로망을 이용한 곱셈기 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890001368A 1989-02-02 1989-02-02 신경회로망을 이용한 곱셈기 KR920007505B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019890001368A KR920007505B1 (ko) 1989-02-02 1989-02-02 신경회로망을 이용한 곱셈기
US07/473,633 US5095457A (en) 1989-02-02 1990-02-01 Digital multiplier employing CMOS transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890001368A KR920007505B1 (ko) 1989-02-02 1989-02-02 신경회로망을 이용한 곱셈기

Publications (2)

Publication Number Publication Date
KR900013388A true KR900013388A (ko) 1990-09-05
KR920007505B1 KR920007505B1 (ko) 1992-09-04

Family

ID=19283644

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890001368A KR920007505B1 (ko) 1989-02-02 1989-02-02 신경회로망을 이용한 곱셈기

Country Status (2)

Country Link
US (1) US5095457A (ko)
KR (1) KR920007505B1 (ko)

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Also Published As

Publication number Publication date
US5095457A (en) 1992-03-10
KR920007505B1 (ko) 1992-09-04

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