ATE96556T1 - Inkrementierer und dekrementierer. - Google Patents

Inkrementierer und dekrementierer.

Info

Publication number
ATE96556T1
ATE96556T1 AT87305226T AT87305226T ATE96556T1 AT E96556 T1 ATE96556 T1 AT E96556T1 AT 87305226 T AT87305226 T AT 87305226T AT 87305226 T AT87305226 T AT 87305226T AT E96556 T1 ATE96556 T1 AT E96556T1
Authority
AT
Austria
Prior art keywords
signal
section
input
carry
generating
Prior art date
Application number
AT87305226T
Other languages
English (en)
Inventor
Yousef Vazir-Zadeh
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE96556T1 publication Critical patent/ATE96556T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Steroid Compounds (AREA)
  • Logic Circuits (AREA)
  • Calculators And Similar Devices (AREA)
AT87305226T 1986-06-20 1987-06-12 Inkrementierer und dekrementierer. ATE96556T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/876,494 US4698831A (en) 1986-06-20 1986-06-20 CMOS incrementer cell suitable for high speed operations
EP87305226A EP0250174B1 (de) 1986-06-20 1987-06-12 Inkrementierer und Dekrementierer

Publications (1)

Publication Number Publication Date
ATE96556T1 true ATE96556T1 (de) 1993-11-15

Family

ID=25367848

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87305226T ATE96556T1 (de) 1986-06-20 1987-06-12 Inkrementierer und dekrementierer.

Country Status (5)

Country Link
US (1) US4698831A (de)
EP (1) EP0250174B1 (de)
JP (1) JPS633335A (de)
AT (1) ATE96556T1 (de)
DE (1) DE3787931T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090292757A1 (en) * 2008-05-23 2009-11-26 Steven Leeland Method and apparatus for zero prediction

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US560488A (en) * 1896-05-19 Car-brake
US4280190A (en) * 1979-08-09 1981-07-21 Motorola, Inc. Incrementer/decrementer circuit
US4417316A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Digital binary increment circuit apparatus
US4419762A (en) * 1982-02-08 1983-12-06 Sperry Corporation Asynchronous status register
US4464774A (en) * 1982-03-15 1984-08-07 Sperry Corporation High speed counter circuit
US4495628A (en) * 1982-06-17 1985-01-22 Storage Technology Partners CMOS LSI and VLSI chips having internal delay testing capability
US4587665A (en) * 1982-10-15 1986-05-06 Matsushita Electric Industrial Co., Ltd. Binary counter having buffer and coincidence circuits for the switched bistable stages thereof
US4611337A (en) * 1983-08-29 1986-09-09 General Electric Company Minimal logic synchronous up/down counter implementations for CMOS

Also Published As

Publication number Publication date
US4698831A (en) 1987-10-06
EP0250174A2 (de) 1987-12-23
DE3787931D1 (de) 1993-12-02
JPS633335A (ja) 1988-01-08
EP0250174B1 (de) 1993-10-27
EP0250174A3 (en) 1990-07-11
DE3787931T2 (de) 1994-04-21

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties