KR900004047B1 - Image data input control circuit - Google Patents

Abstract

The circuit for controlling input tining of video data utilizing field synchronous signal divided from composite video signal so that one field's video data is stored and processed includes a video input controller (40) for controlling I/O signal according to output signal of a key input signal (30) so that video signal is processed, for inputting field synchronous signal transmitted from a synchronous processor (20) according to a video input control signal, and for transmitting digital video data select signal, and a multiplexer (50) for selecting address transmitted from a signal processor (20) and video data of an A/D converter (23) according to the digital video data select signal.

Description

Image data input control circuit

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of one embodiment of the FIG. 1 block diagram.

3 is an operational waveform diagram of FIG.

4 is an operation flowchart of the image data input control circuit of FIG.

<Explanation of symbols for the main parts of the drawings>

10: video signal output unit 20: synchronization signal processing unit

23: A / D conversion unit 30: Key input unit

40: image input control unit 50: multiplexer

60: memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data input control circuit of an image processing apparatus, and in particular, detects and synchronizes a field synchronization signal from a composite synchronization signal loaded on an image signal. The invention relates to a circuit for accurately controlling image input by means of.

In general, image processing is intended to achieve the purpose of image conversion, recall measurement, pattern recognition, image generation, etc., and in recent years, there is a rapid development. In addition, in the image processing apparatus, an image input circuit for converting and inputting a video signal into a digital signal is essentially used to achieve the above object.

The conventional image input circuit simply converts an input image signal into digital data as a clock pulse extracted from a vertical / horizontal synchronization signal and stores it in a memory. That is, the image signal was converted into a digital video signal from the start of the image signal input and stored for one screen as a digital signal in the memory.

Therefore, when the image signal input start signal is input in the middle of one screen, a problem arises in that the image input start point is irregular and the resolution of the image falls.

Accordingly, an object of the present invention is to convert an image signal into a digital image signal, store it in a memory, process the image signal, and then, in the image processing window, extract the synchronized sync signal carried in the composite image signal and thereby control the timing of inputting the image data. There is provided an image data input control circuit for controlling the control.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram according to the present invention, and includes a video signal output unit 10 for inputting various images to output a composite video signal (hereinafter referred to as CVS), and a vertical / horizontal synchronizer for inputting the CVS. The sync signal processor 20 generates a clock and an address by separating a signal and outputting a feed sync signal, and generating a clock and an address, and an analog composite video signal of the video signal output unit 10. A / D conversion (Analog to Digital Converter) unit 23 for converting and outputting digital data by the clock generated by the synchronization signal processing unit 20, and an image input control signal and an image processing signal are generated by pressing a key. To control the image processing by controlling the input / output signal according to the key input unit 30 and the output of the key input unit 30, and at the same time the feed synchronization signal of the synchronization signal processing unit 20 by the input of the image input control signal. Is inputted to the image input control unit 40 for outputting a selection signal for selecting one-fidelity digital image data from the A / D conversion unit 23, and to the selection signal output from the image input control unit 40. The multiplexer 50 selects the address of the synchronization signal processing unit 20 and the image data of the A / D converter 23, and stores the image data in the address output from the multiplexer 50, and at the same time the image input control unit ( The memory unit 60 accesses the program data and the image data under the control of 40.

Now, when the CVS output from the video signal output section 10 is input to the synchronization signal processing section 20 and the A / D conversion section 23, respectively, the synchronization signal processing section 20 performs the vertical synchronization and horizontal synchronization signals loaded on the CVS. Outputs the even and odd feed sync signals to the image input controller 40 and counts the separated vertical / horizontal sync signals to convert the clock and address signals to the A / D converter 23 and the multiplexer 50. )

On the other hand, the A / D converter 23 that inputs the CVS of the video signal output unit 10 and the clock output from the synchronization signal processing unit 20 converts the CVS into a digital signal and outputs it to the multiplexer 50.

When the image input control signal is output from the key input unit 30 to the image input control unit 40 under the above operation, the image input control unit 40 stops the current operation and outputs from the synchronization signal processing unit 20. The multiplexer 50 inputs one feed image data, which is converted and output from the A / D conversion section 23 and a selection signal for selecting an address of the synchronization signal processing section 30, by the input of the synchronization signal. .

Therefore, the multiplexer 50 outputs the address output from the synchronization signal processing section 20 and the one-fidelity image data converted by the A / D conversion section 23 to the memory section 60. In step 60, the one-pixel image data converted into the address generated by the synchronization signal processing unit 20 is stored. Therefore, the image data recorded in the memory unit 60 is accurately recorded from the start of one feed.

After the image signal for one feed is converted into digital data as described above, when an image processing signal is generated from the key input unit 30 and input to the image input control unit 40, the image input control unit 40 is the memory unit 60. Access data for executing a predetermined program.

The image input controller 40 reading the program data outputs a predetermined address signal and a selection signal for reading the image data to the multiplexer 50. As a result, the multiplexer 50 outputs an address output from the image input controller 40. Is outputted to the memory unit 60, and outputs one feed of image data to the image input control unit 40 through the multiplexer 50. At this time, the image input controller 40 performs image processing on the input image signal data according to a program.

를 출력하는 낸드게이트(43)와, 상기 A/D변환 요구 신호(ADRQ)를 동기 분리부(21)의 피일드 동기 신호로 래치하여 브렌치 제어입력신호(Branch Contro1 Input)

를 출력하는 래치회로(44)로 구성된 화상 입력제어부(40)와, 상기 마이컴(41)의 홀드 응답신호(Hold acknowledge :

출력에 의해 어드레스 발생부(22)의 어드레스와 A/D변환부(23)의 출력을 각각 선택 출력하는 어드레스 멀티플렉서(51)와 영방향인 데이터 멀티플렉서(52)로 구성된 멀티플렉서(50)와, 상기 어드레스 멀티플렉서(51)에서 출력하는 어드레스신호에 의해 데이터 멀티플렉서(52)로 입출력하는 데이터를 엑세스 하는 데이터 메모리부(61)와, 시스템 동작 프로그램을 저장하고 있어 마이컴(41)의 제어에 의한 프로그램 데이터를 출력하는 프로그램 메모리부(62)로 구성된다. 상기 제 2 도의 구성중 데이터 메모리부(61)와 프로그램 메모리부(62) 각각의 어드레스 단자와 데이터 단자를 제 1, 제 2어드레스 단자 및 제 1, 제 2데이터 단자라 칭한다.FIG. 2 is a detailed circuit diagram of an embodiment of FIG. 1, which separates and outputs a video signal output unit 10 and a vertical / horizontal sync signal among the CVS signals of the video signal output unit 10, and at the same time outputs a feed sync signal. A synchronization signal processing unit 20 including an synchronization generator 21 for performing a counting and outputting a clock CLK and an address signal by counting a horizontal / vertical synchronization signal of the synchronization separator 21; An A / D converter 23 for sampling the CVS of the video signal output unit 10 at the clock CLK time of the address generator 22 and converting the CVS into a digital signal; an image input control signal and an image processing signal; Key input unit 30 for outputting by pressing a key, a microcomputer 41 for controlling various input / output signals and a system by the key input signal, and an A / D conversion request signal among the output control signals of the microcomputer 41; (Analong to Digital Converter Request: ADRQ) buffered output A buffer 42 for buffering an input signal at a time, an A / D conversion request signal ADRQ of the buffer 42 and an output of the feedback synchronization signal of the synchronization separator 21 by a negative logic to mimic the microcomputer 41. Hold signal to

And a branch control input signal (Branch Contro1 Input) by latching the NAND gate 43 for outputting the signal and the A / D conversion request signal ADRQ as a feed synchronization signal of the synchronization separation unit 21.

An image input control unit 40 including a latch circuit 44 for outputting a signal and a hold acknowledgment signal of the microcomputer 41;

A multiplexer 50 composed of an address multiplexer 51 for selectively outputting an address of the address generator 22 and an output of the A / D converter 23 by an output, and a data multiplexer 52 in the zero direction; A data memory unit 61 for accessing data input / output to the data multiplexer 52 by an address signal output from the address multiplexer 51 and a system operation program are stored. It consists of the program memory part 62 which outputs. The address terminal and the data terminal of each of the data memory unit 61 and the program memory unit 62 in the configuration of FIG. 2 are referred to as first and second address terminals and first and second data terminals.

이다. (D)는 마이컴(41)의 출력으로서 홀드 응답 신호

이다. (E)는 래치회로(44)의 출력으로서 브렌치 제어 입력신호

이다.3 is a partial operation waveform diagram of FIG. 2, wherein (A) is a feed sync signal as an output of the sync separator 21. As shown in FIG. (B) is an A / D conversion request signal ADRQ as an output of the microcomputer 41. (C) is a hold signal as an output of the NAND gate 43.

to be. (D) is a hold response signal as an output of the microcomputer 41;

to be. (E) is a branch control input signal as an output of the latch circuit 44.

to be.

4 is an operation flowchart of FIG. 2, in which an image input control signal outputs an A / D conversion request signal ADRQ at the time of input, and then transfers the image data to the data memory unit 61 from an odd field signal. It is a process of searching for completion of writing and stopping input of image data upon completion.

An operation example of FIG. 2 according to the present invention will be described in detail with reference to the operation waveform diagram of FIG. 3 and the operation flowchart of FIG.

After receiving various images from the video signal output unit 10 and performing signal processing, CVS is input to the input terminal CVS1 of the synchronization separator 21 and the analog signal input terminal Ain of the A / D converter 23. In other words, the synchronization separator 21 separately extracts the horizontal synchronization signal HS and the vertical synchronization VS signal from the CVS, and outputs them to the address generator 22 through the output terminals HS and VS. In addition, the clock synchronization signal CK and the NAND gate of the latch circuit 44 are outputted through the output terminal F through the output terminal F. A shield synchronization signal for distinguishing the even and odd feedback signals as shown in FIG. 43).

On the other hand, the address generator 22 that inputs the horizontal / vertical synchronization signal HS (VS) counts the horizontal / vertical synchronization signal HS and the clock CLK by two counters therein. It outputs to the sampling clock of the / D conversion section 23 and counts pixel positions in one frame period and outputs an address signal to the address output terminal ADPO.

Therefore, the address of the address generator 22 and the digital image data of the A / D converter 23 are input to the input terminal IN2 of the address multiplexer 51 and the input terminal IN1 of the data multiplexer 52, respectively.

"로우"의 홀드

신호를 T1점에서 발생하여 마이컴(41)을 홀딩(Holding)시킨다. 그러므로 마이컴(41)은 제 4 도의 (4-3)과정으로 진행하여 브렌치 제어 입력신호가 "로우"인가를 계속적으로 판단한다. 그리고 마이컴(41)의 A/D변환 요구신호(ADRQ)가 제 3 도(b)와 같이 동기분리부(21)에서 우수 피일드 동기 신호가 출력된 후 T1점에서 출력되어서, 래치회로(44)의 반전출력단자에서 출력되는 제 3도(e)와 같은 브렌치제어 입력신호(Branch Control Input :

)가 "하이"상태로 입력됨으로써 마이컴(41)은 1피일드분의 화상데이터의 시작이 아니라고 판단하여 홀드응답신호

를 출력치 않는다.In the state of operation as described above, the microcomputer 41 continuously checks whether a key is pressed in step (4-1) of FIG. 4 and an image input control signal is generated from the key input unit 30 to interrupt the microcomputer 41 ( When inputted as an Interrupt) signal, the microcomputer 41 stops the current operation, stores the operation state in the internal stack, and reads it out through the second address terminal and the second data terminal of the program memory unit 62. In order to perform the designated job, the process proceeds to step 4-2 of FIG. 4. In step (4-2) of FIG. 4, the A / D conversion request signal ADRQ as shown in FIG. 3 (b) is buffered through the buffer 42, and the one input terminal and the latch 44 of the NAND gate 43 are buffered. Output to the data input terminal (D). At this time, the NAND gate 43 inputs the even-numbered feed signal " high " of FIG. 3 (a) and the A / D conversion request (ADRQ) " high " Such as (P1)

Hold of "Low"

The signal is generated at the point T1 to hold the microcomputer 41. Therefore, the microcomputer 41 proceeds to (4-3) in FIG. 4 and continuously determines whether the branch control input signal is "low". The A / D conversion request signal ADRQ of the microcomputer 41 is outputted at the point T1 after the even-numbered feed sync signal is output from the sync separator 21 as shown in FIG. Branch control input signal (Branch Control Input) as shown in Figure 3 (e)

) Is input in the "high" state, the microcomputer 41 determines that the start of image data for one feed is not the start, and the hold response signal

Does not print.

가 논리 "하이"로 되며 마이컴(41)의 홀드상태를 해제하여 스택(Stack)에 저장시켜 놓은 프로그램을 실행하게 된다. 또한 자기 프레임의 우수 피일드(EV2)가 동기분리부(21)에서 출력되면 래치회로(44)는 마이컴(41)에서 출력하는 A/D변환 요구신호(ADRQ)를 래치하여 마이컴(41)에 입력되는 브렌치 제어 입력신호

를 "로우"의 신호로 출력하며, 낸드게이트(43)는 제 3 도(C)의 (P2)와 같은 T3점에서 "로우"상태가 되는 홀드

신호를 마이컴(41)으로 입력시킨다. 이때 마이컴(41)은 1프레임의 우수 피일드의 화상데이터가 A/D변환부(23) 에서 출력 한다고 판단하고 홀드

신호의 응답신호인 홀드응답신호

를 제 3 도(d)와 같이 T3점에서 "로우"로 하여 선택 신호로써 어드레스 멀티플렉서(51)와 데이터 멀티플렉서(52)의 셀렉터(Selector) 단(S)으로 입력시킨다.On the other hand, when the odd feed OD1 is output from the synchronization separator 21, the hold signal output from the NAND gate 43 is used.

Becomes logic "high" and the hold state of the microcomputer 41 is released and the program stored in the stack is executed. When the even-numbered feed EV2 of the magnetic frame is outputted from the synchronization separator 21, the latch circuit 44 latches the A / D conversion request signal ADRQ output from the microcomputer 41 to the microcomputer 41. Branch control input signal input

Is output as a "low" signal, and the NAND gate 43 is held in a "low" state at a point T3 equal to (P2) in FIG. 3C.

The signal is input to the microcomputer 41. At this time, the microcomputer 41 determines that the image data of the even-numbered feed of one frame is outputted from the A / D converter 23 and holds.

Hold response signal as response signal

As shown in Fig. 3 (d), " low " at the point T3 is input to the selector stage S of the address multiplexer 51 and the data multiplexer 52 as a selection signal.

가 "로우"인, T3점과 T4점의 구간에서 저장한다.Therefore, the address multiplexer 51 selects and outputs the address signal output from the address generator 22, and the data multiplexer 52 selects and outputs image data output from the A / D converter 23. The address specified by the address generator 22 and the image data of the A / D converter 23 are input to the first address terminal and the first data terminal. That is, the hold response signal of the even field EV2 shown in FIG.

Is stored in the interval between T3 and T4, where is "low".

를 출력하는 동기분리부(21)에서 기수피일드 동기신호(OD2)를 래치회로(44)와 낸드게이트(43)로 출력하면, 낸드게이트(43)는 제 3 도(c)의 (P2)와 같이 홀드신호를 "하이"논리로 출력함으로 우수 피일드가 끝나는 부분 즉, T4점에서 마이컴(41)은 홀딩상태에서 해제 되어진다. 이때 마이컴(41)은 제 4 도의 (4-5)과정으로 진행하여 래치회로(44)에서 출력되는 브렌치 제어입력 신호

가 "로우"인가를 검색하여 "로우"이면 1피일드에 대한 A/D변환된 화상 데이터의 입력이 완전히 이루어 졌다고 판단후 제 4 도의 (4-6)과정으로 진행한다. 상기 (4-6)과정에서 버퍼(Buffer)(42)로 출력하였던 A/D변환 요구신호(ADRQ)의 출력을 제 3 도(b)와 같이 T4점에서 "로우"로 출력하여 화상데이터의 입력명령을 완료한다.On the other hand, when the image data is stored in the data memory section 61 as described above, it is determined in step 4-3 of FIG. After determining whether the yield signal is completely input to the data memory unit 61, the process proceeds to step 4-4 of FIG. 4 to search for the present holding state. Also, the signal of the even field as shown in (EV2) in FIG.

When the odd-numbered sync signal OD2 is outputted to the latch circuit 44 and the NAND gate 43 by the synchronizing separator 21 for outputting the NAND gate 43, the NAND gate 43 is shown in FIG. As shown in FIG. 2, the microcomputer 41 is released in the holding state at the point where the excellent feed finishes, that is, the T4 point, by outputting the hold signal in a "high" logic. At this time, the microcomputer 41 proceeds to process (4-5) of FIG. 4 and outputs the branch control input signal output from the latch circuit 44.

Is "low" and if it is "low", it is determined that the input of the A / D converted image data for one feed is completely completed, and the process proceeds to (4-6) in FIG. The output of the A / D conversion request signal ADRQ, which has been output to the buffer 42 in step (4-6), is output as "low" at the point T4 as shown in FIG. Complete the input command.

는 다시 "하이"상태가 된다. 따라서 화상 입력제어부(40)의 제어신호에 의해 원하는 시점에서 정확히 1피일드의 화상데이터를 완전히 취득하게 되며 필요한 화상처리를 실시하게 된다.Next, the branch input signal at the point T5 of FIG. 3 (e) by the "high" input of the next excellent feedback EV3

Becomes "high" again. Therefore, the control signal of the image input control unit 40 completely acquires exactly one feed of image data at a desired point in time, and performs necessary image processing.

As described above, the present invention is an image processing apparatus, which is a circuit for accurately storing and processing one feed image by accurately controlling the input time of image data by using a shield synchronization signal outputted separately from a composite video signal. There is an advantage that the problem of image processing due to the poor image quality when processing the image data can be solved and the resolution can be improved.

Claims (2)

It has a video signal output unit 10 for inputting various images and outputting a composite video signal, and having first and second address terminals and first and second data terminals, which are converted into digital signals and are converted into the first data input terminals. The input image data is generated by counting horizontal and vertical synchronization signals and stored in a designated resistance region of an address input to the first address terminal, and the outputted data is read out by a predetermined control and input to the second address terminal. An image input control circuit having a memory unit 60 for accessing program data at an address to be output to the second data terminal, the image input control circuit being connected to an output terminal of the video signal output unit 10 to output the video signal. Input the composite video signal output from the unit 10 to separate the vertical and horizontal sync signals and output the feed sync signals. And a synchronization signal processor 20 for counting vertical and horizontal synchronization signals to generate a clock and an address, and an output terminal of the image signal output unit 10 and an output terminal of the synchronization signal processor 20 to contact the image signal. An A / D converter 23 for converting a composite video signal output from the output unit 10 into digital image data by an output clock of the synchronization signal processing unit 20, and an image input control signal and an image processing signal. Is connected to a key input unit 30 generated by pressing a key, an address terminal and a data terminal are connected to a second address terminal and a second data terminal of the memory unit 60, and an output terminal of the key input unit 30 is provided. And a synchronous signal output terminal of the synchronous signal processing section 20, and controls image processing by controlling input / output signals in accordance with the output of the key input section 30, and simultaneously controls image processing. An image input control unit 40 for inputting a shielded synchronization signal output from the synchronization processing unit 20 by the input of a signal and outputting a digital image data selection signal, and an address output terminal of the synchronization signal processing unit 20; The synchronization signal processor 20 is connected to an output terminal of the A / D conversion unit 23, an address terminal of the image input control unit 40 and a data terminal, and is output by the digital image data selection signal output from the image input control unit 40. ) And a multiplexer 50 which selects an address outputted from the &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; Data input control circuit. The microcomputer according to claim 1, wherein an image input control unit (40) is connected to the key input unit (30) to control various system input / output signals by an image processing signal and an image input control signal output from the key input unit (30). And an A / D conversion request signal ADRQ, which is connected to the microcomputer 41 and outputted from the microcomputer 41, is inputted to the input terminal I1, buffered, and output to the output terminal O1. Control input signal

Is inputted to the input terminal I2, buffered and output to the microcomputer 41 through the output terminal O2, and one input terminal is connected to the output terminal O1 of the buffer 42, and the synchronous separation unit ( The other input terminal is connected to the output terminal F of the terminal 21, and holds the microcomputer 41 by performing a negative logic multiplication on the A / D conversion request signal ADRQ and the even-order shield signal of the synchronization separator 21.

A data input terminal D is connected to a NAND gate 43 for outputting a signal, an output terminal O1 of the buffer 42, and a clock terminal CK is connected to an output terminal F of the synchronous separator 21. And an inverted output terminal Q connected to the input terminal I2 of the buffer 42 to latch the A / D conversion request signal ADRQ into the even-numbered feed synchronization signal of the synchronization separating unit 21, thereby causing an address multiplexing. Branch control input signal for outputting image data of the lexer 51 and the data multiplexer 52 at the correct time

And a latch circuit (44) for outputting the signal to the microcomputer (41) through the buffer (42).

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