JPH044644A - Signal processor and its test method - Google Patents

Abstract

PURPOSE:To conduct the test to any tested object by a same method without application of delay adjustment of an operation stop release signal for each tested object by monitoring an input signal string, recognizing a specific code string inserted before a test data main text and discriminating the start point. CONSTITUTION:An inspection operator brings a voice processor 30 into the standby state and commands the test mode to an input signal string discrimination control section 32 of the voice processing unit 30 by, e.g. manual operation to start an input digital audio tape recorder 20. The input signal string discrimination control section 32 monitors the timing when a test data received by an input register 31 is switched from a specific code pattern SS1 instructing the start of the test data into a text data main text TES and when the section 32 detects the timing, the section 32 uses an operation control signal COM to control the signal processing section 33 into the execution state. Thus, the signal processing section 33 executes the processing to the test data main text TES.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing device using digital signal processing and a testing method thereof.

U Prior Art] When developing audio processing devices such as codecs (encoding/decoding devices) to support various audio communication systems, it is necessary to conduct tests at the analog signal level, which is the input signal of the actual device. , testing at the digital signal level is required to confirm whether the processing of each block inside the audio processing device is being executed accurately. This is because digital signal level tests have better reproducibility and are suitable for rigorous testing.Also, digital signals for input and output of each part created by computer simulation are used as test signals.
This is because it becomes possible to check the operation at a numerical level.

By the way, in recent years, the signal processing block at the center of audio processing devices has begun to perform complex processing using digital signal processing, and as a result, a large amount of input data is required to determine whether the operation is being performed correctly. Therefore, a test is required to compare the original output data corresponding to such a large amount of input data with the output data actually output from the audio processing device to be tested. Furthermore, in recent years, the sampling frequency of digital signals has become higher, and from this point of view as well, a large amount of test data is required.

FIG. 2 shows a conventional test configuration at the digital signal level using a large amount of test data. input register 1,
Switch circuits 5 and 6 are provided on the input and output sides of the audio processing device 4 to be tested, which includes the audio processing section 2 and the output register 3, respectively, and are switched depending on the normal use mode and the test mode. These switch circuits 5 and 6 are switched by manual operation, for example.

In the normal processing mode, the switch circuit 5 selects the audio data output from the audio signal generation source 7 and converted into a digital signal by the analog/digital conversion circuit 8 and supplies it to the audio processing device 4 . The output data obtained by processing such audio data by the audio processing device 4 is supplied to the digital/analog conversion circuit 9 by the switch circuit 6, and after being converted into an analog signal, it is sent to the audio recording device. and a terminal device 10 such as an audio output device.

Further, for testing the audio processing device 4, an input test data generation circuit 11 is provided, and in the test mode, this test data generation diagram i? The test data output from 4H1 is supplied to the audio processing device 4 via the switch circuit 5. Output data obtained by processing the test I data by the audio processing device 4 is provided to the output data storage circuit 12 via the switch circuit 6 and is stored therein. Based on this stored output data, the microprocessor (
CPtJ) determines whether the audio processing device 4 is operating properly.

By the way, as a fundamental feature of digital signal processing, past input signals are stored in the delay register of the internal digital filter, and the content of the input data immediately before the true test data affects the test results. give. Therefore, some of the test data may become invalid data, but to prevent such invalid data from occurring, it is necessary to input test data synchronously at a specific time, such as immediately after initial settings. Ta. That is, the switching of the switch circuits 5 and 6 described above was performed at such timing.

[Problem to be Solved by the Invention] However, even if test data is input immediately after such initial settings, it is necessary to match the start point of the test data with the operation start point of the audio processing device, and such control is not necessary. Requires configuration. In the conventional test configuration, as shown in FIG. 2, the test data generation circuit 11 controls the operation start point of the audio processing device 4. As a result, the test device consisting of the test data generation circuit 11, output data storage diagram i, etc. has become large and complicated.

As mentioned above, a large amount of test data is required for the test, and this also makes the test equipment large and complicated.

In addition, the starting point of the test data and the audio processing device 4 described above are also included.
Considering the timing alignment with the operation start point of the test data generation circuit 11, it is conceivable to use a RAM or ROM that can easily control the timing as the storage section for storing the test data of the test data generation circuit 11. Nowadays, the amount of test data is much larger than the capacity that can be stored in a ROM, and the number of test data becomes plural, and the readout control structure and the structure for converting the readout data into serial data become larger.

Therefore, it is conceivable to apply a digital audio tape recorder (DAT) that can sequentially output a large amount of test data in the form of serial data.
When DAT is used, it is not possible to appropriately control the start point of the test data and the operation start point of the audio processing device 4 to match.

In addition, as mentioned above, even if timing control is performed using ROM'l'RAM, the objects under test change one after another, and each object under test starts even if the same operation start control signal is given due to product variations, etc. The points are slightly different.

As a way to avoid such inconveniences, it is possible to deal with this by inserting invalid data at the beginning of the test data in an amount corresponding to the current target under test, or by changing the operation start control signal through a variable phase shifter, etc. Individual adjustments are currently being made depending on the test target. but,
Such adjustments require a large amount of work and do not allow rapid testing of a large number of test objects.

In addition, in order to match the start point of the test data and the start point of the operation of the audio processing device 4, a plurality of test data generation circuits with different time differences between the start point of the test data and the start point of the operation are prepared. A method has also been proposed in which the test data generation circuit is selected and tested according to the target under test (Japanese Patent Application Laid-Open No. 181228/1999). A method has been proposed that takes into account the differences between each type of control (Nikkei Electronics 1990.1.
8 (No. 490) Page 268).

However, in either method, the structure inevitably becomes large and complicated, and the control method becomes complicated.

The present invention has been made in consideration of the above points, and it is possible to test any target under test using the same method without adjusting the delay of the operation stop release signal for each target under test.
Moreover, it is an object of the present invention to provide a signal processing device and a testing method thereof that can be tested in a short time due to its small size and simple configuration.

[Means for Solving the Problems] In order to solve the above problems, the first invention (according to claim 1 or 2) provides an audio processing device using digital signal processing as follows. It was composed of each means.

That is, when setting the test mode, monitors the input signal string of the signal processing device, recognizes that there is a first specific code string inserted before the main body of test data that is valid as test input data, A test data body determination means that determines the starting point of the test data body, and based on the determination result, the operation of the signal processing section in the signal processing device.
An operation control means is provided which causes the operation to be stopped when the first specific code string is input and to execute when the test data body is input. In addition, until the test data body determination means determines the starting point of the test data body, the first signal that outputs the second specific code string as the output signal of the signal processing device is
and a second output means for outputting the processing result by the signal processing section after the test data body determining means determines the starting point of the test data body.

A second aspect of the present invention (according to claim 3) is to input a data string consisting of a first specific code string and a valid test data body following this into such a signal processing device, and The signal processing device is tested by collating and analyzing the processing result data corresponding to the test data body output from the signal processing device.

[Operation] Both the first and second inventions are made by taking into consideration the timing alignment between the operation start point in the signal processing section and the start point of valid data of the test data, and the first specific code It is assumed that you will input a data string consisting of a column followed by a valid test data body.

The test data body determination means monitors the input signal string of the signal processing device, recognizes that there is a first specific code string inserted before the test data body that is valid as test input data, Determine the starting point of the test data body. Based on this determination result, the operation control means stops the operation of the signal processing section in the signal processing device when the first specific code string is input, and causes it to execute when the test data body is input. The processing result data obtained by the signal processing section in this manner is outputted by the second output means.

In addition, in order to clarify the starting point of the processing result data, a first output means is provided, and the second specific code is output as the output signal of the signal processing device until the starting point of the test data main body is determined. I am trying to output columns.

The second aspect of the present invention provides an input data string in a predetermined format, and obtains test results of the signal processing device from processing result data corresponding to the input data string.

[Example] Hereinafter, an example in which the present invention is applied to a test of an audio processing device will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

A first digital audio interface circuit #1 is connected to the input terminal of the digital audio signal of the audio processing device 30.
21 is connected. Test data in the form of a serial signal output from a digital audio tape recorder (DA child) 20 serving as a test data generating device is converted into a parallel signal via this digital audio interface circuit 21 and is then given to the audio processing device 30. ing.

Here, the test data shown in FIG. 3(A) is recorded on the tape loaded in the digital audio tape recorder 20, and the digital audio tape recorder 20 records the test data stored in this way. Read and print. That is, after outputting a specific code pattern S81 instructing the start of test data, a predetermined test data body TES is output, and then invalid data NVI is output. The specific code pattern SS1 may be any continuous pattern of specific values, for example, in the case of 16 bits, the numerical value 5 is an appropriate mixture of logical "1" and "0".
555 (hexadecimal notation) can be used.

In the audio processing device 30, the input register 31 takes in the test data input in this way. The test data taken in by the input register 31 is given to the input signal string determination control section 32 and the signal processing section 33 at clock cycles.

An operation mode signal is given to the input signal string determination control section 32, and when this operation mode signal instructs the test mode, the input signal string determination control section 32 controls the signal processing section 33 and the selection mode described below. The operation of the circuit 34 is controlled by an operation control signal COM (Fig. 3(C)) and a selection signal 5EL (Fig. 3(C)).
(D)). For details on this control operation, see
It is shown in FIG. 4 and will be described later.

The signal processing section 33 is configured to stop and cancel its operation under the control of the operation control signal COM from the input signal sequence determination control section 32, and is configured to process input data (including test data).
Processing result data obtained by processing TESOUT (
3(B)) is applied to the selection circuit 34.

A predetermined fixed code pattern SS2 outputted by the fixed value generation section 35 is also provided to the selection port &@ 34, and the selection circuit 34 selects data from the signal processing section 32 or the fixed value generation section 35. It is applied to the output register 36. The data stored in the output register 36 is converted into a serial signal by the second digital audio interface circuit 22, and then given to the digital audio cheap recorder 23 for output and recorded on tape. The signals stored on the tape are then collated and analyzed.In the test mode, the selection circuit 34 selects the fixed code pattern SS2 from the fixed value generation section 35, and then selects the fixed code pattern SS2 from the signal processing section 33. Processing result data TE
SOUT is selected.

Next, centering on the processing flowchart shown in Figure 4,
The processing in test mode will be explained.

The inspection operator connects the input or output digital audio tape recorder 20 or 23 to the digital audio input terminal and digital audio output terminal of the audio processing device 30 to be tested via the digital audio interface circuit 21 or 22, respectively. Connecting. Thereafter, the inspection operator puts the audio processing device 30 in a standby state, instructs the input signal string determination control section 32 of the audio processing device 30 to enter the test mode, for example, by manual operation, and starts the input digital audio tape recorder 20. let

The input signal string determination control unit 32 has included the instructed operation mode, and determines whether or not the captured mode is a test mode (steps 100 and 101).

If the mode is DES 1~, the input signal string determination control section 32 controls the signal processing section 33 to stop operating using the operation control signal COM, and also controls the selection circuit 34 using the selection signal SE.
L is used to control the state in which the fixed code pattern SS2 from the fixed value generation section 35 is selected (step 102.
103). Thereafter, the input signal string determination control unit 32 monitors the timing at which the test data received by the input register 31 switches from the specific code pattern SS1 instructing the start of the test data to the test data main body TES (step 104).

When a mode other than the test mode, such as the normal operation mode, is instructed (step 1), the input signal string determination control unit 32
01) or a transition from a specific code pattern SSI to the test data body TES, the signal processing section 33 is controlled to an execution state using the operation control signal COM (step 105). In the case of the test mode, the signal processing unit 33 executes processing on the test data body TES.

After causing the signal processing section 33 to start processing, the input signal string determination control section 32 switches the selection state of the selection circuit 34 with a delay of a processing delay time T (see FIG. 3) in the signal processing section 33, and The output operation by the output register 36 is activated (step 106).

In the case of test mode, the third
The output data shown in FIG. 2B is output from the second digital audio interface circuit 22 and stored on the tape loaded in the output digital audio tape recorder 23. That is, after the fixed code pattern SS2 outputted by the fixed value generation unit 35 continues for a predetermined period, the processing result data TESOUT corresponding to the test data body TES is
is followed by invalid data INV2. Processing result data TESOUT corresponding to the main body of test data stored on this tape is collated and analyzed, and is used to determine the quality of the subject to be tested.

According to this first embodiment, by simply preparing a data synchronization circuit (hardware configuration) for testing in the audio processing device 30, it is possible to check the functionality of a digital signal algorithm with a fast sampling frequency of, for example, 32 kHz to 48 kHz. Since it is possible to perform numerical checks, it is expected that the test time for audio processing devices using digital signal processing can be shortened. Furthermore, there is an advantage that hardware and software changes associated with changes/modifications to the processing algorithm can be confirmed at an early stage.

Further, in this way, unlike the conventional method, timing control between the test data itself and the time point at which the operation of the signal processing section starts can be appropriately performed.

Furthermore, digital audio tape recorder 20.23
Because it uses , it is possible to properly input and output large amounts of test data.

FIG. 5 shows a second embodiment of the present invention, and shows a first embodiment.
Corresponding parts to those in the embodiment are shown with the same reference numerals. In the first embodiment, the fixed value generation unit 35 was used, and the fixed code pattern SSI for input and the fixed code pattern SS2 for output were different, but in this second embodiment, these two The pattern is the same. That is, the test data received by the input register 31 is directly input to the selection circuit 34, and the fixed pattern psi (SS2>) is selected as output data during the fixed code pattern period.

In this second embodiment as well, the simple configuration allows the start point of the test data to be aligned with the start point of the signal processing unit's operation without any adjustment work, and it is possible to perform an appropriate test. It should be noted that, unlike the first embodiment, the fixed value generating section 35 is not provided, which simplifies the point configuration, which is an advantage, but the process corresponding to the fixed code pattern SS2 of the output data and the test data body is This has the disadvantage that invalid data is inserted between the result data TESOUT and the result data TESOUT for a predetermined period of time.

The present invention can be applied not only to testing of audio processing devices, but also to signal processing devices that employ various types of digital processing.

Moreover, although the above description has been made of the case where the audio processing device to be tested has one signal processing section, the present invention can also be applied to a case where it has a plurality of signal processing sections. That is, the signal processing section unrelated to the test may be put into a through mode in which the signal passes through as is, and the test data may be applied to the signal processing section to be tested. In this case as well, the input signal string determination control section needs to control the start of operation of the signal processing section.

[Effects of the Invention] As described above, according to the present invention, it is possible to test any target under test using the same method without adjusting the delay of the operation stop release signal for each target under test. The simple configuration allows testing to be carried out in a short time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram according to the first embodiment of the present invention, Fig. 2 is a block diagram showing a conventional test method, Fig. 3 is an explanatory diagram showing various signals of the first embodiment, and Fig. 4 is a block diagram showing the conventional test method. FIG. 5 is a block diagram of a second embodiment of the present invention. 20.23...Digital audio tape recorder,
21.22...Digital audio interface circuit, 30...Audio processing device, 32...Input signal string determination control unit, 33...Signal processing unit (test target), 34
. . . selection circuit, 35 . . . fixed value generation section. 1. Display of the case 1990 Patent Application No. 105410 2. Name of the invention Signal processing device and its testing method 3. Person making the amendment Relationship to the case Patent applicant address (105) 1-chome Toranomon, Minato-ku, Tokyo 7-12 Name (029) Oki Electric Industry Co., Ltd. Representative Nobumitsu Kosugi 4 Address of agent (〒108) 4-10-3 Shibaura, Minato-ku, Tokyo Reception □゛・ 6 Contents of amendment (1) Details "Figure 3 (A) J" in page 12, line 16 of the book.
3(a)". (2) 1. “Fig. 3 (C)” in lines 17 to 18 of page 13 of the specification is corrected to “Fig. 3 (C).” (3) Change “Figure 3 (D)” on page 13, line 18 of the specification to “
3(d)". (4) "Figure 3 (B)" on page 14, line 5 of the specification and page 17, line 6 shall be corrected to "Figure 3 (b)."that's all

Claims (3)

[Claims] (1) In a signal processing device using digital signal processing, when setting the test mode, the input signal string of the signal processing device is monitored, and the first a test data body determining means that recognizes the existence of a specific code string and determines the starting point of the test data body; An operation control means that stops when a specific code string is input and executes when the test data body is input; and an output signal of the signal processing device until the test data body determination means determines the starting point of the test data body. a first output means for outputting a second specific code string, and a second output means for outputting a processing result by the signal processing unit after the test data body determination means determines the starting point of the test data body. A signal processing device characterized by being provided with an output means. (2) The signal processing device according to claim 1, wherein the first output means outputs the first specific code string as it is as the second specific code string. (3) A data string consisting of the first specific code string and the valid test data body that follows it is defined in claim 1 or 2.
A method for testing a signal processing device in which the signal processing device is tested by collating and analyzing processing result data input to the signal processing device described in section 1 and outputted from the signal processing device, which corresponds to the main body of test data. .