JPS58207169A - Input interface circuit of image pickup information - Google Patents

Abstract

PURPOSE:To ensure the input of the image pickup information to a processor by means of a device of a simple constitution and without using a large-capacity memory, by extracting a picture element with each horizontal scan and feeding it to the processor. CONSTITUTION:The image pickup signal given from an ITV1 is applied to a monitor device 4 as well as to a sample holding circuit 6 via an amplifier 5. A signal generator 7 consisting of a counter 71 and a comparator 72 countsclocks CK and delivers the sampling signal to the circuit 6 based on the sampling position information given from a processor 2 and at the sampling position on a horizontal scanning line that is designated with each horizontal scanning period. The sampling output given from the circuit 6 is fed to the processor 2 in the next horizontal scanning period together with the horizontal scanning number via an A/D converter 10 and a buffer 11. The sampling position information which is given to the generator 7 from the processor 2 every time a vertical scan is over is varied to feed successively the whole image pickup information to the processor 2.

Description

[Detailed Description of the Invention] [Technical Development of the Invention] The present invention provides a method for inputting imaged information captured by an imaging device such as an industrial television (ITV) camera into an information processing device comprising a microprocessor or the like. The present invention relates to an imaging information input interface circuit.

[Technical background of the invention]

Conventionally, for example, when inputting imaging information obtained by an ITV camera to an information processing device, the travel speed of the ITv camera is generally high; Since the speed is slow, I
It is not possible to directly input the imaging information of a TV camera into one information processing device.Therefore, in the past, a balance between the ITV camera and the information processing device is set in accordance with the information speed between the two. Either a memory is provided and the imaging information is input via this buffer memory, or the imaging information for one screen is input via a so-called frame memory that can store one screen of imaging information. There is.

[Problems with background technology]

For this reason, these conventional interface circuits must use ultra-high-speed sample and hold, ultra-high-speed A/D conversion elements, and large-capacity, high-speed memory, making them expensive.

[Purpose of the invention]

Is this corpse the imaging information obtained by the imaging device? It is an object of the present invention to provide an imaging information input interface circuit that can input information to an information processing device without using an ultra-high-speed confectionery or a large-capacity memory, thereby reducing the cost.

[Summary of the invention]

In order to achieve all of the above objectives, Misashi Akira adds the pixel price to be input in the scanning line for each scan that requires input using the mysterious information processing system, and according to this specification. A sampling signal is emitted at a timing corresponding to the pixel-equipped board to sample and hold the pixel information at the positions of both systems, and this held pixel information is digitized and stored in a buffer memory, from which the next input should be made. The digitized pixel information is read out and input to the information processing device during the horizontal scanning period.

That is, the present invention specifies and extracts one pixel for each horizontal scanning period, and inputs this to the information processing device via a buffer during the next horizontal scanning period.

[Embodiments of the invention]

FIG. 1 is a professional configuration diagram of an interface circuit in one embodiment of the present invention, and J is an industrial television screen (ITV).
) camera, central processing unit (CPU) of the information processing device
) are shown respectively.

This interface F-S circuit has a synchronization circuit 3 belonging to the ITv camera 1, and uses the vertical synchronization signal VD and horizontal synchronization signal HD generated from this synchronization circuit 3 to synchronize the ITV camera JK imaging circuit 1. ]. and,
The imaging signal gvB outputted from the ITV camera 1 is displayed on the monitor device 4 and is led to a sample hold (SH) circuit 6117 via the buffer amplifier 5. This sample and hold circuit 6 samples and holds the image pickup signal VS from the buffer amplifier 5 when the sampling signal SHS is generated from the signal generation circuit 7, and maintains this hold until the horizontal synchronization signal HD 25 arrives. . Here, the signal generation circuit 7 includes a counter 7 that counts clock pulses CK generated from the synchronization circuit 3 and outputs information for changing the pixel position in the horizontal scanning direction, and information output from the counter 71. It is composed of a comparator 72 which generates a sampling signal SH8'i when compared with the sampling position information output from the fccPU2, and a flip circuit 8 and a flip 70.
The input period of CPU 2 set in knob 9 (seconds is t
This is for supplying sampling position information to the comparator 72 by opening the dart for one field scanning period of the TV camera l. CS is the operation start signal of CPU 2, C
FS indicates a dart control signal output from the flip-flop 9.

Further, this interface circuit converts the pixel signals of the image pickup signal vS sampled and held in the sample and hold circuit 6 into analog and digital (A/D) signals within the hold period.
D) The signal is converted into an 8-bit digital signal by the i-converter 10 and stored in the pack 711. Then, the horizontal synchronizing signal I (D) is applied to the interrupt input terminal of the CPU 2 through the entire dart circuit 12, and the CPU 2 is inputted to read out the digitized pixel information CDS from the buffer 711 and sent to the CPU 2. Note that the counter shown at 13 in the figure counts the horizontal synchronizing signal HD to obtain the position information in the vertical scanning direction of the image pickup signal VS, that is, the number information of the horizontal scanning line, and uses this information as described above. This is input to the CPU 2 as position information in the & plane scanning direction of the digitized image information CDS.

Because of these two configurations, when the synchronization circuit 3 is fully operated and the CPU 2 generates the operation 1 start signal C8 in synchronization with it, the ITV camera 1 starts the first imaging scan, and each horizontal scan takes 3 ETHs. .

For example, as shown in FIG. 2, an imaging signal VS is obtained every time THI tTHm t... On the other hand, simultaneously with this imaging scan, the ratio unit 72 of the signal generation circuit 7 generates information (counter 71
(output) and sampling position information specified by the CPU 2, and when the information indicating the pixel position becomes larger, a sampling signal SH8 is generated. For example, C.P.
The sampling position information specified by U2 is shown in Figure 2 1X-
If it corresponds to the position shown in , the sampling signal SH8 is generated when the set value of the counter 71 reaches the value corresponding to the second section TX. As a result, in the sample hold circuit 6, the sampling signal SH
8, the pixel signal at the time tX of occurrence is sampled and held until the horizontal synchronizing signal HD of the next horizontal scanning period arrives. Then, the sampled pixel signal is
It is digitized by the A/D converter 10 within the above-mentioned hold period, and then at the trailing edge of the horizontal synchronizing signal HD, the buffer I
J Ic memorized.

Then, the stored digitized image purple @ number is stored in the next horizontal scanning period, for example, if it is a signal sampled in the period THI, it will be in the period TH2, and again in the period TH! If the signal is sampled in the period T Hm, for example, CDS in Figure 2
The data are read out and input to the CPU 2 as shown in FIG. Therefore, the sampled pixel signal information can be input to the CPU 2 at low speed using the entire horizontal scanning period (for example, 63.5 μs).

In this way, if pixel information at an arbitrary pixel position is sampled for each horizontal scanning hill and inputted to the CPU 2 via the buffer 11, and this input operation is performed up to the last horizontal scanning line in the vertical scanning direction Y, for example, All images at positions indicated by ω etc. on the diagonal in Figure 3, for example, are input to the 512th purple pixel PU. Then, if the above input operation is performed by controlling the sampling position external signal specified by the CPU 2 pixel by pixel; The input is a photon.

In this way, if the interface circuit of this embodiment is
Only the pixel reliability at an arbitrary pixel position of each horizontal scanning line is sampled and held, and this is transferred to the CP within the next horizontal scanning period.
Since input is made to U2, pixel information can be input at a correspondingly low input speed even when a CPU 'i with a slow input speed, such as a microprocessor, is used. Furthermore, in this case, since the amount of information handled in one input operation is one pixel, the capacity of the buffer 11 is reduced by storing this one pixel's worth of information (for example, 8 bits). It is possible to reduce the capacity of the buffer, and as a result, it is possible to provide a significantly inexpensive circuit.

Note that the present invention is not limited to the above embodiments.

For example, in the above embodiment, a case was described in which the exercise information for the entire screen is input, but it is necessary to specify the legal area to be input and to write a horizontal line and its running in the i-direction X for this area only. You may also specify the can axis input. 1. Specify the horizontal scanning line that should be input every other line or every multiple lines, and specify the pixel position that should be input every other pixel or every multiple pixels, and input some rough information. Good too. In short, since the present invention inputs information Fi pixel by pixel, there is an advantage that the shape, size, density, etc. of the information to be input can be freely set. Further, in the embodiment described above, the hold period of pixel information is set from sampling to the arrival of the next horizontal synchronizing signal HD, but it may be set from sampling to the sampling point in the next horizontal scan. In this way, even if the sampling position is arbitrary, the hold period can be guaranteed for one horizontal scanning period, so it is only necessary to perform A/D conversion within this period, and as a result, Since it becomes possible to use an A/D converter with a low conversion speed, it is possible to further reduce the cost. Further, in this case, the input period of the digitized pixel report to the CPU 2 may be set from the end point of holding the pixel information to the next hold period. In addition to the above, the structure of the signal generating circuit, the control procedure in the CPU, the construction and configuration of the imaging device, etc. can be modified in various ways without departing from the spirit of the present invention.

〔Effect of the invention〕

As described in detail above, the present invention specifies the pixel position to be input in each horizontal scanning line to be input by the information processing device, and performs sampling at the timing corresponding to the pixel position according to this designation. A signal is emitted to sample and hold the image information at the above pixel position, this held image information is digitized and stored in a buffer memory, and from this buffer memory the above information is sampled during one period of the next horizontal staff line to be input. A device that reads digitized pixel information and inputs it to the information processing device.◎ It can input the 4% information to the information processing device without using the transformer or the memory of the photographic cover, which reduces the price. A measurable imaging information interface circuit can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an interface circuit in one embodiment of the invention, Figs. 2 and 3 are used to explain the operation of the circuit, Fig. 2 is a timing diagram thereof, and Fig. The figure is a schematic diagram showing the traveling state. J-ITV power,)'U, 2 ・CPU, 3-・
・Synchronous circuit, 4--Monitor device, 5--k amplifier, 6... Sampling hold circuit, 7... Signal generation circuit, 8.12... Dart circuit, 9... Free lag flop , lθ...A/D converter, JJ...buffer.・、、′：

Claims (1)

[Claims] In an imaging information input interface circuit that inputs imaging information obtained by an imaging device to an information processing device, a horizontal line to be input specified by the information processing device for each horizontal scanning line that requires input among the imaging information is provided. Pixel position in scanning direction +
A signal generation circuit that introduces a pI strain and generates a sampling signal at a timing corresponding to the pixel position according to the pixel position information, and a signal generation circuit that samples and holds the imaging information from the imaging device at the time when the sampling signal is generated, and generates the information. One sample/hold station that obtains bidirectional information on the pixel position specified by the processing device, and the pixel information held by this sample and hold circuit. We commemorate the analog-to-digital conversion circuit to be digitized and the digitized dual-system information obtained by this analog-to-digital conversion circuit, and we also use this memorized dual-system information to calculate the foot of the horizontal line that should be input next. 1. An imaging information input interface circuit comprising: 11 buffers for escaping and supplying the data to the information processing apparatus during the process;