CN116996637A - 8K video shooting and recording system and 8K video shooting and recording all-in-one machine - Google Patents
8K video shooting and recording system and 8K video shooting and recording all-in-one machine Download PDFInfo
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- CN116996637A CN116996637A CN202310828423.1A CN202310828423A CN116996637A CN 116996637 A CN116996637 A CN 116996637A CN 202310828423 A CN202310828423 A CN 202310828423A CN 116996637 A CN116996637 A CN 116996637A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/78—Television signal recording using magnetic recording
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/20—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding
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Abstract
The invention discloses an 8K video shooting and recording system and an 8K video shooting and recording integrated machine, comprising: FPGA and CMOS image sensor for 8K recording; the CMOS image sensor is used for: collecting a first 8K video signal, performing photoelectric conversion on the first 8K video signal to obtain a second 8K video signal, and sending the second 8K video signal to an FPGA; the FPGA is used for: and performing signal processing on the second 8K video signal to obtain a target 8K video signal and outputting the target 8K video signal. The invention can realize the shooting of the ultra-high definition video with 8K resolution, thereby bringing higher quality video shooting experience for users.
Description
Technical Field
The invention relates to the technical field of video shooting and recording, in particular to an 8K video shooting and recording system and an 8K video shooting and recording integrated machine.
Background
With the continuous development of high and new technologies, the current 4K video-recording all-in-one machine cannot show finer and clearer picture effects, cannot show more real, natural and vivid picture effects, and cannot realize the reduction of occupation of storage space while guaranteeing high image quality in the aspect of video compression.
Accordingly, there is a need to provide a solution to the above-mentioned problems.
Disclosure of Invention
In order to solve the technical problems, the invention provides an 8K video shooting and recording system and an 8K video shooting and recording integrated machine.
The technical scheme of the 8K video shooting and recording system is as follows:
comprising the following steps: FPGA and CMOS image sensor for 8K recording;
the CMOS image sensor is used for: collecting a first 8K video signal, performing photoelectric conversion on the first 8K video signal to obtain a second 8K video signal, and sending the second 8K video signal to an FPGA;
the FPGA is used for: and performing signal processing on the second 8K video signal to obtain a target 8K video signal and outputting the target 8K video signal.
The 8K video shooting and recording system has the following beneficial effects:
the invention can realize the shooting of the ultra-high definition video with 8K resolution, thereby bringing higher quality video shooting experience for users.
Based on the scheme, the 8K video shooting and recording system can be improved as follows.
Further, the method further comprises the following steps: a coding chip and a memory; the coding chip is used for:
HEVC coding is carried out on the target 8K video signal, an 8K video coding file is obtained and sent to the memory for storage.
The beneficial effects of adopting the further technical scheme are as follows: HEVC encoding is carried out on the 8K video signal, so that the occupation of storage space is reduced while high image quality is ensured.
Further, the method further comprises the following steps: PCI-E channel; the coding chip is specifically used for: and sending the 8K video coding file to the memory for storage through the PCI-E channel.
The beneficial effects of adopting the further technical scheme are as follows: the method can realize higher data writing speed and meet the recording requirement of 8K video.
Further, the method further comprises the following steps: a decoding chip; the decoding chip is used for:
when a video playing instruction sent by the FPGA is received, the 8K video coding file is obtained from the memory and decoded, and a decoded target 8K video signal is sent to the FPGA so as to be output through the FPGA.
Further, the method further comprises the following steps: a target SDI interface;
the FPGA is specifically used for: and outputting the target 8K video signal to an external 8K screen for playing through the target SDI interface.
Further, the method further comprises the following steps: an HDMI interface and a display screen;
the FPGA is specifically further configured to: and outputting the target 8K video signal to the display screen for playing through the HDMI interface.
Further, the target SDI interface is an SDI interface of 4×12g.
Further, the FPGA is specifically configured to:
processing the second 8K video signal by adopting a plurality of picture processing modes to obtain the target 8K video signal; the multiple picture processing modes comprise: image brightness processing, image color processing, and image white balance processing.
Further, the CMOS image sensor is a CMOS image sensor of GCINE 4349.
The technical scheme of the 8K video shooting and recording all-in-one machine is as follows:
the 8K video shooting and recording all-in-one machine adopts the 8K video shooting and recording system to carry out 8K video shooting and recording.
Drawings
Fig. 1 is a schematic diagram of a first structure of an embodiment of an 8K video recording system according to the present invention;
FIG. 2 is a schematic diagram showing the structure of an encoding process in an embodiment of an 8K video recording system according to the present invention;
fig. 3 is a schematic diagram showing a decoding process in an embodiment of an 8K video recording system according to the present invention;
fig. 4 is a schematic diagram of a second structure of an embodiment of an 8K video recording system according to the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a first structure of an embodiment of an 8K video recording system according to the present invention. As shown in fig. 1, includes: an FPGA110 and a CMOS image sensor 120 for 8K recording.
The CMOS image sensor 120 is configured to: and acquiring a first 8K video signal, performing photoelectric conversion on the first 8K video signal, obtaining a second 8K video signal, and sending the second 8K video signal to the FPGA 110.
The CMOS image sensor 120 (1) is a CMOS image sensor of GCINE 4349. (2) The first 8K video signal is: an 8K video light signal of the acquired target scene (region). (3) The second 8K video signal is: an electric signal (digital signal) of the 8K video obtained by converting the optical signal. (4) The CMOS image sensor 120 is connected with the FPGA110 through an SDI-12Gx4 interface.
Specifically, when the FPGA110 receives an instruction of recording an 8K video signal sent by a user, the FPGA110 sends an acquisition instruction to the CMOS image sensor 120. When the CMOS image sensor 120 receives the acquisition command, the CMOS image sensor 120 acquires a first 8K video signal, performs photoelectric conversion on the first 8K video signal, and obtains a second 8K video signal and sends the second 8K video signal to the FPGA 110.
It should be noted that, a lens is disposed at the front end of the CMOS image sensor 120, and the lens is used for converging the light of the target scene (area), so that the CMOS image sensor 120 collects the corresponding light signal (the first 8K video signal).
The FPGA110 is configured to: and performing signal processing on the second 8K video signal to obtain a target 8K video signal and outputting the target 8K video signal.
Wherein (1) the manner of signal processing the second 8K video signal includes: image brightness processing, image color processing, and image white balance processing. (2) The target 8K video signal is: video signals (electric signals) after signal processing. (3) The mode of outputting the target 8K video signal includes: and directly outputting the target 8K video signal after signal processing, and outputting the target 8K video signal obtained after encoding and decoding.
Specifically, the FPGA110 performs image brightness processing, image color processing, and image white balance processing on the second 8K video signal, obtains a target 8K video signal, and outputs the target 8K video signal.
Preferably, the method further comprises: a coding chip 130 and a memory 140.
The encoding chip 130 is configured to:
and receiving the target 8K video signal sent by the FPGA110, performing HEVC coding on the target 8K video signal, obtaining an 8K video coding file, and sending the 8K video coding file to the memory 140 for storage.
Wherein (1) the encoding chip 130 adopts the model number: a coding chip of Haishi Hi 3559A+ or a chip of Soxhlet MB86M30x 4. (2) The memory 140 is: CFexpress memory card.
Specifically, as shown in fig. 2, the encoding chip 130 receives the target 8K video signal sent by the FPGA110, performs HEVC encoding on the target 8K video signal, obtains an 8K video encoding file, and sends the 8K video encoding file to the memory 140 for storage.
The FPGA110 and the encoding chip 130 are connected by an SDI-12Gx4 interface.
Preferably, the method further comprises: PCI-E channel 150.
The encoding chip 130 is specifically configured to: and sending the 8K video coding file to the memory 140 for storage through the PCI-E channel 150.
The 8K video coding file is as follows: the file obtained after encoding the target 8K video signal has the format of MP4, AVI or other formats supporting HEVC encoding.
Preferably, the method further comprises: and a decoding chip 160.
The decoding chip 160 is configured to:
when receiving the video playing instruction sent by the FPGA110, the 8K video encoding file is obtained from the memory 140 and decoded, and the decoded target 8K video signal is sent to the FPGA110 to be output through the FPGA 110.
Wherein (1) the decoding chip 160 is of the type: a coding chip of Haishi Hi 3559A+ or a chip of Soxhlet MB86M30x 4. (2) The video playing instruction is an instruction sent by the FPGA 110.
Specifically, as shown in fig. 3, when the decoding chip 160 receives a video playing instruction sent by the FPGA110, an 8K video encoding file is obtained from the memory 140 through the PCI-E channel 150, and the 8K video encoding file is decoded, so that a decoded target 8K video signal is obtained and sent to the FPGA110 for output through the FPGA 110.
Preferably, the method further comprises: the target SDI interface 170.
The FPGA110 is specifically configured to: the target 8K video signal is output to an external 8K screen for playing through the target SDI interface 170.
Wherein (1) the target SDI interface 170 is a 4×12G SDI interface. (2) The external 8K screen is: an 8K screen (8K display screen) connected by an SDI interface of 4×12G.
Preferably, the method further comprises: an HDMI interface 180 and a display screen 190.
The FPGA110 is specifically further configured to: and outputting the target 8K video signal to the display screen 190 for playing through the HDMI interface 180.
The display screen 190 is an LCD screen (4K screen) of the main body.
Preferably, the FPGA110 is specifically configured to:
and processing the second 8K video signal by adopting a plurality of picture processing modes to obtain the target 8K video signal.
Wherein, the multiple picture processing modes include but are not limited to: image brightness processing, image color processing, and image white balance processing.
In addition, as shown in fig. 4, the PCI-E Gen3 Switch is the PCI-E channel 150 in the present embodiment, and is capable of writing the encoded 8K video encoding file into the CFexpress memory card through the high-speed bus. The ARM SOC is the decoding chip 160 in the embodiment, which can decode the 8K video coding file in the CFexpress memory card, and then the FPGA110 transmits the decoded video to the 4K screen on the machine body through the HDMI2.0 or outputs the video to the external 8K screen through the 4x12G-SDI cable. Meanwhile, the management of on-machine control, a touch screen, an external interface and other devices is also responsible for ARM SOC. Alternatively, JPEG-XS encoding/decoding) enables the 8K video camera system of the present embodiment to support encoding and decoding of JPEG-XS (a high quality shallow compression algorithm) signals.
According to the technical scheme, the ultra-high definition video with 8K resolution can be shot, so that higher-quality video shooting experience is brought to a user.
The embodiment provides an 8K video shooting and recording all-in-one machine, which adopts the 8K video shooting and recording system of the embodiment. For specific reference, the modules and parameters in the embodiment of an 8K video recording system are not described herein.
In the description provided herein, numerous specific details are set forth. It will be appreciated, however, that embodiments of the invention may be practiced without such specific details. Similarly, in the above description of exemplary embodiments of the invention, various features of embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. Wherein the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specifically stated.
Claims (10)
1. An 8K video recording system, comprising: FPGA and CMOS image sensor for 8K recording;
the CMOS image sensor is used for: collecting a first 8K video signal, performing photoelectric conversion on the first 8K video signal to obtain a second 8K video signal, and sending the second 8K video signal to an FPGA;
the FPGA is used for: and performing signal processing on the second 8K video signal to obtain a target 8K video signal and outputting the target 8K video signal.
2. The 8K video recording system of claim 1, further comprising: a coding chip and a memory; the coding chip is used for:
HEVC coding is carried out on the target 8K video signal, an 8K video coding file is obtained and sent to the memory for storage.
3. The 8K video recording system of claim 2, further comprising: PCI-E channel; the coding chip is specifically used for: and sending the 8K video coding file to the memory for storage through the PCI-E channel.
4. The 8K video recording system of claim 3 further comprising: a decoding chip; the decoding chip is used for:
when a video playing instruction sent by the FPGA is received, the 8K video coding file is obtained from the memory and decoded, and a decoded target 8K video signal is sent to the FPGA so as to be output through the FPGA.
5. The 8K video recording system of any one of claims 1-4, further comprising: a target SDI interface;
the FPGA is specifically used for: and outputting the target 8K video signal to an external 8K screen for playing through the target SDI interface.
6. The 8K video recording system of any one of claims 1-4, further comprising: an HDMI interface and a display screen;
the FPGA is specifically further configured to: and outputting the target 8K video signal to the display screen for playing through the HDMI interface.
7. The 8K video recording system of claim 5 wherein the target SDI interface is a 4x12G SDI interface.
8. The 8K video recording system of claim 1, wherein the FPGA is specifically configured to:
processing the second 8K video signal by adopting a plurality of picture processing modes to obtain the target 8K video signal; the multiple picture processing modes comprise: image brightness processing, image color processing, and image white balance processing.
9. The 8K video recording system of claim 1 wherein the CMOS image sensor is a CMOS image sensor model GCINE 4349.
10. An 8K video camcorder, wherein the 8K video camcorder system according to any one of claims 1-9 is employed.
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| CN202310828423.1A CN116996637A (en) | 2023-07-06 | 2023-07-06 | 8K video shooting and recording system and 8K video shooting and recording all-in-one machine |
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| CN202310828423.1A CN116996637A (en) | 2023-07-06 | 2023-07-06 | 8K video shooting and recording system and 8K video shooting and recording all-in-one machine |
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