KR890007579A - 2D image contour correction circuit - Google Patents

2D image contour correction circuit Download PDF

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Publication number
KR890007579A
KR890007579A KR870011803A KR870011803A KR890007579A KR 890007579 A KR890007579 A KR 890007579A KR 870011803 A KR870011803 A KR 870011803A KR 870011803 A KR870011803 A KR 870011803A KR 890007579 A KR890007579 A KR 890007579A
Authority
KR
South Korea
Prior art keywords
adder
output signal
delay circuit
output
signal
Prior art date
Application number
KR870011803A
Other languages
Korean (ko)
Other versions
KR900003775B1 (en
Inventor
박영준
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR1019870011803A priority Critical patent/KR900003775B1/en
Publication of KR890007579A publication Critical patent/KR890007579A/en
Application granted granted Critical
Publication of KR900003775B1 publication Critical patent/KR900003775B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness
    • G06T5/73—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/142—Edging; Contouring

Abstract

내용 없음No content

Description

2차원 화상 윤곽 보정회로2D image contour correction circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도는 본 발명의 블럭도.2 is a block diagram of the present invention.

제 3 도는 본 발명 회로도.3 is a circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1-4 : 증폭기 5-8 : 가산기1-4: Amplifier 5-8: Adder

9 : 감산기 10 : 저역통과필터9: subtractor 10: low pass filter

11, 12 : 지연회로11, 12: delay circuit

Claims (1)

휘도신호를 조절함으로서 화상의 윤곽을 보정하는 텔레비젼 영상신호처리계의 윤곽 보정회로에 있어서, 입력영상신호를 1수평주기 지연하는 지연회로(11)와,지연회로(11)의 입출력신호를 가산하는 가산기(5)와, 가산기(5)의 출력신호를 1수평주기 지연하는 지연회로(12)와, 지연회로의 입출력신호를 가산하는 가산기(6)와지연회로(11)와 가산기(6)을 출력신호를 가산하는 가산기(7)와 가산기(7)의 출력단에 구성된 저역통과필터(10)와, 지연회로(11)의 출력신호로부터 저역통과필터(l0)의 출력신호를 감산하는 감산기(9)와, 지연회로(11)의 출력신호와 감산기(9)의 출력신호를 가산하여 출력하는 가산기(8)와, 상기한 가산기(5,6,7)의 출력단에 각각 구성된 신호감쇄용 증폭기(1,2,3)와, 상기한 감산기(9)의 출력단에 구성된 증폭율 조정용 증폭기(4)를 포함하여 이루어지는 것을 특징으로 하는 2차원 화상 윤곽 보정회로.A contour correction circuit of a television video signal processing system that corrects the outline of an image by adjusting a luminance signal, comprising: a delay circuit 11 for delaying an input video signal by one horizontal period and an input / output signal of the delay circuit 11; An adder 5, a delay circuit 12 for delaying the output signal of the adder 5 by one horizontal period, an adder 6 for adding an input / output signal of the delay circuit, a delay circuit 11, and an adder 6; An adder 7 for adding an output signal, a low pass filter 10 configured at the output of the adder 7, and a subtractor 9 for subtracting the output signal of the low pass filter 110 from the output signal of the delay circuit 11; ), An adder 8 for adding and outputting the output signal of the delay circuit 11 and the output signal of the subtractor 9, and a signal attenuation amplifier configured at the output terminals of the adders 5, 6, and 7, respectively. 1,2,3), and an amplifier 4 for amplification factor adjustment configured at the output end of the subtractor 9. 2D image contour correction circuit, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870011803A 1987-10-23 1987-10-23 Video contour compensating circuit KR900003775B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870011803A KR900003775B1 (en) 1987-10-23 1987-10-23 Video contour compensating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870011803A KR900003775B1 (en) 1987-10-23 1987-10-23 Video contour compensating circuit

Publications (2)

Publication Number Publication Date
KR890007579A true KR890007579A (en) 1989-06-20
KR900003775B1 KR900003775B1 (en) 1990-05-31

Family

ID=19265409

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870011803A KR900003775B1 (en) 1987-10-23 1987-10-23 Video contour compensating circuit

Country Status (1)

Country Link
KR (1) KR900003775B1 (en)

Also Published As

Publication number Publication date
KR900003775B1 (en) 1990-05-31

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