KR890006041A - Tone decoder - Google Patents

Tone decoder Download PDF

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Publication number
KR890006041A
KR890006041A KR870010709A KR870010709A KR890006041A KR 890006041 A KR890006041 A KR 890006041A KR 870010709 A KR870010709 A KR 870010709A KR 870010709 A KR870010709 A KR 870010709A KR 890006041 A KR890006041 A KR 890006041A
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South Korea
Prior art keywords
frequency
decoder
unit
output
cadence
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KR870010709A
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Korean (ko)
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KR900004468B1 (en
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류광희
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강진구
삼성반도체통신 주식회사
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Priority to KR1019870010709A priority Critical patent/KR900004468B1/en
Publication of KR890006041A publication Critical patent/KR890006041A/en
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Publication of KR900004468B1 publication Critical patent/KR900004468B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Executing Machine-Instructions (AREA)
  • Telephonic Communication Services (AREA)
  • Telephone Function (AREA)

Abstract

내용 없음No content

Description

톤 디코더Tone decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 톤 디코더의 블록도.1 is a block diagram of a tone decoder of the present invention.

제2도는 제1도의 실시예를 도시한 상세회로도.2 is a detailed circuit diagram showing the embodiment of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100 : 카덴스 디코더부(Cadence Decoder)100: cadence decoder (Cadence Decoder)

200 : 주파수 디코더부(Frequency Decoder)200: frequency decoder unit (Frequency Decoder)

300 : 주파수 조합부300: frequency combination unit

400 : 데이타 인지부 500 : 출력버퍼부400: data recognition unit 500: output buffer unit

Claims (4)

교환기기 또는 단말기기꼭 톤 디코더에 있어서, 입력된 소정톤의 단속비를 검출하여 그 단속비에 대응하는 카덴스 데이타를 출력하는 카덴스 디코더부(100)와, 소정의 단일주파수 또는 복합주파수로된 상기 톤의 주파수를 검출하여 그에 대응하는 하나 또는 다수의 주파수 인식신호를 출력하는 주파수 디코뎌부(200)와, 소정의 주파수 조합상태로 기설정된 논리상태에 따라서 상기 주파수 인식신호의 출력에 대응하는 주파수 데이타를 출력하는 주파수 조합부(300)와, 소정 제어신호의 인가상태에 따라 상기 주파수 데이타 및 카덴스 데이타를 출력하는 출력버퍼부(500)와, 상기 카덴스 디코더부(100) 또는 주파수 디코더부(200)의 톤인식상태에 대웅하여 데이타 인지신호를 출력하는 데이타인지부(400)를 구비하여, 상기 카덴스 디코더부(100)에 의해서는 상기 톤의 단속비에 대응하는 카덴스 데이타를 출력하고 또한 상기 주파수 디코더(200) 및 주파수 조합부(300)에 의해서는 상기 톤의 주파수에 대응하는 주파수 데비타를 출력하게한 다음, 상기 카덴스데이타 및 주파수 데이타가 출력버퍼부(500)를 통해 소정제어신호 인가상태에 따라 출력되게한 것을 특징으로 하는 톤 디코더.A tone decoder of a switching device or a terminal device, comprising: a cadence decoder unit 100 for detecting an intermittent ratio of an input predetermined tone and outputting cadence data corresponding to the intermittent ratio; and the tone having a predetermined single frequency or a complex frequency. A frequency decoder 200 which detects a frequency of the signal and outputs one or a plurality of frequency recognition signals corresponding thereto, and frequency data corresponding to the output of the frequency recognition signal according to a logic state preset to a predetermined frequency combination state. The frequency combining unit 300 to output the output buffer unit 500 for outputting the frequency data and the cadence data according to an application state of a predetermined control signal, and the cadence decoder unit 100 or the frequency decoder unit 200. And a data recognition unit 400 for outputting a data recognition signal in response to a tone recognition state, wherein the cadence decoder unit 100 Outputs the cadence data corresponding to the intermittent ratio of and outputs the frequency delta corresponding to the frequency of the tone by the frequency decoder 200 and the frequency combination unit 300, and then the cadence data and the frequency data. Is output according to a predetermined control signal application state through the output buffer unit (500). 제1항에 있어서, 상기 주파수 조합부(300)는 주파수 디코더부(200)의 출력단에 대응하여 접속된 다수의 입력선택단자와 그에 대응하는 다수쌍의 출력선택 단자를 갖는 단자조합부(65)와 상기 출력선택단자 측에 그 입력단이 대응하여 접속된 다수의 논리소자로 구성함을 특징으로 하는 톤 디코더.The terminal combination unit (65) of claim 1, wherein the frequency combination unit (300) has a plurality of input selection terminals connected corresponding to the output terminals of the frequency decoder unit (200) and a plurality of pairs of output selection terminals corresponding thereto. And a plurality of logic elements whose input ends are correspondingly connected to the output selection terminal side. 제2항에 있어서, 상기 다수의 논리소자는 NOR게이트로 됨을 특징으로 하는 톤 디코더.3. The tone decoder of claim 2, wherein the plurality of logic elements are NOR gates. 제1항에 있어서, 상기 데이타인지부(400)는 주파수 조합부(300)의 출력신호를 입력하는 OR게이트(67)와 상기 OR게이트(67)의 출력신호를 클록입력단으로 입력하는 D-형플립플롭(68)과 상기 D-형플립플롭(68)의 출력신호를 일입력단으로 하고 상기 카덴스 디코더부(100)의 출력신호를 타 입력단으로 하는 OR게이트(69)로 접속하여 구성함을 특징으로 하는 톤 디코더.The D-type input circuit of claim 1, wherein the data recognizer 400 inputs an OR gate 67 for inputting an output signal of the frequency combiner 300 and an output signal of the OR gate 67 to a clock input terminal. And the output signal of the flip-flop 68 and the D-type flip-flop 68 as one input terminal, and the output signal of the cadence decoder unit 100 to the other input terminal. Tone decoder. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870010709A 1987-09-26 1987-09-26 Tone decoder in exchanges Expired KR900004468B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870010709A KR900004468B1 (en) 1987-09-26 1987-09-26 Tone decoder in exchanges

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870010709A KR900004468B1 (en) 1987-09-26 1987-09-26 Tone decoder in exchanges

Publications (2)

Publication Number Publication Date
KR890006041A true KR890006041A (en) 1989-05-18
KR900004468B1 KR900004468B1 (en) 1990-06-28

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ID=19264766

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870010709A Expired KR900004468B1 (en) 1987-09-26 1987-09-26 Tone decoder in exchanges

Country Status (1)

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KR (1) KR900004468B1 (en)

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KR900004468B1 (en) 1990-06-28

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