KR880011637A - Reset, Data Protection, and Automatic Restart Circuits in Systems Using Microprocessors - Google Patents

Reset, Data Protection, and Automatic Restart Circuits in Systems Using Microprocessors Download PDF

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Publication number
KR880011637A
KR880011637A KR870001983A KR870001983A KR880011637A KR 880011637 A KR880011637 A KR 880011637A KR 870001983 A KR870001983 A KR 870001983A KR 870001983 A KR870001983 A KR 870001983A KR 880011637 A KR880011637 A KR 880011637A
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KR
South Korea
Prior art keywords
circuit
memory
reset
automatic restart
power
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Application number
KR870001983A
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Korean (ko)
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KR890003751B1 (en
Inventor
박승건
Original Assignee
강진구
삼성반도체통신 주식회사
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Priority to KR1019870001983A priority Critical patent/KR890003751B1/en
Publication of KR880011637A publication Critical patent/KR880011637A/en
Application granted granted Critical
Publication of KR890003751B1 publication Critical patent/KR890003751B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

마이크로 프로세서를 이용한 시스템에 있어서의 리세트, 데이터보호 및 자동 리스타트회로Reset, Data Protection, and Automatic Restart Circuits in Systems Using Microprocessors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 블럭도.2 is a block diagram according to the present invention.

제3도는 본 발명에 따른 제2도의 구체회로도.3 is a detailed circuit diagram of FIG. 2 in accordance with the present invention.

제4도는 제2도의 블록도중 저전압 감지부(30)의 출력파형도.4 is an output waveform diagram of the low voltage detector 30 in the block diagram of FIG.

Claims (1)

시스템을 초기화 할수 있는 리세트회로(10)와, 각 시스템의 입력을 체크하여 프로그램에 따라 처리하여 제어 및 데이터를 출력하는 중앙처리장치(100)를 구비한 시스템에 있어서, 프로그램이 비정상적으로 수행될 시 이를 감지하여 상기 중앙처리장치(100)를 리세트 시킨 후 시스템을 작동으로 리스타트 시키는 자동리스타트 회로(20)와, 전원전압이 변동되더라도, 전원이 온과 오프점에서만 스위칭되도록 히스테리시스 특정에 비교되어 입력 전압을 감지하는 저전압감지부(30)와, 상기 저전압감지부(30)로부터 정상동작시 상기 중앙처리장치(100)로부터 칩 실렉터 어드레스 신호를 받아 기입/독출 신호에 따라 메모리를 억세스하며 비정상 작동시 데이터 기압을 방지하는 기입방지회로(40)와, 상기 리세트회로(10)와 자동리스타트회로(20)의 출력을 논리곱하는 게이트회로(50)와, 상기 저전압감지부(30)의 출력에 의해 시스템에 전원 공급 및 충전용 건정지로 충전하도록 하며 전원전압변동시 재충전용 건전지로부터 충전된 전원을 전원전압으로 공급할 수 있도록 하는 밧데리 및 충전회로(60)와, 시스템의 메모리 확장에 따른 메모리 영역을 선택할 수 있는 메모리 선택회로(70)와, 상기 밧데리 및 충전회로(60)로부터 전원을 받아 메모리 선택회로(70)의 메모리 영역 선택에 의해 상기 중앙처리장치(100)의 제어로 억세스하는 메모리부(90)로 구성됨을 특징으로 하는 마이크로 프로세서를 이용한 시스템에 있어서 리세트, 데이터보호 및 자동 리스타트회로.In a system having a reset circuit 10 capable of initializing a system and a central processing unit 100 that checks an input of each system and processes it according to a program to output control and data, the program may be abnormally executed. The automatic restart circuit 20 which detects the time and resets the CPU 100 and restarts the system in operation, and the hysteresis specific so that the power is switched only at the on and off points even when the power supply voltage is changed. The low voltage detection unit 30 which compares and senses an input voltage, receives a chip selector address signal from the CPU 100 during normal operation from the low voltage detection unit 30, and accesses a memory according to a write / read signal. The write prevention circuit 40 which prevents data atmospheric pressure during abnormal operation and the output of the reset circuit 10 and the automatic restart circuit 20 By the output circuit 50 and the output of the low voltage detection unit 30 to charge the system to the power supply and charge dry stop and to supply the power supplied from the rechargeable battery to the power voltage when the power supply voltage changes A battery and charging circuit 60, a memory selection circuit 70 capable of selecting a memory area according to memory expansion of the system, and a memory area of the memory selection circuit 70 receiving power from the battery and charging circuit 60; A reset, data protection and automatic restart circuit in a system using a microprocessor, characterized in that it comprises a memory unit (90) accessed by control of the central processing unit (100) by selection. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019870001983A 1987-03-05 1987-03-05 Reset, Data Protection, and Automatic Start-Start Circuits in Microprocessor-Based Systems KR890003751B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870001983A KR890003751B1 (en) 1987-03-05 1987-03-05 Reset, Data Protection, and Automatic Start-Start Circuits in Microprocessor-Based Systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870001983A KR890003751B1 (en) 1987-03-05 1987-03-05 Reset, Data Protection, and Automatic Start-Start Circuits in Microprocessor-Based Systems

Publications (2)

Publication Number Publication Date
KR880011637A true KR880011637A (en) 1988-10-29
KR890003751B1 KR890003751B1 (en) 1989-10-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870001983A KR890003751B1 (en) 1987-03-05 1987-03-05 Reset, Data Protection, and Automatic Start-Start Circuits in Microprocessor-Based Systems

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Publication number Publication date
KR890003751B1 (en) 1989-10-04

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