JPH04359309A - Reset circuit for microcomputer device - Google Patents

Abstract

PURPOSE:To easily constitute a circuit which recognizes power-on reset for power-on and reset due to the other factors to perform the reset processing corresponding to each factor. CONSTITUTION:A CPU 3 having the non-maskable interrupt function (NMI function) is used, and the processing is performed in accordance with software held in a memory 5 as follows; flag data is read in from a specific flag area in the memory 5 simultaneously with input of a CPU reset command signal from a register 4 and is compared with a specific value indicating the other reset factors, and this specific value is written in the flag area and the power-on reset processing is performed in the case of disaccord as the result of comparison, but the reset processing due to the other factors is performed otherwise, and contents of the flag area are forcibly set to flag data for power-on by the NMI function if a power source 1 outputs an abnormality signal PF/L.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit used for internal control of a microcomputer device, and more particularly to a reset circuit for distinguishing between a power-on reset at power-on and a reset caused by other factors.

0002

2. Description of the Related Art The scope of application of microcomputer devices is expanding year by year. Recently, the role of microprocessors (Central Processing Units, hereinafter referred to as CPUs) has become more diverse, and they are used in a wide range of systems, from single CPU systems to multi-CPU systems, so the configuration of their reset circuits is highly versatile. There must be. Therefore, among the reset circuits, the circuit configuration of the power-on reset status circuit when the power is turned on is quite complicated.

FIG. 5 shows a configuration diagram of a general reset circuit in a microcomputer device. In the figure, 10 is a power supply device, 11 is a reset IC that outputs a signal when the voltage is below a predetermined voltage value, 12 is an interrupt circuit, and 13 is a CPU.

[0004] The power supply 10 converts the primary voltage (AC) into a secondary voltage (DC) and supplies it to the CPU board.
An abnormality signal PF/L (/L means a Low signal and the same applies hereinafter) is input to the interrupt circuit 12. Further, a power-off signal PDOWN/L output from the reset IC 11 is also input to the interrupt circuit 12 .

FIG. 6 is an operation timing diagram for explaining the operation of the reset circuit having the above configuration. In the figure, (
1) to (3) are CPU reset command signals CPURESE
It shows the point in time when the CPU 13 starts operating after being reset by T/L, (1) is a power-on reset when the power is turned on, (2) is another manual reset, (
3) is a reset that occurs when the reset IC 11 detects a slight fluctuation in the secondary voltage (DC) due to a momentary interruption of the power supply 10 or the like.

However, in the reset circuit configured as described above, there is no way to determine what factor caused the reset. Therefore, there is a drawback that software processing cannot be performed in accordance with each case.

Conventionally, a reset circuit having the configuration shown in FIG. 7 has been used to distinguish between power-on reset and other resets. In FIG. 7, 20 is a reset IC, 21 is a CPU, 22 is a flip-flop circuit, 23 is a decoder, 24 is a status read register, 25 and 26 are NAND circuits with inverted inputs, and 27 is a NOR circuit with inverted inputs. The components are placed on the CPU board. Note that the reset IC 20 has the same function as the reset IC 11 shown in FIG.

Next, the operation of the reset circuit having the above configuration will be explained.

[0009] The moment the power is turned on to the CPU board,
Power-off signal PDOWN output from reset IC20
Since /L has not yet reached the predetermined voltage value, the set terminal S of the flip-flop circuit 22 is at a low level.
is input. Further, this power-off signal PDOWN/L is applied to the reset terminal R of the CPU 21 via the NOR circuit 27.
The voltage is also input to ESET and reset is applied to the voltage at which the CPU 21 can fully operate.

After that, the power-off signal PDOW/L becomes High.
When the level becomes h level and the reset of the CPU 21 is released, the CPU 21 first accesses the register 24 in order to read the reset factor set in advance. This access is performed by the address signal ADDR output from the CPU 21.
The decoder 23 decodes the ESS and outputs the output signal REGS.
While inverting EL/L to the NAND circuit 26, C
This is done by inverting the read command signal IORD/L from the PU 21 to the NAND circuit 26 and inputting the enable signal REGENB/L output from the NAND circuit 26 to the enable terminal ENB of the register 24.

The reset cause data output from the register 24 is taken into the CPU 21 via the data bus. The cause of the reset is then identified, and if the power-on reset bit is set, power-on reset processing is performed.

This power-on reset process mainly involves initializing peripheral ICs, but at the end of the process, the power-on reset factor must be cleared. Otherwise, when another reset is applied to the CPU 21, it will not be possible to identify the cause of the reset. Therefore, the address signal AD for clearing the flip-flop circuit 22 in advance is
DRESS is determined, and the address signal AD at this time is
Output signal FFSE of decoder 23 corresponding to DRESS
The AND condition of L/L and the IOWR/L signal output from the CPU 21 is detected by an inverting input NAND circuit 25 to generate a PORCLR/L signal, which is input to the clear terminal R of the flip-flop circuit 22. The POR/L signal input to the register 24 is negated.

As described above, the flip-flop circuit 22 has conventionally been an essential component in constructing a power-on reset status circuit.

[0014]

However, as is well known, once the flip-flop circuit 22 is set to a certain value, it continues to maintain that state unless it is cleared. A circuit had to be provided to clear the flip-flop circuit 22. Therefore, the circuit configuration of the reset circuit has become complicated, leading to deterioration in operating efficiency and reliability.

The present invention was devised in view of such problems, and its purpose is to be able to distinguish between a power-on reset and a reset caused by other factors without using a flip-flop circuit or a decoder. An object of the present invention is to provide a reset circuit for a microcomputer device.

[0016]

[Means for Solving the Problems] The structure of the present invention for achieving the above object includes a non-maskable interrupt function (NM
This is a reset circuit that performs power-on reset processing when power is turned on to a microcomputer device and reset processing due to other factors using a CPU with I function), which converts primary voltage (AC) to secondary voltage (DC). A power supply that outputs an abnormal signal when the primary voltage is cut off, and a status circuit that inputs a reset command signal to the CPU, differs depending on when the power is turned on and other reset factors. a memory having a flag area in which flag data is set, selectively writing and reading the flag data to and from the CPU, and holding software for operating the CPU; According to the software, at the same time as the reset command signal is input, the flag data is read from the memory and compared with a specific value representing another reset factor, and if the result of the comparison is a different value, the specific value is changed to Power-on reset processing is performed while writing to the flag area, and if the values are the same, reset processing is performed due to other factors, and when the power supply outputs an abnormal signal, the contents of the flag area are written to the flag data at power-on. The feature is that it is forcibly set to .

[0017]

[Operation] When a power-on reset is applied, an abnormality signal is output from the power supply to the CPU in advance, and the flag data at power-on is set in the flag area by the NMI function of the CPU. Therefore, when the data is read into the CPU and compared with specific values representing other reset factors, the two values are different, so it can be easily recognized that this reset is not caused by other factors. In this case, power-on reset processing is performed after setting the flag area to a specific value.

On the other hand, when the power supply is normal but a reset is applied due to other factors, a specific value is set in the flag area. Therefore, when the CPU reads the data and compares it with the specific value, they are the same, so
It is easy to recognize that this reset is not a power-on reset.

Note that if the power supply outputs an abnormal signal after setting a specific value in the flag area, the CPU's NMI
The function resets the flag area to the state it was in when the power was turned on, so it can be recognized even if power-on resets occur continuously.

[0020]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 is a configuration diagram of a reset circuit according to an embodiment of the present invention. In this figure, 1 is a power supply, 2 is a reset IC, 3 is a CPU with an NMI function, that is, a non-maskable interrupt function, 4 is a register for reading NMI factors, 5 is a memory with a specific flag area,
6 is a NAND circuit with an inverting input. For example, a dynamic memory (DRAM) is used as the memory 5, and the memory state when the power is turned on is "0000" or "FFFF".
” (easily).

The power fail signal PF/L from the power supply 1 and other signals that cause NMI are inverted input to the NAND circuit 6, and these signals are also branched to the register 4. The output of the NAND circuit 6 is the CPU
The CPU reset command signal CPURESET/L output from register 4 to the NMI terminal of CPU 3 is the IO of CPU 3.
They are respectively input to the RD terminals. Further, the power-off signal PDOWN/L from the reset IC 2 is input to the CPU 3, and the CPU 3 is connected to the memory 5 via a data bus. In this embodiment, the reason why the CPU 3 is provided with the NMI function is that the flag area for determining power-on reset is cleared by the NMI using the power fail signal PF/L. This is because if it is performed as an integrated process, the CPU 3 may stop before the flag area is cleared because it takes too much time to execute the process.

Note that the reset IC 2, register 4, and NA
The ND circuit 6 constitutes a status circuit for inputting a reset command signal to the CPU 3.

Next, the operation of the reset circuit according to this embodiment will be explained with reference to FIGS. 2 to 4.

FIG. 2 is an operation timing diagram of the reset circuit configured as described above, and FIGS. 3 and 4 are flowcharts of the reset process. In these figures, (4) to (16) indicate the state of the reset circuit at each point in time and the processing of each part at that time. I will explain step by step.

(4) CPU reset signal C at the bottom of FIG.
When PURESET/L changes from Low level to High level, the reset circuit starts the reset process. Specifically, first, data in a specific flag area in the memory 5 is read to the CPU 3, and a specific value representing this and other predetermined reset factors is read, for example, "1234.
” compared with the data. Referring to FIG. 2, this reset factor is due to the power-off signal PDOWN/L going high, and the data in the flag area of the memory 5 is normally "0000" or "FFFF".
”. Therefore, since both data do not match, the process moves to the N side (5) in FIG. 3.

(5) The CPU 3 determines that this reset cause is due to a power-on reset, writes the specific value "1234" in the flag area, and uses it as a determining factor for subsequent reset causes. After writing, the process moves to (6).

(6) Perform initialization at power-on reset and end the reset process.

(7) CPU reset signal CPURESE
After T/L once turned to Low level, it became High level again, so the process in (4) above is performed in the same way. At this time, since data "1234" has been written in the flag area, the process moves to the Y side (8) in FIG. 3.

(8) The CPU 3 determines that this reset cause is due to another reset, performs initialization for other resets, and ends the reset process.

(9) The abnormality signal PF/L becomes Low level, and the NMI process in FIG. 4 is started. This NM
Since I is due to the power fail signal PF/L, the process is shifted to the Y side (10) in FIG. 4.

(10) Clear the flag area of memory 5 and end the NMI processing.

(11) Power-off signal PDOWN/L is Lo
The level becomes W, "0000" or "FFFF" is written in the flag area, and the power-on reset state is entered.

(12) CPU reset signal CPURES
ET/L becomes High level and the process (4) above is performed. At this time, since the data in the flag area is not "1234", the process moves to the N side (13) in FIG. 3.

(13) Write "1234" in the flag area and use it as a determining factor for subsequent reset factors. The process moves to (14).

(14) Perform initialization at power-on reset and end the reset process. (15) The abnormality signal PF/L becomes Low level again, and the NMI process in FIG. 4 is started. This NM
Since I is due to the abnormal signal PF/L, the Y side of Fig. 4 (
16).

(16) Clear the flag area of memory 5 and end the NMI processing.

(17) Note that in the case of NMI due to something other than the abnormal signal PF/L, the process shifts to the N side (18) in FIG. (18) Do not clear the flag area, perform other processing, and end the NMI processing.

As described above, in the reset circuit according to this embodiment, when a power-on reset is applied, the abnormal signal PF/L is output from the power supply 1 to the CPU 3 in advance, and the
Due to the NMI function of PU3, flag data (0000 or FFF) is stored in the flag area of memory 5 when the power is turned on.
F) is set. Therefore, the data is read into the CPU 3 and a specific value "
1234", the two values are different, so
It can be easily recognized that this reset is not caused by other factors.

On the other hand, if the power supply 1 is normal but has been reset due to other factors, the specific value "
1234" is set. Therefore, CPU3
When the data is read and compared with the specific value "1234", they are the same, so it can be easily recognized that this reset is not a power-on reset.

[0041] Also, after the power-on reset is applied and the specific value "1234" is set in the flag area, the power supply 1
outputs the abnormal signal PF/L, the NA of the inverted input
The ND circuit 6 detects this and outputs a signal to the NMI terminal of the CPU 3. This causes an NMI, and the flag area is reset to the state at power-on (0000 or FFFF). Therefore, even if power-on resets are applied continuously, this can be recognized.

In this embodiment, a DRAM is used as the memory 5. However, if a memory other than a DRAM is used, the number of digits in the flag area may be increased. This reduces the probability that the random data at power-on and the specific value match, and can prevent misrecognition.

[0043]

[Effects of the Invention] As explained above, according to the reset circuit for a microcomputer device according to the present invention, various reset factors can be correctly recognized and reset processing (initialization processing) corresponding to each factor can be appropriately performed. be able to. In addition, in this reset circuit, even if the data in the flag area in the memory is in an undefined state due to a momentary power cut, etc., an NMI is caused by an abnormal signal that detects a power abnormality, and this NMI processing is performed. Since the flag area is set to the state at power-on, reliable power-on reset processing is performed.

Moreover, since this reset circuit does not use a flip-flop circuit or a decoder for maintaining status as in the conventional case, the amount of hardware can be greatly reduced, and operational efficiency and reliability can be improved. .

Furthermore, since a series of operational controls are performed by software, it is highly versatile and easy to handle.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a reset circuit of a microcomputer device according to an embodiment of the present invention.

FIG. 2 is an operation timing diagram for explaining the operation of the reset circuit.

FIG. 3 is a flowchart for explaining reset processing in the reset circuit.

FIG. 4 is a flowchart for explaining NMI processing in the reset circuit.

FIG. 5 is a configuration diagram of a general reset circuit of a microcomputer device.

FIG. 6 is an operation timing diagram for explaining the operation of the reset circuit.

FIG. 7 is a configuration diagram of a conventional reset circuit for recognizing power-on reset.

[Explanation of symbols]

1, 10...power supply, 2,11,20...reset IC,
3, 13, 21...Microprocessor (CPU), 4,
24...Register, 5...Memory.

Claims (1)

[Claims] [Claim 1] Non-maskable interrupt function (NMI
A reset circuit that performs power-on reset processing when the microcomputer device is powered on and reset processing due to other factors using a microprocessor having a function), which converts primary voltage (AC) to secondary voltage (DC). a power supply that supplies the power to the microprocessor and outputs an abnormal signal when the primary voltage is cut off; a status circuit that inputs a reset command signal to the microprocessor; a memory having a flag area in which different flag data is set, selectively writing and reading the flag data to and from the microprocessor, and holding software for operating the microprocessor; According to the software, the microprocessor reads the flag data from the memory at the same time as the input of the reset command signal and compares it with a specific value representing another reset factor, and if the result of the comparison is a different value, Writes the specific value in the flag area and performs power-on reset processing, and when the values are the same, performs reset processing due to other factors, and
A reset circuit for a microcomputer device, characterized in that when the power supply outputs an abnormal signal, the NMI function forcibly sets the contents of the flag area to the flag data at power-on.