KR880001978Y1 - Least significant digit position generaling circuit by rounding off - Google Patents

Abstract

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Description

Position generating circuit of rounded minimum unit

1 is a circuit diagram of the present invention.

2 is a timing chart when counting down.

3 is a timing chart in the case of counting down.

* Explanation of symbols for main parts of the drawings

1: Multiplexer 2: D flip flop

3: toe flip-flop 4: down-counter

AD ₁ , AD ₂ : AND gate NR ₁ : Noah gate

ND ₁ , ND ₂ : NAND gate SW ₁ : Inverting switch

The present invention is a nominal controller that controls a DC servo motor using a microprocessor or precisely controls the position of an XY table using a ball screw. A position generating circuit of a rounded minimum unit that generates position information and executes a counter shut down operation.

At present, the trend of increasing labor force and unmanned manufacturing industry is increasing, among which automation process (assembly, measurement, packing, transportation, warehouse automation, etc.) is emerging.

Here, in the dedicated machine for automatically inserting the radial type of components in the assembly automation equipment, in order to control the motor, the position control was performed in decimal units by counting down or down using the phase signal of the encoder. In addition, when performing position control corresponding to 1/2 of the minimum unit in the position control of the decimal unit, a separate counter has to be added to round the value in software.

The present invention obtains the position precision by 2 times the minimum unit through the circuit that generates the minimum position information corresponding to 1/2 of the minimum unit in the decimal minimum unit, and automatically processes the rounding process to Simple software, rounded minimum unit that can arbitrarily control the rotation direction of the motor by exchanging the input order of the A and B phases by using the multiplexer and the switch in the process of processing the A and B phases of the double encoder. The purpose is to provide a position generating circuit of.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a plurality of D-type flip flops 2 are connected to a multiplexer ₁ to which an inversion switch SW ₁ is connected, and an AND gate AD ₁ (AD 2) to the D-type flip flops _2. The NOR gate NR ₁ and the NAND gate ND ₁ (ND ₂ ) are respectively connected to each other through N, and the NOR gate NR ₁ is connected to the NAND gate ND ₁ (TOC) via a toe flip-flop 3. ND ₂ ) is connected to the NAND gate ND ₁ and ND ₂ . The down counter 4 is connected.

Reference numerals A and B denote encoder phase signals, 4D, 3D and 4Q, 4, 3Q, and 3Q denote I / O terminals of a D flip-flop.

1 is a circuit diagram of the present invention having the above-described structure, and the A and B phase signals transmitted from the encoder of the motor are represented by (2-2) and (2-3) signals in FIG. 2 and (3- in FIG. 2) and (3-3) are supplied to the pressure stage of the multiplexer 1, and the system clock signal is multiplexed as the (2-1) signal in FIG. 2 and the (3-1) signal in FIG. It is supplied to the clock stages of the servo 1 and the D flip-flop 2, and the A and B phase signals of the encoder are synchronized with the system clock signal by the multiplexer 1. First, in the case of counting down, according to FIG. 2, the clock of the multiplexer 1 is delayed by one clock like the signals of (2-4) and (2-5). The input terminal 4D and _one gate of the AND gate AD ₁ and AD ₂ are input to the input terminal 4D, and then the D clock flip delayed signals 4Q, 3Q and " T-1 " Signal of (2-8) (2-7) (2-6) (2-9) is supplied to the other input of AND gate (AD ₁ ) (AD ₂ ), whereby AND gate (AD ₁ ) ( Is supplied to the other input terminal of AD ₂ , and thus the output signal of AND gate AD ₁ (AD ₂ ) is the (2-10) and (2-11) signals as the input terminal of NOR gate NR ₁ and the NAND gate. It is input to one input terminal of (ND ₁ ) (ND ₂ ). Here, the output signal of the AND gate AD ₁ represents the rotation direction information of the motor, and the output signal of the AND gate AD ₂ is a signal necessary for generating the count shut pulse. In addition, the noise gate NR ₁ combines the output signals of the AND gates AD ₁ (AD ₂ ) and transmits a signal such as (2-12) to be supplied to the cool end of the toggle flip-flop 3, wherein the toggle The output terminal signal of the flip-flop 3 is a signal of (2-14) and is supplied to the CPU as a position information positive signal corresponding to 1/2 of the minimum decimal unit.

In addition, in FIG. 2, since signals of (2-10) (2-11) (2-13) (2-14) are inputted to the NAND gate, (2-15) (2-16) Signal is applied to enable decimal position control.

Therefore, the CPU reads the signal (2-14) from the A and B phase signals of the encoder through the optical tablet to determine that there is a half value of the decimal minimum unit in the high level, and 1 in the low level. It can be determined that the value / 2 does not exist.

On the other hand, in the case of counting down, as shown in FIG. 3, the output terminal of the multiplexer 1 is delayed by one clock like the signals of (3-4) and (3-5), and thus the input terminal of the D-type flip-flop 2 ( 4D) and an input of one of the AND gates AD ₁ (AD ₂ ), and then the D-type flip-flop 2 again has one clock delayed signal (4Q, 3Q, , ) Is sequentially supplied with the signals of the (3-8) (3-7) (3-6) (3-9) to the other input terminal of the AND gate (AD ₁ ) (AD ₂ ), accordingly the AND gate (AD ₁₎ The output signal of (AD ₂ ) is input to the input terminal of NOR gate NR ₁ and _one input terminal of NAND gate ND ₁ (ND ₂ ) as (3-10) and (3-11) signals.

The AND gate output signal of the (AD ₁₎ indicates the direction of rotation information of the Motor and the output signal of the AND Gade (AD ₁₎ is a signal required for generating the count-down pulse. In addition, the NOR gate NR ₁ combines the output signals of the AND gates AD ₁ (AD ₂ ), sends a signal such as (3-12), and is supplied to the clock terminal of the toggle flip-flop 3, where the toggle The output terminal signal of the flip-flop 3 is a signal of (3-14) and is supplied to the CPU as a position information signal corresponding to 1/2 of the minimum decimal unit.

Since the signals of (3-10) (3-11) (3-13) (3-14) of FIG. 2 are input to the NAND gate, the (3-15) and ( 3-16) Signal is applied to enable decimal position control.

Therefore, the signal (3-14) is read from the A and B phase signals of the encoder through the above process from the CPU, and it is determined that there is a half value of the decimal minimum unit in the high level and 1 in the low level. You can determine that the value / 2 does not exist. In addition, the inversion switch SW ₁ selects the word of the multiplexer 1 to invert the phases of the a and b signals, thereby easily inverting the rotational direction of the motor, and observes the cases of FIGS. 2 and 3. In the case of counting down and counting down, the value of 1/2 of the minimum decimal unit becomes high at the point of 1/4 of the minimum decimal unit, and 1 / of the minimum decimal unit at 3/4 of the minimum decimal unit. As the value of 2 goes low, the hardware rounding operation increases the value of the minimum decimal unit by one.

As described above, the present invention can obtain 1/2 minimum position information using the decimal counter's down counter as it is, and is rounded, so the actual position control error is 1/4 of the position of the decimal counter. If you use the other method, the frequency of encoder pulse should be 10 times higher, but the minimum unit position generating circuit does not have this restriction, and even if there are many encoder pulses, you need to round the encoder pulse in software to obtain the minimum unit position of 1/2. The CPU only needs to have minimal position information, and there is an advantage that the rotation direction of the motor can be easily reversed by operating the reverse switch.

Claims (1)

A plurality of D-type flip-flops 2 are connected to the multiplexer ₁ to which the inversion switch SW ₁ is connected, and the D-type flip-flop 2 is connected to an AND gate AD ₁ (AD ₂ ). NOR gate (MR ₁₎ and NAND gate (ND ₁₎ and (ND ₂₎ is connected to each of the NOR gate (NR _1), the toggle flip-flop (3) the parameters to the NAND gate (ND _1), (ND ₂₎ is The NAND gate ND ₁ and ND ₂ are connected to the down counter 4 to process the A and B signals of the encoder and to round them, and to provide a position control information signal corresponding to 1/2 of the minimum decimal unit. Position generating circuit of the smallest rounded unit to be generated.