KR870006783A - Integrated circuit for composite synchronizing signal separation and high frequency digital synchronizing signal separation - Google Patents

Integrated circuit for composite synchronizing signal separation and high frequency digital synchronizing signal separation Download PDF

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Publication number
KR870006783A
KR870006783A KR1019850009320A KR850009320A KR870006783A KR 870006783 A KR870006783 A KR 870006783A KR 1019850009320 A KR1019850009320 A KR 1019850009320A KR 850009320 A KR850009320 A KR 850009320A KR 870006783 A KR870006783 A KR 870006783A
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KR
South Korea
Prior art keywords
level
circuit
signal
predetermined
synchronizing signal
Prior art date
Application number
KR1019850009320A
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Korean (ko)
Other versions
KR890003222B1 (en
Inventor
신명철
김영생
장영욱
Original Assignee
강진구
삼성반도체통신 주식회사
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Priority to KR1019850009320A priority Critical patent/KR890003222B1/en
Publication of KR870006783A publication Critical patent/KR870006783A/en
Application granted granted Critical
Publication of KR890003222B1 publication Critical patent/KR890003222B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음.No content.

Description

합성 동기신호 분리 및 고주파 디지탈 동기신호 분리용 직접회로Integrated circuit for composite synchronizing signal separation and high frequency digital synchronizing signal separation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 합성동기 신호분리 및 고주파 디지탈 동기 신호 분리용 집적회로의 블럭도.2 is a block diagram of an integrated synchronous signal separation and a high frequency digital synchronous signal separation integrated circuit according to the present invention.

제3도는 제2도의 본 발명에 따른 블럭도의 일실시예의 구체회로도.3 is a concrete circuit diagram of one embodiment of a block diagram according to the present invention of FIG.

제4도는 제3도의 각 부분의 동작 파형도.4 is an operational waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 고주파버퍼회로 12 : 증폭회로10: high frequency buffer circuit 12: amplification circuit

16 : 제1비교회로 18 : 제2비교회로16: to the first non-church 18: to the second non-church

20 : 드라이브회로 22 : 저주파필터20: drive circuit 22: low frequency filter

24 : 합성동기 분리회로24: Synthetic synchronous separation circuit

Claims (2)

문자방송의 디지탈 동기클럭과 합성동기신호를 분리하는 회로에 있어서, 입력하는 합성비디오 신호를 외율 및 위상차없이 출력하는 차동 증폭기로 구상한 버퍼증폭기로 된 고주파 버퍼회로(10)와, 상기 합성 비디오 신호중 디지탈 동기 신호만을 공진시켜 증폭하는 증폭회로(12)와 상기 증폭된 디지탈 동기신호를 입력하여 소정의 직류레벨에 실어 출력하는 제1비교기(16)와, 상기 소정의 직류레벨 이상의 신호를 제거하고 소정의 직류레벨 이하의 신호만을 출력하는 제2비교기(18)와, 상기 제2비교기에서의 출력하는 소정의 직류레벨에서 도통되고 상기 소정의 직류 레벨이하의 전압에서 오프되어 소정레벨(VBB)의 동기클럭펄스를 제생하는 드라이브회로(20)와, 합성비디오 신호중 수평동기 신호만 통과시키는 저주파필터(22)와, 상기 수평동기신호에서만 오픈동작을 하여 소정레벨의 펄스를 출력하는 스위칭회로로만 합성동기분리회로(24)로 구성됨을 특징으로 하는 회로.A circuit for separating a digital synchronization clock and a composite synchronization signal for character broadcasting, comprising: a high frequency buffer circuit (10) consisting of a buffer amplifier designed by a differential amplifier for outputting an input composite video signal without an external rate and a phase difference; An amplifying circuit 12 which resonates and amplifies only the digital synchronizing signal, a first comparator 16 which inputs and outputs the amplified digital synchronizing signal to a predetermined DC level, and removes a signal having the predetermined DC level or more, A second comparator 18 for outputting only a signal below a DC level of? And a predetermined DC level output from the second comparator, turned off at a voltage below the predetermined DC level, and being at a predetermined level V BB ? A drive circuit 20 for generating synchronous clock pulses, a low frequency filter 22 for passing only a horizontal synchronous signal of a composite video signal, and the horizontal synchronous signal only Peun the operation circuit characterized by a switching circuit composed of only synthetic sync separation circuit 24 for outputting a pulse of a predetermined level. 제 1항에 있어 제 2비교회로(18)가 트랜지스터(Q34)(Q35)의 에미터에 제너다이오우드(ZD1)(ZD2)를 접속하고 저항(R30)(R31)을 접속하여 트랜지스터(Q36)(Q37)(Q38)로 구성되는 정전류원에 접속한 구성으로하여 트랜지스터(Q35)의 베이스 직류전압레벨 이상의 전압을 바이패스시키고 그 이하의 전압을 출력하는 것을 특징으로 하는 회로.The second non-intersection 18 connects the zener diodes ZD 1 and ZD 2 to the emitters of transistors Q 34 and Q 35 , and connects resistors R 30 and R 31 . Connected to a constant current source composed of transistors Q 36 , Q 37 , and Q 38 to bypass a voltage above the base DC voltage level of transistor Q 35 and output a voltage below that. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850009320A 1985-12-11 1985-12-11 Integrated circuit for composite synchronizing signal separation and high frequence digital synchronizing separation KR890003222B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850009320A KR890003222B1 (en) 1985-12-11 1985-12-11 Integrated circuit for composite synchronizing signal separation and high frequence digital synchronizing separation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850009320A KR890003222B1 (en) 1985-12-11 1985-12-11 Integrated circuit for composite synchronizing signal separation and high frequence digital synchronizing separation

Publications (2)

Publication Number Publication Date
KR870006783A true KR870006783A (en) 1987-07-14
KR890003222B1 KR890003222B1 (en) 1989-08-26

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Application Number Title Priority Date Filing Date
KR1019850009320A KR890003222B1 (en) 1985-12-11 1985-12-11 Integrated circuit for composite synchronizing signal separation and high frequence digital synchronizing separation

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KR (1) KR890003222B1 (en)

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Publication number Publication date
KR890003222B1 (en) 1989-08-26

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