KR870005295A - Banking VRAM for Videotex Decode for Computers - Google Patents

Banking VRAM for Videotex Decode for Computers Download PDF

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Publication number
KR870005295A
KR870005295A KR1019850008932A KR850008932A KR870005295A KR 870005295 A KR870005295 A KR 870005295A KR 1019850008932 A KR1019850008932 A KR 1019850008932A KR 850008932 A KR850008932 A KR 850008932A KR 870005295 A KR870005295 A KR 870005295A
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KR
South Korea
Prior art keywords
video ram
banking
color
decode
video
Prior art date
Application number
KR1019850008932A
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Korean (ko)
Inventor
주필상
Original Assignee
정재은
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정재은, 삼성전자 주식회사 filed Critical 정재은
Priority to KR1019850008932A priority Critical patent/KR870005295A/en
Publication of KR870005295A publication Critical patent/KR870005295A/en

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Abstract

내용 없음No content

Description

컴퓨터용 비디오텍스 디코드를 위한 뱅킹 VRAMBanking VRAM for Videotex Decode for Computers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명을 나타내는 블럭도,1 is a block diagram showing the present invention,

제2도는 제1도를 구체로 도시하는 회로도,FIG. 2 is a circuit diagram showing the first diagram in a concrete manner;

제3도는 빨강 색상을 인에이블 하기 위한 각부 파형도.3 is a waveform diagram of each part to enable the red color.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 컴퓨터 2 : CRTC1: computer 2: CRTC

23 : 디코드 4 : 비디오 램선택 및 뱅킹회로23: Decode 4: Video RAM Selection and Banking Circuit

5 : 비디오 RAM 회로 6 : 병-직렬 변환쉬프트래지스터5: video RAM circuit 6: bottle-serial conversion shift register

7 : 비디오 제어기 8 : CRT7: video controller 8: CRT

F1-F2: D플립플롭 MUX : 디코드F 1 -F 2 : D flip-flop MUX: Decode

B1-B3: 버퍼 RR1-RR3: 빨강색상을 위한 비디오 램B 1 -B 3 : Buffer RR 1 -RR 3 : Video RAM for Red Color

RG1-RG3: 녹색색상을 위한 비디오 램 RB1-RB3: 푸른색상을 위한 비디오 램RG 1 -RG 3 : Video ram for green color RB 1 -RB 3 : Video ram for blue color

PS1-PS3: 병렬-직렬 쉬프트 레지스터 OR1-OR3: 오아 게이트PS 1 -PS 3 : Parallel-serial shift register OR 1 -OR 3 : OR gate

D0-D7: 데이타 버스 A0-A12: 어드레스 버스D 0 -D 7 : data bus A 0 -A 12 : address bus

BW : 기입신호 SP : 디 플립플롭 클럭BW: Write Signal SP: De-Flip-Flop Clock

MCL : 쉬프트 레지스터 클럭 SCL : 쉬프트 레지스터 S/L 신호MCL: Shift Register Clock SCL: Shift Register S / L Signal

Claims (1)

비디오 텍스를 위해 오는 정보를 받을 수 있도록 하며, 정보를 검색하여 볼 수 있도록 인터페이스한 컴퓨터(1)와, 데이타가 전송되는 데이터버스(10)와, 각 버퍼와 메모리장치 번지를 지정하는 어드레스버스(9)와, 상기 어드레스버스(9), 데이터버스(10)의 양 신호를 받아 CRT를 제어하는 CRT제어기(2)와, 상기 CRT제어기(2), 어드레스버스(9)의 신호를 받아 칩선택 신호를 출력하는 디코드(3)와, 디플립플롭(F1,F2), 오아개이트(OR1-OR3), 뱅킹버퍼(B1-B3)구성 하여 데이타신호(D0-D2)와 디플립플롭(F1,F2)의 클럭에 따라 뱅킹버퍼를 인에이블 되도록 하는 비디오 램 선택 및 뱅킹회로(4)와, 빨강 색상을 위한 비디오 램(RR1-RR3), 녹색 색상을 위한 비디오 램(RG1-RG3), 푸른 색상을 위한 비디오 램(RB1-RB3)을 구성하여 상기 디코드(MUX)의 비디오 램 칩 실렉터와 상기 오아게이트(OR1-OR3)의 출력에 따라 각 색상 비디오 램이 인에이블되는 비디오 RAM회로(5)와, 상기 각 색상 비디오 RAM회로(5)의 병렬데이타 출력을 쉬프트 레지스터 콜럭(MCL)와 SCL신호에 따라 직렬데이타로 변환시키는 병-직렬 변환쉬프트 레지스터(6)와, CRT제어기(2)의 제어신호에 따라 색상이(R, G, B)제어되어 비디오 제어기(7)와 표시부위 CRT(8)로 구성된 것을 특징으로 컴퓨터용 비디오 텍스 디코드를 위한 뱅킹 VRAM.A computer (1) interfaced to retrieve and view information coming from video text, a data bus (10) to which data is transmitted, and an address bus (address) to designate each buffer and memory device address ( 9) and a CRT controller 2 for controlling the CRT by receiving both signals of the address bus 9 and the data bus 10, and the chip selection by receiving the signals of the CRT controller 2 and the address bus 9; Data signal (D 0 -D) consisting of a decode (3) for outputting a signal, a deflip-flop (F 1 , F 2 ), an oagite (OR 1 -OR 3 ), and a banking buffer (B 1 -B 3 ) 2 ) and video ram selection and banking circuitry (4) to enable the banking buffer according to the clocks of the flip-flops (F 1 and F 2 ), and video ram (RR 1- RR 3 ) for the red color, green a video RAM for the color (RG 1 -RG 3), the video RAM for the color blue (RB 1 -RB 3) of the video RAM configuration, the decode (MUX) and the chip selector Iowa gate group (OR 1 -OR 3) according to an output circuit and a video RAM (5) which enable each color video RAM, shifting the parallel data output of each of the color video RAM circuit 5 of register kolreok (MCL) And the serial-to-serial conversion shift register 6 for converting the serial data according to the and SCL signals, and the color (R, G, B) is controlled according to the control signal of the CRT controller 2 so that the video controller 7 and the display portion are controlled. A banking VRAM for computer video decode decoding comprising a CRT (8). * 참고사항 : 최초출원 내용에 의하여 공개하는 것임.* Note: The disclosure is based on the original application.
KR1019850008932A 1985-11-29 1985-11-29 Banking VRAM for Videotex Decode for Computers KR870005295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850008932A KR870005295A (en) 1985-11-29 1985-11-29 Banking VRAM for Videotex Decode for Computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850008932A KR870005295A (en) 1985-11-29 1985-11-29 Banking VRAM for Videotex Decode for Computers

Publications (1)

Publication Number Publication Date
KR870005295A true KR870005295A (en) 1987-06-08

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ID=69468123

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850008932A KR870005295A (en) 1985-11-29 1985-11-29 Banking VRAM for Videotex Decode for Computers

Country Status (1)

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KR (1) KR870005295A (en)

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