KR870004583A - ADPCM codec circuit using digital signal processor - Google Patents

ADPCM codec circuit using digital signal processor Download PDF

Info

Publication number
KR870004583A
KR870004583A KR1019850007943A KR850007943A KR870004583A KR 870004583 A KR870004583 A KR 870004583A KR 1019850007943 A KR1019850007943 A KR 1019850007943A KR 850007943 A KR850007943 A KR 850007943A KR 870004583 A KR870004583 A KR 870004583A
Authority
KR
South Korea
Prior art keywords
data
unit
buffer
parallel
pcm
Prior art date
Application number
KR1019850007943A
Other languages
Korean (ko)
Other versions
KR880002134B1 (en
Inventor
이강석
정광영
Original Assignee
정재은
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정재은, 삼성전자 주식회사 filed Critical 정재은
Priority to KR1019850007943A priority Critical patent/KR880002134B1/en
Publication of KR870004583A publication Critical patent/KR870004583A/en
Application granted granted Critical
Publication of KR880002134B1 publication Critical patent/KR880002134B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

내용 없음No content

Description

디지탈 신호 처리용 프로세서를 사용한 ADPCM 코덱 회로ADPCM codec circuit using digital signal processor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 회로를 나타내는 블럭도.1 is a block diagram showing a circuit according to the present invention.

제2도는 제1도의 상세회로도.2 is a detailed circuit diagram of FIG.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

A : 필터/코덱 B : 쉬프트 로직부 C : 버퍼A: Filter / Codec B: Shift Logic C: Buffer

D : 인코더 E : 채널 디코더 F : 콘트롤부D: Encoder E: Channel Decoder F: Controller

G : 디코더 H : 클럭발생부G: Decoder H: Clock Generator

Claims (1)

아날로그 음성신호를 8 비트 PCM 신호로 변조하여 출력하는 필터/코덱(A)과,A filter / codec (A) for modulating and outputting an analog audio signal into an 8-bit PCM signal; 직렬 PCM 데이터를 병렬로 변환하는 S/P 부와 병렬 PCM 데이터를 직렬로 변환하는 P/S부로 이루어지는 쉬프트로직부(B)와A shift logic unit (B) comprising an S / P unit for converting serial PCM data in parallel and a P / S unit for converting parallel PCM data in series; 상기한 S/P 부의 출력 데이터를 일시 저장하는 버퍼(C)와,A buffer C for temporarily storing the output data of the S / P unit; 버퍼(C)에 저장된 데이터를 소정의 비트소로 부호화 하는 인코더(D)와,An encoder (D) for encoding data stored in the buffer (C) to a predetermined bit size; 인코딩할 데이터가 저장된 버퍼(C)의 어드레스를 선택하기 위한 데이터 셀렉터(U7)와 상기한 병렬 PCM 데이터를 직렬로 변환할 P/S 부의 어드레스를 선택하기 위한 데이터 셀렉터(U8)로 구성된 채널 디코더(E)와,A channel consisting of a data selector U 7 for selecting an address of a buffer C in which data to be encoded is stored and a data selector U 8 for selecting an address of a P / S unit for serially converting the parallel PCM data. Decoder E, 단안정 멀티 바이브레이터(U5)(U9)와 D 플립플롭 (U6)(U10) 및 4개의 낸드게이트(N2-N5)로 구성되어 인코딩 및 디코딩을 위한 제어신호를 발생하는 동시에 상기한 인코더(D)의 출력을 외부에 전송 또는 메모리에 저장하는 콘트롤부(F)와,Monostable multivibrator (U 5 ) (U 9 ), D flip-flop (U 6 ) (U 10 ) and four NAND gates (N 2 -N 5 ) to generate control signals for encoding and decoding A controller (F) for transmitting the output of the encoder (D) to the outside or storing it in a memory; 메모리에 저장된 데이터 혹은 전송되어온 데이터를 상기한 콘트롤부(F)를 통해 받아 병렬 PCM 데이터를 출력하는 디코더(G)와,A decoder G for receiving the data stored in the memory or the transmitted data through the control unit F and outputting parallel PCM data; 상기한 구성부(A,B,D,G,F)에 클럭 펄스를 공급하는 클럭발생부(H)등을 포함하여 이루어진 것을 특징으로 하는 디지탈 신호 처리용 프로세서를 사용한 ADPCM Z코덱회로.And a clock generator (H) for supplying clock pulses to the components (A, B, D, G, F). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850007943A 1985-10-26 1985-10-26 Adpcm codec circuit using dsp KR880002134B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850007943A KR880002134B1 (en) 1985-10-26 1985-10-26 Adpcm codec circuit using dsp

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850007943A KR880002134B1 (en) 1985-10-26 1985-10-26 Adpcm codec circuit using dsp

Publications (2)

Publication Number Publication Date
KR870004583A true KR870004583A (en) 1987-05-11
KR880002134B1 KR880002134B1 (en) 1988-10-15

Family

ID=19243363

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850007943A KR880002134B1 (en) 1985-10-26 1985-10-26 Adpcm codec circuit using dsp

Country Status (1)

Country Link
KR (1) KR880002134B1 (en)

Also Published As

Publication number Publication date
KR880002134B1 (en) 1988-10-15

Similar Documents

Publication Publication Date Title
KR860009422A (en) Memory circuit
DE3482158D1 (en) Cmi-decoder.
KR900701101A (en) Variable-length encoded data decoding device
KR910002191A (en) Dial signal generator for dial pulse signal and dual tone multi-frequency signal generation
GB2113875B (en) Electronic timepiece
DE3687235D1 (en) DEVICE FOR ENCRYPTION AND UNLOCKING.
KR870004583A (en) ADPCM codec circuit using digital signal processor
JPS5799083A (en) Coding method
KR870005337A (en) Coding System for Speech Synthesizer
JPS55136753A (en) Compressed data recovery system
KR830000959A (en) Long and short signal memory of electronic musical instruments
SE8406242D0 (en) Encryption and decryption device
TW260847B (en) Huffman decoder
KR960009542B1 (en) Viterbi decoder in code division multiple access
SU1621179A1 (en) Device for coding information
KR890009125A (en) Data Compression Device in Communication System
SU1748195A1 (en) Interaction signal read-out device
KR950002251A (en) Variable length code decoding device
FR2247027A2 (en) Coding and decoding of digital information - with enhanced transfer speeds and higher information packing density
KR840001725A (en) Digital Serial Interface with Decode Logic
JPS54122008A (en) Data transmission system
KR890009169A (en) Facsimile recording control device
KR890001282A (en) Digital Dither Additional Circuit
JPS57100535A (en) Data array converter
KR900019490A (en) Word deinterleave circuit of MUSE voice decoder

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020930

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee