KR850002618A - 디지탈 컴퓨터 시스템의 다중 프로세서 시스템용 캐쉬 무효 장치 - Google Patents

디지탈 컴퓨터 시스템의 다중 프로세서 시스템용 캐쉬 무효 장치

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Publication number
KR850002618A
KR850002618A KR1019840005836A KR840005836A KR850002618A KR 850002618 A KR850002618 A KR 850002618A KR 1019840005836 A KR1019840005836 A KR 1019840005836A KR 840005836 A KR840005836 A KR 840005836A KR 850002618 A KR850002618 A KR 850002618A
Authority
KR
South Korea
Prior art keywords
systems
digital computer
cache invalidation
invalidation device
computer systems
Prior art date
Application number
KR1019840005836A
Other languages
English (en)
Other versions
KR910001789B1 (ko
Inventor
봄바 후랭크 씨
피. 반다카 디이립
제이. 그래이디 제이.
에이. 랙키 스탠리
더블유. 밋첼 제프리
슈만 레인하드
Original Assignee
디지탈 이큅먼트 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 디지탈 이큅먼트 코포레이션 filed Critical 디지탈 이큅먼트 코포레이션
Publication of KR850002618A publication Critical patent/KR850002618A/ko
Application granted granted Critical
Publication of KR910001789B1 publication Critical patent/KR910001789B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1019840005836A 1983-09-22 1984-09-22 디지탈 컴퓨터 시스템의 다중 프로세서 시스템용 캐쉬 무효 장치 KR910001789B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/534,783 US4555642A (en) 1983-09-22 1983-09-22 Low power CMOS input buffer circuit
US534,782 1983-09-22

Publications (2)

Publication Number Publication Date
KR850002618A true KR850002618A (ko) 1985-05-15
KR910001789B1 KR910001789B1 (ko) 1991-03-23

Family

ID=24131521

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840005836A KR910001789B1 (ko) 1983-09-22 1984-09-22 디지탈 컴퓨터 시스템의 다중 프로세서 시스템용 캐쉬 무효 장치

Country Status (2)

Country Link
US (1) US4555642A (ko)
KR (1) KR910001789B1 (ko)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60694A (ja) * 1983-06-15 1985-01-05 Hitachi Ltd 半導体メモリ
DE3339253A1 (de) * 1983-10-28 1985-05-09 Siemens AG, 1000 Berlin und 8000 München Cmos-inverter
US4656373A (en) * 1984-11-26 1987-04-07 Rca Corporation High-speed voltage level shift circuit
JP2592234B2 (ja) * 1985-08-16 1997-03-19 富士通株式会社 半導体装置
US4642488A (en) * 1985-09-03 1987-02-10 Codex Corporation CMOS input buffer accepting TTL level inputs
JPS62230220A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 相補性絶縁ゲ−ト型論理回路
US4717845A (en) * 1987-01-02 1988-01-05 Sgs Semiconductor Corporation TTL compatible CMOS input circuit
US4825106A (en) * 1987-04-08 1989-04-25 Ncr Corporation MOS no-leak circuit
US5059835A (en) * 1987-06-04 1991-10-22 Ncr Corporation Cmos circuit with programmable input threshold
KR900001817B1 (ko) * 1987-08-01 1990-03-24 삼성전자 주식회사 저항 수단을 이용한 씨 모스 티티엘 인푸트 버퍼
US4855624A (en) * 1988-02-02 1989-08-08 National Semiconductor Corporation Low-power bipolar-CMOS interface circuit
US4814688A (en) * 1988-03-03 1989-03-21 Brooktree Corporation Reference generator
US4894562A (en) * 1988-10-03 1990-01-16 International Business Machines Corporation Current switch logic circuit with controlled output signal levels
KR910007785B1 (ko) * 1988-12-20 1991-10-02 삼성전자 주식회사 전원공급전압 변동에 대해 안정한 씨모스 입력 버퍼회로
JPH04360312A (ja) * 1991-06-06 1992-12-14 Hitachi Ltd 半導体集積回路装置と信号処理装置
US5402356A (en) * 1992-04-02 1995-03-28 Vlsi Technology, Inc. Buffer circuit design using back track searching of site trees
JPH06209252A (ja) * 1992-09-29 1994-07-26 Siemens Ag Ｃｍｏｓ入力段
US5329184A (en) * 1992-11-05 1994-07-12 National Semiconductor Corporation Method and apparatus for feedback control of I/O characteristics of digital interface circuits
US5596286A (en) * 1993-11-12 1997-01-21 Texas Instruments Incorporated Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit
EP0661812A1 (en) * 1993-12-31 1995-07-05 STMicroelectronics S.r.l. Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level
US5420499A (en) * 1994-03-02 1995-05-30 Deshazo; Thomas R. Current rise and fall time limited voltage follower
US5691654A (en) * 1995-12-14 1997-11-25 Cypress Semiconductor Corp. Voltage level translator circuit
US5666069A (en) * 1995-12-22 1997-09-09 Cypress Semiconductor Corp. Data output stage incorporating an inverting operational amplifier
US5880623A (en) * 1997-02-28 1999-03-09 Exar Corporation Power supply control techniques for FET circuits
US6049242A (en) 1997-10-14 2000-04-11 Cypress Semiconductor Corp. Voltage reference source for an overvoltage-tolerant bus interface
US5914844A (en) * 1997-10-14 1999-06-22 Cypress Semiconductor Corp. Overvoltage-tolerant input-output buffers having a switch configured to isolate a pull up transistor from a voltage supply
GB2335556B (en) 1998-03-18 2002-10-30 Ericsson Telefon Ab L M Switch circuit
JP2000134085A (ja) * 1998-09-16 2000-05-12 Microchip Technol Inc 低電力デジタル入力回路
US6496054B1 (en) 2000-05-13 2002-12-17 Cypress Semiconductor Corp. Control signal generator for an overvoltage-tolerant interface circuit on a low voltage process
US7301370B1 (en) * 2003-05-22 2007-11-27 Cypress Semiconductor Corporation High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
US8018268B1 (en) 2004-11-19 2011-09-13 Cypress Semiconductor Corporation Over-voltage tolerant input circuit
US7512019B2 (en) * 2005-11-02 2009-03-31 Micron Technology, Inc. High speed digital signal input buffer and method using pulsed positive feedback

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
US4475050A (en) * 1981-12-21 1984-10-02 Motorola, Inc. TTL To CMOS input buffer
US4471242A (en) * 1981-12-21 1984-09-11 Motorola, Inc. TTL to CMOS Input buffer
US4469959A (en) * 1982-03-15 1984-09-04 Motorola, Inc. Input buffer

Also Published As

Publication number Publication date
US4555642A (en) 1985-11-26
KR910001789B1 (ko) 1991-03-23

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E902 Notification of reason for refusal
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Payment date: 19980309

Year of fee payment: 8

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