KR850001439B1 - Epitaxial growth for semiconductor materials on a substrate - Google Patents

Epitaxial growth for semiconductor materials on a substrate Download PDF

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KR850001439B1
KR850001439B1 KR1019830005887A KR830005887A KR850001439B1 KR 850001439 B1 KR850001439 B1 KR 850001439B1 KR 1019830005887 A KR1019830005887 A KR 1019830005887A KR 830005887 A KR830005887 A KR 830005887A KR 850001439 B1 KR850001439 B1 KR 850001439B1
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layer
emitter
substrate
epitaxial growth
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KR850005131A (en
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김도식
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삼성반도체통신 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)

Abstract

An n-type Si layer (2) is grown on an n+ type Si substrate (1). The isolation region (12) is scribed. An SiO2 layer (13) is grown on the substrate and all the layer, except for the scribed region, is etched by photo-lithography. A p-type Si layer is formed on the water through epitaxial growth. An SiO2 layer is formed again and a window for emitter diffusion is opened. The ntype impurity is diffused to form an emitter layer (17). Windows (18,19) to allow contact between the emitter and base lead wires are opened. Aluminium is deposited on the windows.

Description

에피택셜 성장기술에 의한 메사트랜지스터의 제작방법Method for manufacturing mesa transistor by epitaxial growth technology

제1(a)도~제1(i)도는 종래의 메사트랜지스터의 제작공정도.1 (a) to 1 (i) are manufacturing process diagrams of a conventional mesa transistor.

제2(a)도~제2(h)도는 본 발명에 따른 메사트랜지스터의 제작공정도.2 (a) to 2 (h) is a manufacturing process of the mesa transistor according to the present invention.

본 발명은 선택 에피택셜 성장기술에 의한 메사트랜지스터의 제작방법에 관한 것으로 특히 소자 영역만 에피택셜 성장을 시켜 베이스층을 형성하고 에미터를 확산시켜 메사 트랜지스터를 제작하는 방법에 관한 것이다.The present invention relates to a method for fabricating a mesa transistor by a selective epitaxial growth technique, and more particularly, to a method for fabricating a mesa transistor by epitaxial growth of only a device region to form a base layer and diffusing an emitter.

제1도 (a)~(i)는 종래의 메사 트랜지스터의 제작공정도로써 제1도의 (a)는 출발재료인 고농도 N형 실리콘 기판 1위에 저농도 P형 불순물을 가지는 실리콘 2를 적층한 기판이다. 제1도(a)의 기판을 확산로에서 P형 불순물을 흘리면서 확산시키면 제1도(b)와 같이 고농도 P형 불순물층 3이 확산되고 그위에 SiO2층 4가 형성된다. 제1도(c)와 같이 제1도 (b)의 SiO2층 4상에 사진식각법으로 에미터를 확산시키기 위한 창 5를 형성시키고 다시 확산로 속에서 N형 불순물을 흘리면서 확산시키면 제1도(d)와 같이 고농도 N형 불순물층 6이 확산되며 그 위에는 SiO2의 층 4이 생기게 된다. 그 다음 제1도(e)와 같이 Si를 에칭하기 위한 창을 사진식각법으로 뚫고 그위에 스크라이브(scribe)를 하여 스크라이브 7부분을 형성시킨다. 스크라이브 부분 7의 Si를 에칭하기 위해서 웨이퍼의 양면에 왁스를 도포시킨 후 사진 식각법으로 에칭할 부분의 왁스를 제거시키면 제1도(f)와 같이 왁스층 8이 형성된다. 제1도(f)의 웨이퍼를 불산과 질산용액을 혼합한 에칭용액에서 웨트 에칭(wet Etching)하면 제1도(g)와 같이 부분 9가 에칭된다. 그 후 왁스를 녹여 제거한 후 확산로 속에서 수증기를 흘리면서 SiO2층 4를 형성시키면 제1도(h)와 같이 된다. 그 다음에 에미터와 베이스 도선을 인출하기 위한 창을 뚫기 위해 사진식각법으로 SiO2를 에칭해내면 제1도(i)와 같이 에미터창 10과 베이스창 11이 형성된다. 이 웨이퍼를 진공증착법에 의해 알루미늄을 증착시킨후 다시 사진식각법으로 베이스와 에미터에 해당하는 도선을 인출해 낸다.1A to 1I are conventional manufacturing process diagrams of mesa transistors, and FIG. 1A is a substrate in which silicon 2 having low concentration P-type impurities is laminated on a high concentration N-type silicon substrate as a starting material. When the substrate of FIG. 1 (a) is diffused while flowing P-type impurities in the diffusion path, as shown in FIG. 1 (b), the high concentration P-type impurity layer 3 is diffused and SiO 2 layer 4 is formed thereon. As shown in FIG. 1 (c), a window 5 for diffusing an emitter by photolithography is formed on the SiO 2 layer 4 of FIG. 1 (b), and again diffused while flowing N-type impurities in the diffusion path. As shown in (d), a high concentration N-type impurity layer 6 is diffused and a layer 4 of SiO 2 is formed thereon. Then, as shown in FIG. 1 (e), a window for etching Si is drilled through photolithography and scribed thereon to form a scribe 7 part. Wax is applied to both sides of the wafer to etch the Si of the scribe portion 7, and then the wax of the portion to be etched is removed by photolithography to form the wax layer 8 as shown in FIG. When the wafer of FIG. 1 (f) is wet etched in an etching solution in which hydrofluoric acid and nitric acid solution are mixed, the portion 9 is etched as shown in FIG. Thereafter, the wax is dissolved and removed to form SiO 2 layer 4 while flowing water vapor in the diffusion furnace, as shown in FIG. 1 (h). Next, when SiO 2 is etched by photolithography to drill the window for drawing the emitter and the base lead, the emitter window 10 and the base window 11 are formed as shown in FIG. The wafer is deposited by vacuum evaporation, and then the conductors corresponding to the base and the emitter are extracted by photolithography.

상기와 같은 종래의 메사트랜지스터 제작방법에 있어서는 스크라이브를 한 후 왁스 도포를 하며 Si를 에칭한 후 왁스를 제거하는 것의 제작공정이 어렵고 고압특성을 갖기 위한 소자제작에서는 장시간의 확산으로 인한 디플레숀층(Depletion layer)의 조정문제와 베이스와 콜렉터와 Si에칭 경계부분 표면을 고압특성에 맞게 완전히 분리시키는데는 현재의 보호피막형성 방법에서도 구조적 어려움이 많은 결점을 가지고 있었다.In the conventional mesatransistor fabrication method as described above, the manufacturing process of removing wax after scribing wax after scribing and etching is difficult, and in manufacturing a device for having high pressure characteristics, a depletion layer due to prolonged diffusion The problem of the adjustment of the layer) and the separation of the surface of the base, collector, and Si-etched boundary parts according to the high-pressure characteristics had a lot of structural difficulties in the current protective film formation method.

본 발명의 목적은 웨트 에칭(wet Etching)에 의한 에칭 공정을 완전히 제거하고 선택 에피택셜 방법에 의한 메사 트랜지스터 제작방법을 제공하는데 있다.An object of the present invention is to completely eliminate the etching process by wet etching and to provide a method for manufacturing a mesa transistor by a selective epitaxial method.

이하 본 발명을 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.

제2도는 본 발명에 따른 메사 트랜지스터의 제작공정도이다.2 is a manufacturing process diagram of the mesa transistor according to the present invention.

제2도 (a)는 고농도 N형 불순물을 가지는 실리콘층 1에 저농도 N형 불순물을 가지는 실리콘층 2를 에피택시한 실리콘 기판상에 소자를 분리해낼 부분을 스크라이브하여 스크라이브 부분 12를 형성시킨 것이다. 그후 제2도(b)와 같이 제2도(a)의 웨이퍼상에 SiO2층 13을 형성시킨다.In FIG. 2 (a), a scribe portion 12 is formed by scribing a portion from which a device is to be separated on a silicon substrate epitaxially having a silicon layer 1 having a high concentration N-type impurity and a silicon layer 2 having a low concentration N-type impurity. Thereafter, as shown in FIG. 2 (b), SiO 2 layer 13 is formed on the wafer of FIG.

제2도 (b)의 SiO2층 13상에 포토 레시스트(Photo Resist)를 도포하고 사진식각법에 의해 P형 불순물을 갖는 실리콘층을 성장시키지 않을 부분 13을 제2도(c)와 같이 남기고 나머지 부분의 SiO2층을 모두 에칭해 내고 제2도(d)와 같이 P형 불순물을 갖는 실리콘층 14를 선택에 미택시를 하여 성장시킨다. 그 후 SiO2층 13을 에칭하고 제2도(e)와 같이 SiO2층 14를 확산로 속에서 전면에 형성시키고 사진 식각법에 의해 에미터를 확산시키기 위해 제2도(f)와 같이 에미터 확산용 창 16을 뚫는다. 확산로 속에서 N형 불순물을 흘리면서 N형 불순물을 확산시켜 제2도(g)와 같이 에미터층 17을 형성시킨후 사진식각법으로 에미터와 베이스 도선을 인출하기 위해 에미터도선 인출용 창 18과 베이스 도선 인출용 창 19를 제2도 (h)와 같이 SiO2를 에칭시켜 창을 형성시킨 후 알루미늄을 진공증착시켜 사진식각법에 의해 에미터와 베이스도선을 형성시키며 콜렉터는 웨이퍼의 후면인 고농도 N형 불순물층 1에 금을 진공증착시켜 N형 불순물층 1을 콜렉터로 한다.A photoresist is applied on the SiO 2 layer 13 in FIG. 2 (b), and a portion 13 in which the silicon layer having P-type impurities is not grown by photolithography is shown in FIG. The remaining SiO 2 layer is etched away, and the silicon layer 14 having the P-type impurity is grown by untaxing as shown in FIG. Then etching SiO 2 layer 13 and forming SiO 2 layer 14 on the front surface in the diffusion furnace as shown in FIG. 2 (e) and emi as in FIG. 2 (f) to diffuse the emitter by photolithography. Drill through the spreading window 16. N-type impurities are diffused through the diffusion path to form N-type impurities to form emitter layer 17 as shown in FIG. 2 (g). The window 19 for drawing the lead-out and the base lead is formed by etching SiO 2 as shown in FIG. 2 (h), and aluminum is vacuum-deposited to form the emitter and the base lead by photolithography. Gold is vacuum-deposited on the high concentration N-type impurity layer 1 to form N-type impurity layer 1 as a collector.

상기와 같이 본 발명은 종래의 메사 트랜지스터 제작방법인 웨트 에칭방법을 제거하고 선택에피택셜 방법에 의해 제작하므로서 에미터 형성시에만 불순물을 확산시키는 공정이 있게되어 종래와 같이 베이스 확산공정이 필요없게 되며 베이스층의 불순물 농도가 균일한 불순물 분포를 얻을수 있음으로서 소자의 특성을 향상시키고 디플레숀층(Depletion layer)의 조정도 용이하며 베이스, 콜렉터의 경계부분 표면을 완전히 분리시킬 수 있어 고압에서 동작하는 트랜지스터의 동작특성도 양호하며 메사 트랜지스터의 수율도 향상되는 이점이 있게 된다.As described above, the present invention removes the wet etching method, which is a conventional method for manufacturing a mesa transistor, and is manufactured by a selective epitaxial method so that impurities are diffused only at the time of emitter formation, thereby eliminating the need for a base diffusion process as in the prior art. Impurity distribution of the base layer can be obtained with uniform impurity distribution, which improves the device characteristics, facilitates the adjustment of the deflation layer, and completely separates the boundary surface of the base and the collector. The operating characteristics are also good and the mesa transistor yields an advantage.

Claims (1)

메사 트랜지스터의 제작방법에 있어서, 소자형성 부분만 선택 에피택셜 성장을 시켜 베이스층(14)으로 하고 에미터(17)를 확산시켜 웨트 에칭방법을 제거함을 특징으로 하는 에피택셜 성장 기술에 의한 메사트랜지스터의 제작방법.In the method for manufacturing a mesa transistor, the mesa transistor by epitaxial growth technique is characterized in that only the element formation portion is subjected to selective epitaxial growth to form the base layer 14 and the emitter 17 is diffused to remove the wet etching method. How to make.
KR1019830005887A 1983-12-08 1983-12-08 Epitaxial growth for semiconductor materials on a substrate KR850001439B1 (en)

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KR850001439B1 true KR850001439B1 (en) 1985-10-02

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