KR840005865A - Interactive Data Processing System - Google Patents

Abstract

No content

Description

Interactive Data Processing System

As this is a public information case, the full text was not included.

1 is a block diagram of an interactive terminal data processing system.

2 is a block diagram of a high speed connection controller (HSLC).

3A is a diagram showing information transmitted between HSLC and work benches.

3B is a waveform diagram of signals transmitted between the HSLC and the work benches.

FIG. 3C is a waveform diagram of the signals of FIG. 3B received by HSLC and converted into RCVGATE signals.

Claims (14)

A single conducting coaxial bus having a predetermined length, a plurality of work benches, each of which is commonly connected to the bus, for transmitting information at a predetermined bit rate to one of the plurality of work benches, and one of the plurality of work benches. And a high speed connection controller coupled to the bus for receiving information at a predetermined bit rate from the system. 2. The apparatus of claim 1, wherein the high speed connection controller comprises: a storage device for storing information in the form of respective characters represented by a first plurality of parallel data bits, and receiving the first plurality of parallel data bits from the storage device. And a communication controller responsive to the parallel data bits for converting the first plurality of parallel data bits from the microprocessor to the first plurality of serial data bits. Processing system. 3. The high speed link controller of claim 2, further coupled to the communication controller, responsive to a first plurality of serial data bits, and generating a plurality of first and second signals that are indicative of a first plurality of serial data bits. An interactive data processing system comprising means for. 4. The high speed connection controller of claim 3, wherein the high speed connection controller has an analog circuit device, the analog circuit is responsive to a plurality of first and second signals, has a predetermined rise and fall time, and is adapted to transmit to the bus to a plurality of work stations. 1 An interactive data processing system having a device for generating a third signal, which is a representation of a plurality of serial data bits. 5. The high speed connection controller of claim 4, wherein the high speed connection controller has an analog circuit device, the analog circuit device responds to a plurality of third signals received from a plurality of workstations and is a second plurality of serial data bit representations. And an apparatus for generating a fifth signal. 6. The apparatus of claim 5, wherein the high speed connection controller has a data recovery device that responds to a plurality of fourth and fifth signals and generates a plurality of sixth signals that are the second plurality of serial data bit representations. Interactive data processing system, characterized in that it has a device for. 7. The interaction of claim 6, wherein the high speed connection controller comprises a communication controller responsive to a plurality of sixth signals for generating a second plurality of parallel data bits for transmission to a microprocessor for storage in memory. Expression Data Processing System. The interactive data processing system of claim 1, wherein the predetermined length is 1 kilometer. 2. The interactive data processing system of claim 1, wherein the predetermined bit rate is 750,000 bits per second. 5. The interactive data processing system of claim 4, wherein the predetermined rise and fall time is 200 nanoseconds. An interactive data processing system for transferring an information block between a central processing unit and a plurality of work benches at a predetermined bit rate, wherein the central processing unit stores memory for storing a first plurality of characters that are an indication of the information block. A read-only storage device for storing the first plurality of microwords, which is an indication of the first plurality of microprograms, and a micro responding to the first plurality of microwords for receiving the first plurality of characters from the storage device. A processor, a communication controller coupled to the microprocessor for receiving a first plurality of characters and generating a first plurality of serial data signals, a communication controller coupled to the communication controller, and generating a first plurality of first and second signals. A data return device responsive to the first plurality of data signals, and a first plurality of third signals having a predetermined rise and fall time to generate a first A central processing unit comprising an analog device coupled to a data recovery device to receive a number of first and second signals, and a single wire coaxial bus having a predetermined length and connected to the analog device, wherein the workbenches are configured to include a first plurality of signals. A device coupled to the bus in common to receive a first plurality of third signals representing a character, the device including a second plurality of third signals, wherein the data recovery device comprises a second plurality of serial data signals. In response to a second plurality of first and second signals to generate a second, the communication controller is configured to receive a second plurality of serial data signals and to generate a second plurality of characters, wherein the microprocessor And respond to the second plurality of micro words to receive the second plurality of characters for storage. 12. The interactive data processing system of claim 11, wherein the predetermined rise and fall time is 200 nanoseconds. 12. The interactive data processing system of claim 11, wherein the predetermined length is one kilometer. 12. The interactive data processing system of claim 11, wherein the predetermined bit rate is 750,000 bits per second. ※ Note: The disclosure is based on the initial application.