KR20250108625A - 반도체 장치 및 그 제작 방법 - Google Patents

반도체 장치 및 그 제작 방법

Info

Publication number
KR20250108625A
KR20250108625A KR1020257015674A KR20257015674A KR20250108625A KR 20250108625 A KR20250108625 A KR 20250108625A KR 1020257015674 A KR1020257015674 A KR 1020257015674A KR 20257015674 A KR20257015674 A KR 20257015674A KR 20250108625 A KR20250108625 A KR 20250108625A
Authority
KR
South Korea
Prior art keywords
layer
insulating layer
semiconductor
opening
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020257015674A
Other languages
English (en)
Korean (ko)
Inventor
준이치 고에즈카
마사미 진쵸우
유키노리 시마
겐스케 요시즈미
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20250108625A publication Critical patent/KR20250108625A/ko
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0318—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] of vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Landscapes

  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020257015674A 2022-11-04 2023-10-27 반도체 장치 및 그 제작 방법 Pending KR20250108625A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JPJP-P-2022-176862 2022-11-04
JP2022176862 2022-11-04
PCT/IB2023/060839 WO2024095113A1 (ja) 2022-11-04 2023-10-27 半導体装置、及びその作製方法

Publications (1)

Publication Number Publication Date
KR20250108625A true KR20250108625A (ko) 2025-07-15

Family

ID=90929889

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020257015674A Pending KR20250108625A (ko) 2022-11-04 2023-10-27 반도체 장치 및 그 제작 방법

Country Status (7)

Country Link
US (1) US20260020285A1 (https=)
JP (1) JPWO2024095113A1 (https=)
KR (1) KR20250108625A (https=)
CN (1) CN120092498A (https=)
DE (1) DE112023004639T5 (https=)
TW (1) TW202425355A (https=)
WO (1) WO2024095113A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12342681B2 (en) * 2023-09-15 2025-06-24 Industrial Technology Research Institute All-oxide transistor structure, method for fabricating the same and display panel comprising the structure
WO2025243161A1 (ja) * 2024-05-23 2025-11-27 株式会社半導体エネルギー研究所 半導体装置
WO2026033402A1 (ja) * 2024-08-09 2026-02-12 株式会社半導体エネルギー研究所 表示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012257187A (ja) 2010-08-06 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体集積回路
JP2013211537A (ja) 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
WO2021053473A1 (ja) 2019-09-20 2021-03-25 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2871347B2 (ja) * 1992-10-08 1999-03-17 日本電気株式会社 半導体装置及びその製造方法
JP2017168760A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
US10593693B2 (en) * 2017-06-16 2020-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012257187A (ja) 2010-08-06 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体集積回路
JP2013211537A (ja) 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
WO2021053473A1 (ja) 2019-09-20 2021-03-25 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
M. Oota et. al, "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm", IEDM Tech. Dig., 2019, pp. 50-53

Also Published As

Publication number Publication date
US20260020285A1 (en) 2026-01-15
DE112023004639T5 (de) 2025-10-02
WO2024095113A1 (ja) 2024-05-10
JPWO2024095113A1 (https=) 2024-05-10
CN120092498A (zh) 2025-06-03
TW202425355A (zh) 2024-06-16

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