KR20240037965A - 다이-기판 스탠드오프 공동 내의 다이-투-다이(d2d) 연결들을 채용하는 분할형 다이 집적 회로(ic) 패키지들, 및 관련 제조 방법들 - Google Patents

다이-기판 스탠드오프 공동 내의 다이-투-다이(d2d) 연결들을 채용하는 분할형 다이 집적 회로(ic) 패키지들, 및 관련 제조 방법들 Download PDF

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KR20240037965A
KR20240037965A KR1020247002305A KR20247002305A KR20240037965A KR 20240037965 A KR20240037965 A KR 20240037965A KR 1020247002305 A KR1020247002305 A KR 1020247002305A KR 20247002305 A KR20247002305 A KR 20247002305A KR 20240037965 A KR20240037965 A KR 20240037965A
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die
interconnects
package
package substrate
cavity
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Korean (ko)
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아니켓 파틸
브리검 나바자
홍복 위
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퀄컴 인코포레이티드
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H01L21/568—
    • H01L21/6835—
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/616—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips
    • H10W70/618—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
KR1020247002305A 2021-07-27 2022-06-17 다이-기판 스탠드오프 공동 내의 다이-투-다이(d2d) 연결들을 채용하는 분할형 다이 집적 회로(ic) 패키지들, 및 관련 제조 방법들 Pending KR20240037965A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/443,740 2021-07-27
US17/443,740 US20230035627A1 (en) 2021-07-27 2021-07-27 Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods
PCT/US2022/073006 WO2023009919A1 (en) 2021-07-27 2022-06-17 Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods

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KR20240037965A true KR20240037965A (ko) 2024-03-22

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KR1020247002305A Pending KR20240037965A (ko) 2021-07-27 2022-06-17 다이-기판 스탠드오프 공동 내의 다이-투-다이(d2d) 연결들을 채용하는 분할형 다이 집적 회로(ic) 패키지들, 및 관련 제조 방법들

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US (1) US20230035627A1 (https=)
EP (1) EP4377999A1 (https=)
JP (1) JP2024528794A (https=)
KR (1) KR20240037965A (https=)
CN (1) CN117751449A (https=)
TW (1) TW202306094A (https=)
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