KR20230149784A - Narrow bezel display device - Google Patents

Abstract

By creating a paired upper dam, lower dam, and trench at a specific location in the non-display area, the bezel width is reduced to a certain level or less, while at the same time controlling the spread of the sealant and the orientation material to overlap the sealant and the orientation material. minimize. Additionally, the contact area between the sealant and the underlying substrate is expanded by the trench formed at the bottom of the seal-region. As a result, it is possible to provide a display device in which adhesion between the upper substrate and the lower substrate is improved.

Description

Narrow bezel display device {NARROW BEZEL DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, a sealant that joins the upper and lower substrates on the outside to reduce the bezel width by overlapping the signal wiring area or gate driver area. It concerns display devices.

A liquid crystal display device includes an upper substrate, a lower substrate, and a liquid crystal layer formed between the upper substrate and the lower substrate. An image is displayed by light passing through a liquid crystal layer whose orientation is controlled by an electric field applied to the liquid crystal display device. In other words, a liquid crystal display device is a device that displays images by adjusting light transmittance by the orientation of the liquid crystal layer. A sealant is applied to the non-display area (or bezel area) corresponding to the outer periphery of the display area of the display device so that a liquid crystal layer can be provided between the upper substrate and the lower substrate, and the upper substrate is sealed from the outer portion. Cement the and lower substrates.

Recently, from a design perspective, display devices with reduced bezel width have been in the spotlight. Accordingly, in order to reduce the bezel width in display devices, the industry continues to make efforts to reduce the area of the seal region, the area where sealant is applied to bond the upper and lower substrates of the display device. there is. However, since the area of the seal region is proportional to the adhesive force between the upper and lower substrates, there is a limit to reducing the area of the seal region. Since the seal-area must be designed to avoid areas made of materials with poor adhesion to the sealant or areas that are prone to damage by external forces, it is difficult to reduce the bezel by overlapping the circuit areas of the seal-area and the non-display area. There are limits.

Additionally, since the sealant may spread or overflow as it is applied to the upper or lower substrate in a fluid liquid state, there is a limit to reducing the area of the seal-region.

Additionally, when the sealant is made of a photocurable material, high-energy light such as UV must be irradiated from the outside of the lower substrate toward the seal-area to cure the sealant. At this time, if the sealant is applied or spread to the part of the circuit area where metal wiring is arranged at a high density, the sealant may not harden because the light cannot reach the sealant due to the metal wiring that reflects light. .

In addition, the alignment material for aligning the liquid crystal layer may also spread or overflow as it is applied in a fluid liquid state to the upper or lower substrate. If the applied orientation material spreads and invades the seal area, the sealant and orientation material may overlap unintentionally. Since the adhesion between the sealant and the alignment material is poor, the larger the overlapping area between the sealant and the alignment material, the lower the adhesion between the upper substrate and the lower substrate. Therefore, in order to prevent the applied orientation material from spreading and invading the seal area, a predetermined gap (or margin) is required between the seal area and the area to which the orientation material is applied. The predetermined gap between the seal-area and the area where the orientation material is applied causes the bezel width to increase.

The present invention was designed to solve the above-mentioned conventional problems, and the narrow bezel display device according to an embodiment of the present invention improves the adhesion between the upper substrate and the lower substrate by overlapping the seal-region and the circuit region. The purpose is to provide a display device that can reduce the bezel width to a certain level or at the same time.

In addition, the narrow bezel display device according to an embodiment of the present invention configures a bumper that can minimize damage to the circuit area that may occur in the area where the seal-area and the circuit area overlap, thereby preventing damage to the circuit area. The purpose is to provide a display device in which the occurrence of electrostatic or corrosion of metal wiring is reduced.

In addition, the narrow bezel display device according to an embodiment of the present invention reduces the bezel width to a certain level or less while simultaneously controlling the spread of the sealant and the spread of the orientation material, so that the overlap between the sealant and the orientation material is minimized. The purpose is to provide a device.

In addition, the narrow bezel display device according to an embodiment of the present invention expands the contact area between the sealant and the lower substrate by a trench formed in the lower part of the seal-region or the lower part near the seal-region, thereby increasing the contact area between the sealant and the lower substrate. The purpose is to provide a display device in which adhesion between a substrate and a lower substrate is improved.

In addition, in reducing the bezel width of the display device, avoiding design of the seal-area and specific circuit area and preventing defective adhesion of the upper and lower substrates and damage to the circuit under the sealant without adding a separate independent process or mask. The purpose is to provide a display device with a high degree of design/process freedom by providing a structure that can reduce the occurrence of metal corrosion/corrosion.

In order to achieve the above-described object, the present invention includes an upper substrate and a lower substrate arranged to face each other with liquid crystal interposed, the upper substrate is provided with a plurality of upper spacers, and the lower substrate is provided with a plurality of lower spacers. A gate link unit and a gate driver on which a plurality of external signal wires are arranged are provided on the outer part of the substrate. The plurality of external signal wires and the gate driver are electrically connected by a plurality of bridge regions. In order to reduce the bezel, a sealant is formed in the seal-area to overlap a portion of the area where the gate link portion and the gate driver are disposed, and the upper substrate and the lower substrate are bonded. Each of the plurality of bridge regions has a first contact hole where the first metal layer is exposed and an upper part of a second contact hole where the second metal layer is exposed, and the first metal layer and the second contact hole are connected through the first contact hole and the second contact hole. A bridge electrode connecting the two metal layers is provided. The plurality of lower spacers formed on the lower substrate include a lower spacer disposed at a position corresponding to the upper spacer and a lower spacer disposed to overlap at least one bridge region among the plurality of bridge regions.

In addition, by creating a paired upper dam, lower dam, and trench at a specific location in the non-display area, the bezel width is reduced to a certain level or less, while at the same time controlling the spread of the sealant and the orientation material to control the spread of the sealant and the orientation material. Minimize overlap. Additionally, the contact area between the sealant and the underlying substrate is expanded by the trench formed at the bottom of the seal-region.

A display device divided into a display area for displaying an image and a non-display area around the display area according to an embodiment of the present invention, comprising: a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween; a sealant disposed in a non-display area between the first and second substrates so that the first and second substrates are bonded to each other; an upper alignment film and a lower alignment film disposed facing each other in the display area between the first and second substrates, which are positions that determine the initial alignment direction of the liquid crystal of the liquid crystal layer; A gate link unit, gate driver, and touch wiring area arranged in a non-display area; an overlap prevention area including a lower dam rising from the first substrate toward the second substrate and an upper dam extending from the second substrate toward the first substrate; and a trench region including a plurality of trenches through which the sealant flows. At this time, the overlap prevention area and the trench area are disposed adjacent to the boundary of the touch wiring area and the gate driver and overlap each other.

In another aspect, a display device divided into a display area for displaying an image and a non-display area around the display area according to an embodiment of the present invention, comprising: a first substrate; UV curing slant placed around the outside of the display device; an alignment film surrounded by a UV cured sealant; It is characterized in that it includes a first structure disposed at a position to prevent overlap of the UV curing sealant and the alignment layer in the non-display area to minimize the bezel width of the display device.

According to an embodiment of the present invention, it is possible to provide a display device that can improve the adhesion between the upper substrate and the lower substrate and reduce the bezel width below a certain level by overlapping the seal-region and the circuit region.

In addition, according to an embodiment of the present invention, by constructing a bumper that can minimize damage to the circuit area that may occur in the area where the seal area and the circuit area overlap, electrolysis or corrosion of the metal wiring due to damage to the circuit area is prevented. It is possible to provide a display device in which the occurrence of is reduced.

In addition, according to an embodiment of the present invention, it is possible to provide a display device in which the overlap between the sealant and the alignment material is minimized by reducing the bezel width to a certain level or less and controlling the spread of the sealant and the alignment material at the same time. .

In addition, according to an embodiment of the present invention, the contact area between the sealant and the lower substrate is expanded by the trench formed in the lower part of the seal area or the lower part near the seal area, thereby improving the adhesion between the upper substrate and the lower substrate. A display device may be provided.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

Since the content of the invention described in the problem to be solved, the means for solving the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

1 is a schematic plan view of a display device according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
3A to 3D are schematic plan views and cross-sectional views for explaining an upper spacer and a lower spacer of a display device according to an embodiment of the present invention.
FIG. 4A is an enlarged plan view of a portion of a non-display area of a display device according to an embodiment of the present invention.
FIG. 4B is a cross-sectional view of the corresponding area along the line extending from A to A' shown in FIG. 4A.
FIG. 4C is a cross-sectional view of an enlarged portion of a non-display area of a display device according to an embodiment of the present invention, showing another embodiment, corresponding to FIG. 4B.
Figure 5 is a diagram schematically showing a non-display area of a display panel according to an embodiment of the present invention.
Figure 6 is a diagram schematically showing a non-display area of a display panel according to an embodiment of the present invention.
Figures 7a to 7h are plan views corresponding to the overlap prevention area shown in Figure 5.
Figures 8a to 8d are plan views corresponding to the overlap prevention area and trench area shown in Figure 5.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the various embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the various embodiments disclosed below and will be implemented in various different forms. The present various embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Each of the features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, and various technical interconnections and operations are possible, and each of the various embodiments may be implemented independently of each other or may be implemented together in a related relationship. It may be possible.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of a display area of a display panel according to an embodiment of the present invention.

Referring to FIGS. 1 and 2 , the display device 10 includes a display panel 100 provided with a plurality of pixels P that output light. The area provided with the plurality of pixels (P) is divided into a display area (DA), and the outer periphery of the display area (DA) is divided into a non-display area (NDA). When the display panel 100 is implemented as a liquid crystal panel, the first substrate 110 and the second substrate 115 face each other and are spaced apart from each other at a predetermined distance. A liquid crystal layer LC filled with liquid crystal is formed between the spaced apart first substrate 110 and the second substrate 115, corresponding to the display area DA. At this time, the first substrate 110 may be a TFT array substrate on which a plurality of thin film transistors (TFTs) are formed, and the second substrate 115 may be a color filter layer (color filter layer) corresponding to a plurality of pixels (P). CF) may be a color filter substrate formed. Alternatively, the second substrate 115 may be a TFT array substrate on which a plurality of thin film transistors (TFTs) are formed, and the first substrate 110 may be a color filter layer (CF) corresponding to a plurality of pixels (P). ) may be a color filter substrate on which a color filter substrate is formed. Alternatively, the color filter layer CF and the TFT array may be formed together on one of the first substrate 110 and the second substrate 115. At least one of the first substrate 110 and the second substrate 115 is provided with a common electrode 140 and a pixel electrode 150. The orientation of the liquid crystal between the first substrate 110 and the second substrate 115 is controlled by a vertical or horizontal electric field formed by the difference in voltage applied to the common electrode 140 and the pixel electrode 150, respectively. .

Additionally, the display device 10 is a light source of the liquid crystal panel and includes a backlight unit disposed below the liquid crystal panel. Additionally, the display device 10 includes various driving circuits for driving the liquid crystal panel. The driving circuit part may be implemented on a printed circuit board (PCB). The driving circuit part is connected to the gate pad part (G_Pad) and the data pad part (D_Pad) formed on one side of the outer side of the liquid crystal panel. The driving circuit unit drives the gate driver and data driver of the liquid crystal panel.

Referring to Figures 1 and 2, the first substrate 110 is divided into a display area (DA) and a non-display area (NDA) surrounding it. In the display area (DA), a plurality of gate lines (GL) and data lines (DL) are arranged to intersect each other, and each pixel (P) area is defined by the intersection of the gate lines (GL) and data lines (DL). A thin film transistor 130 is provided. For example, in the display panel 100, M*N pixels (P) may be provided by crossing N gate lines (GL) and M data lines (DL). In some embodiments of the display panel 100, the display panel 100 may be designed in a structure in which adjacent pixels P share a gate line GL or a data line DL. Accordingly, the display panel 100 may be provided with more pixels (P) than M×N. The thin film transistor 130 provided in each pixel (P) area is connected to the gate line (GL) and the data line (DL), and switches according to the gate signal applied to the gate line (GL), and the data line (DL) The data signal applied from is supplied to the pixel electrode 150. The pixel electrode 150 is connected to the thin film transistor 130 to form an electric field according to the data signal supplied from the thin film transistor 130, and the liquid crystal orientation of the liquid crystal layer LC is adjusted by the formed electric field.

FIG. 2 shows three pixels P arranged in the display area DA of the display panel 100 for convenience of explanation. The thin film transistor 130 formed in each pixel (P) includes a gate electrode 131, an active layer 132, a first electrode 133, and a second electrode 134 formed on the first substrate 110. do. More specifically, a gate electrode 131 electrically connected to the gate line GL is formed on the first substrate 110, and a gate insulating layer 121 is formed on the gate electrode 131. An active layer 132 in which a channel is formed is formed on the gate insulating layer 121, and a first electrode 134 and a pixel electrode 150 electrically connected to the data line DL are formed on the active layer 132. An electrically connected second electrode 133 is formed. The active layer 132 may be formed of amorphous silicon, polycrystalline silicon, oxide semiconductor, etc.

A planarization layer 122 is formed to cover the thin film transistor 130 on the first substrate 110. The planarization layer 122 forms a flat surface on the thin film transistor 130. The planarization layer 122 may be formed of an organic insulating material such as photo-acryl (PAC). A separate passivation layer (PAS) may be formed between the thin film transistor 130 and the planarization layer 122. For example, the passivation layer (PAS) provided between the thin film transistor 130 and the planarization layer 122 may be formed of a silicon-based inorganic insulating material.

A common electrode 140 is formed on the planarization layer 122. The common electrode 140 drives the liquid crystal by forming an electric field between it and the pixel electrode 150. Since FIG. 2 shows a portion where the pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through a contact hole, it is as if the common electrode 140 is connected to each pixel (P). They are shown as if separated. However, the common electrode 140 is the common electrode of each pixel (P) in parts other than the part where the pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through the contact hole. (140) may be electrically connected to each other along the common electrode line through a separate contact hole.

Additionally, each pixel P may be provided with a separate common electrode 140, but a plurality of pixels P adjacent to each other may share one common electrode block. As a result, the display panel 100 that detects touch can be implemented by time-dividing one frame period of the screen and applying a signal for detecting a touch input to a common electrode line in one section. An individual common electrode line extends from each common electrode block, and each common electrode line may be arranged so that at least a portion of the common electrode line overlaps the gate line GL or the data line DL. The common electrode line may be disposed on the thin film transistor 130, between the thin film transistor 130 and the common electrode block. Alternatively, the common electrode line may be disposed below the thin film transistor 130. or,

When the common electrode line is disposed below the thin film transistor 130, a highly heat-resistant planarization layer, different from the planarization layer 122 formed on the thin film transistor 130, is formed between the common electrode line and the thin film transistor 130. It can be provided. For example, a plurality of common electrode lines are formed on the first substrate 110, a silicon-based, high heat-resistant planarization layer (Silicon on Glass (SOG)) is formed on the common electrode line, and a high heat-resistant planarization layer is formed on the high heat-resistant planarization layer. A thin film transistor 130 may be formed.

The common electrode line may extend from the non-display area (NDA) along the boundary between the display area (DA) and the non-display area (NDA) and be connected to the touch driver by the touch wiring, which will be described later.

An insulating layer 123 is formed between the common electrode 140 and the pixel electrode 150 to insulate the two electrodes. The insulating layer 123 protects the common electrode 140 and forms a flat surface on top of the common electrode 140. The insulating layer 123 may be formed of the same material as the planarization layer 122 or may be formed of the same material as the passivation layer (PAS). That is, the insulating layer 123 may be a planarization layer 122 or a passivation layer (PAS). Alternatively, the insulating layer 123 may be formed of an insulating material different from the passivation layer and the planarization layer 122.

The pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through a contact hole formed in the planarization layer 122 and the insulating layer 123. The pixel electrode 150 and the common electrode 140 may be formed of a transparent conductive material, such as indium tin oxide (ITO), and the pixel electrode 150 and the common electrode 140 form a horizontal electric field. A plurality of slits may be formed to do so. However, this is only an example, and the structure and arrangement relationship between the common electrode 140 and the pixel electrode 150 are not limited to this. Accordingly, in some embodiments, the common electrode 140 may be disposed on top of the pixel electrode 150, or the pixel electrode 150 and the common electrode 140 may be disposed on the same layer. Additionally, in some embodiments, the common electrode 140 may be formed to have a plurality of slits instead of the pixel electrode 150.

Referring to FIG. 2, the second substrate 115 disposed opposite the first substrate 110 is a color filter substrate of the display panel 100. The second substrate 115 is provided with a black matrix (BM) and a color filter layer (CF) that partition light-shielding areas and opening areas into the plurality of pixels (P), respectively. The area where the black matrix (BM) is formed is defined as a light blocking area, and the area where the black matrix (BM) is not formed is defined as an opening area. Various driving elements and wiring, such as a thin film transistor 130, a data line (DL), and a gate line (GL), are formed in the light blocking area by the black matrix (BM). A pixel electrode 150 and a common electrode 140 are formed in the opening area. Since FIG. 2 shows a cross section cut along the gate line GL of the display panel 100, the black matrix BM is continuously extended. That is, Figure 2 shows a cross-sectional view in the light-shielding area. However, the black matrix (BM) is not formed in the opening area. As the black matrix BM is disposed between two adjacent pixels P, it is arranged to block structures that may reflect external light, such as the lower data line DL and the thin film transistor 130.

A plurality of color filters CF1, CF2, and CF3 are formed on the second substrate 115 to correspond to each pixel P of the display panel 100. That is, the color filter layer CF includes color filters CF1, CF2, and CF3. Specifically, color filters CF1, CF2, and CF3 are formed to correspond to the opening areas of each of the red pixel (R), green pixel (G), and blue pixel (B). Some areas of each color filter (CF1, CF2, CF3) may overlap with the black matrix (BM). In the embodiment shown in FIG. 2, the black matrix BM is disposed closer to the second substrate 115 than the color filter layer CF. However, in some other embodiments, in order to reduce light leakage between adjacent pixels P, the color filter layer CF is disposed closer to the second substrate 115 than the black matrix BM, and the black matrix (BM) may be disposed on the surface of the first substrate 110.

An over coating layer (OC) is formed on the second substrate 115 to cover the black matrix (BM) and the color filter layer (CF). The overcoating layer (OC) is a layer to provide a flat surface to the second substrate 115 by covering the black matrix (BM) and the color filter layer (CF). Additionally, the overcoating layer (OC) prevents contamination of the liquid crystal by various pigments of the color filter layer (CF). For example, the overcoating layer (OC) may be composed of acrylic resin or epoxy resin. Alternatively, the overcoating layer OC may be made of the same material as the planarization layer 122.

The non-display area (NDA) of the first substrate 110 is provided with a pad portion (PAD), a data link portion (D_Link), a gate link portion (G_Link), and a gate driver (GIP). The pad portion (PAD) includes a data pad portion (D_Pad) and a gate pad portion (G_Pad). The gate pad portion (G_Pad) is formed on one side of the data pad portion (D_Pad) and is connected to an external driving circuit portion. The data pad portion D_Pad may be formed on one side of the non-display area NDA of the first substrate 110 and connected to an external driving circuit. Additionally, a data driver with an integrated circuit (IC) structure may be directly connected to the first substrate 110 in the data pad portion (D_Pad) using a chip-on-glass (COG) method.

In addition to the data pad part (D_Pad) and gate pad part (G_Pad) described above, the pad part (PAD) includes input and output of signals necessary to drive the pixel (P) of the display panel 100 or implement various other additional functions. Pads may be provided for. For example, the pad portion (PAD) may include a common voltage pad connected to the common voltage generator of the driving circuit portion. Alternatively, the pad portion (PAD) may be configured with a touch sensor pad connected to a touch driver for performing the touch recognition function of the display panel. The location of each pad portion (PAD) is not limited to one side of the non-display area (NDA), but may be located on at least one side of the top, bottom, left, and right side of the non-display area (NDA).

The data link unit (D_Link) may include a data link wire (D_LL) that is disposed between the data line (DL) and the data pad unit (D_Pad) disposed in the display area (DA) and electrically connect them to each other. The gate link unit (G_Link) may be configured with an external signal wire through which various external signals are supplied to drive the gate driver (GIP). For example, as shown in FIG. 1, a gate start signal line (VST), a plurality of clock signal lines (CLK1-4), a reset signal line (RESET), and voltage lines (VSS, VDD, VDD1) are connected to the gate. It can be configured in the link unit (G_Link). Each external signal wire of the gate link unit (G_Link) electrically connected to the gate pad unit (G_Pad) is connected to the gate driver through the connection wire (CL).

The gate driver may be formed by the thin film transistor 130 formed in the non-display area NDA of the first substrate 110 during the process of forming the thin film transistor 130 in the display area DA. The gate driver disposed on one substrate of the JUG display panel may be configured in a gate-in-panel (GIP) method. The gate driver generates a gate signal and sequentially supplies it to the gate lines (GL) arranged in the display area (DA). To this end, the gate driver includes a plurality of stages ST connected to each gate line GL. Accordingly, each external signal wire of the gate link unit (G_Link) is selectively connected to each stage (ST) of the gate driver (GIP) through the connection wire (CL).

Each of the plurality of stages (ST) responds to the gate start signal wire (VST) or the gate start signal supplied from the previous stage, and clocks supplied from one of the plurality of clock signal wires (CLK1, CLK2, CLK3, CLK4). The signal is applied as a gate signal. And each of the plurality of stages (ST) supplies the received gate signal to the gate line (GL). Each of these multiple stages (ST) operates sequentially according to the gate start signal line (VST) or the gate start signal supplied from the previous stage, thereby sequentially transmitting the gate signal from the first gate line (GL) to the last gate line (GL). or supplied sequentially from the last gate line (GL) to the first gate line (GL).

A sealant is applied to the edge of the first substrate 100 or the edge of the second substrate 115 along the non-display area NDA. The first substrate 110 and the second substrate 115 are bonded opposite each other in the display area DA with the liquid crystal layer LC interposed therebetween. Since the seal-area where the sealant is applied and the non-display area (NDA) of the first substrate 110 are not areas where images are displayed, they are obscured by the black matrix (BM) or the housing of the display device. do. At this time, the non-display area (NDA) obscured by the black matrix (BM) or housing is also called a bezel. To reduce the width of the bezel, the seal-area where the sealant is applied may overlap the circuit area in the non-display area (NDA). That is, the seal-area may overlap with a portion of the gate link portion (G_Link), may overlap with an area where the extension wiring (CL) is disposed, or may also overlap with an area where the gate driver is formed.

In order to maintain a constant gap between the first substrate 110 and the second substrate 115 bonded by the sealant provided in the seal area, there is a gap between the first substrate 110 and the second substrate 115. A spacer is provided. The spacer may be formed on one side of the first substrate 110 or on one side of the second substrate 115. When the display panel receives an external force, the alignment of the first substrate 110 and the second substrate 115 becomes misaligned. At this time, if the spacer is formed on one side of the first substrate 110, the spacer may damage the alignment film provided on one side of the second substrate 115. Accordingly, unintended distortion of the liquid crystal orientation occurs, and light leakage occurs due to the distortion of the liquid crystal orientation. The leaking light is recognized as reddish, greenish, or bluish light depending on the position of the spacer when the display panel displays a black image to the user. In other words, light leakage defects in black images result from damage to the alignment film caused by the spacer. In order to reduce light leakage defects due to damage to the alignment layer due to the above-mentioned spacer, the area of the black matrix BM that covers the spacer may be designed to be larger. However, considering the high resolution and high aperture ratio of the display panel, solving light leakage defects by expanding the area of the black matrix (BM) should be avoided. Accordingly, in the display panel 100 according to an embodiment of the present invention, a spacer is formed on one side of the first substrate, and a spacer is formed on one side of the second substrate to face the spacer correspondingly.

Referring to FIG. 2 , a plurality of upper spacers U_SP are disposed between the first substrate 110 and the second substrate 115 on the overcoating layer OC of the second substrate 115 . The upper spacer (U_SP) is disposed in the light blocking area where the black matrix (BM) is disposed. Between the first substrate 110 and the second substrate 115, a plurality of lower spacers L_SP are disposed on the planarization layer 122 and the insulating layer 123 of the first substrate 110. The lower spacer (L_SP) and the upper spacer (U_SP) are disposed to face each other.

The height of some of the plurality of spacers (U_SP, L_SP) provided on each of the first substrate 110 and the second substrate 115 may be longer or shorter than the height of the other spacers (U_SP, L_SP). That is, the length of each of the plurality of upper spacers (U_SP) may not be uniform. Additionally, the lengths of the plurality of lower spacers L_SP may not be uniform. For example, some of the upper spacers (U_SP) may be formed to have a longer height than the others. Additionally, the distance (or spacing) between the upper spacer (U_SP) and the corresponding lower spacer (L_SP) may also not be uniform.

The cell gap of the display panel 100 is fixed by some upper spacers (U_SP) and corresponding lower spacers (L_SP) that have a longer height than the rest. For example, for maintaining the cell gap between the first substrate 110 and the second substrate 115, the sum of the heights of the lower spacer (L_SP) and the corresponding upper spacer (U_SP) is the cell gap and may be the same. As a result, the upper surface of the lower spacer (L_SP) and the lower surface of the corresponding upper spacer (U_SP) can contact each other.

Due to the remaining upper spacer (U_SP) and the corresponding lower spacer (L_SP) having a short height, even if the cell gap of the display panel 100 is momentarily reduced when external pressure is applied to the display panel 100, the cell gap remains. Reduction below a certain value is prevented.

FIGS. 3A to 3D are schematic cross-sectional views and plan views for explaining the upper spacer (U_SP) and lower spacer (L_SP) provided in the display panel 100 according to various embodiments of the present invention. 3A to 3D , for convenience of explanation, planarization is performed in the area where the gate line GL and the data line DL intersect on the first substrate 110 among the components of the display panel 100 described above. Only the contact hole formed in the layer 122 and the planarization layer 122, the pixel electrode 150, the upper spacer (U_SP), and the lower spacer (L_SP) are shown.

Referring to FIG. 3A, the upper spacer (U_SP) and lower spacer (L_SP) are implemented in the form of a bar. The bar-shaped upper spacer (U_SP) and lower spacer (L_SP) may be formed in a light blocking area by the black matrix (BM) disposed along the gate line (GL). The upper spacer (U_SP) overlaps the gate line (GL) and is formed to extend in the same direction as the extension direction of the gate line (GL). The lower spacer (L_SP) disposed at a position corresponding to the upper spacer (U_SP) overlaps the data line (DL) on the first substrate 110 and extends in the same direction as the extension direction of the data line (DL). In FIG. 3A , the upper spacer U_SP is formed to extend along the gate line GL within a range that does not exceed (or does not pass) the contact holes of two adjacent pixel P areas. However, the upper spacer U_SP is not limited to this, and may be formed to extend beyond (or past) the contact holes of the plurality of pixels along the gate line GL.

Referring to FIG. 3B, the upper spacer (U_SP) and the lower spacer (L_SP) are formed to correspond to the light blocking area by the black matrix (BM) disposed along the gate line (GL). In the embodiment of FIG. 3B, the upper spacer (U_SP) extends in the same direction as the extension direction of the data line (DL) and overlaps the data line (DL). The lower spacer (L_SP) disposed at a position corresponding to the upper spacer (U_SP) extends in the same direction as the extending direction of the gate line (GL) on the first substrate 110 and overlaps the gate line (GL). When the first substrate 110 and the second substrate 115 of the upper spacer (U_SP) are slightly offset due to external pressure applied to the display panel 100, the position of the upper spacer (U_SP) changes and the upper spacer (U_SP) (U_SP) may be located on the contact hole. At this time, the upper spacer (U_SP) may not be restored to its original position even after the external pressure applied to the display panel 100 disappears. Therefore, to prevent the upper spacer (U_SP) from getting caught in the contact hole, the horizontal or vertical length of the upper spacer (U_SP) is formed to be long. As a result, the upper spacer (U_SP) is not caught in the contact hole. That is, the upper spacer (U_SP) may be formed so that the horizontal length of the upper spacer (U_SP) is longer than the horizontal length of the contact hole, or the vertical length of the upper spacer (U_SP) is longer than the vertical length of the contact hole.

Alternatively, as shown in FIG. 3B, the lower spacer (L_SP) may be formed in a structure that extends in the same direction as the extension direction of the gate line (GL) and covers a plurality of contact holes. The lower spacer L_SP may be formed in a line shape along the gate line GL and on the gate line GL. When the lower spacer L_SP is formed in a line shape on the gate line GL, it may be difficult to optimize the amount of liquid crystal between the first substrate 110 and the second substrate 115. Accordingly, the lower spacer (L_SP) may be formed to cover only a predetermined number of contact holes adjacent to the lower spacer (L_SP). That is, the lower spacer (L_SP) may not have a line shape. For example, the lower spacer (L_SP) may be formed to have a length that covers only the two contact holes adjacent to the lower spacer (L_SP).

The upper spacer (U_SP) and the lower spacer (L_SP) may be formed in a circular shape, different from the bar shape shown in FIGS. 3A and 3B. Referring to FIG. 3C, the upper spacer (U_SP) and the lower spacer (L_SP) are formed in a light blocking area by the black matrix (BM) disposed along the gate line (GL). The upper spacer (U_SP) may be formed in a cone shape. At this time, the cone-shaped pointed portion faces from the second substrate 115 to the first substrate 110. The lower spacer (L_SP) opposing the upper spacer (U_SP) extends in the same direction as the extending direction of the gate line (GL) on the first substrate 110 and overlaps the gate line (GL). At this time, the diameter of the lower spacer (L_SP) may be longer than the diameter of the upper spacer (U_SP) corresponding to the lower spacer (L_SP). That is, the circle area of the lower spacer may be wider than the circle area of the upper spacer (U_SP) corresponding to the lower spacer (_SP). Additionally, as in the embodiment of FIG. 3B, the lower spacer (L_SP) may cover the contact holes of a plurality of pixels along the gate line (GL), or may cover only two contact holes adjacent to the lower spacer (L_SP).

FIG. 3D is a cross-sectional view showing an example of a spacer (hereinafter referred to as a push spacer) formed with a shorter height than other spacers among a plurality of spacers. The push spacer serves to prevent the cell gap from shrinking below a certain level even if the cell gap is momentarily slightly reduced when an external force is applied to the display panel. Figure 3d shows the upper spacer (U_SP) and lower spacer (L_SP) serving as push spacers. Meanwhile, FIGS. 3A to 3C show an example of a spacer (hereinafter referred to as a gap spacer) formed to have a longer height than other spacers among a plurality of spacers provided on the substrate. Gap spacers serve to fix the cell gap of the display panel. 3A to 3C show an upper spacer (U_SP) and a lower spacer (L_SP) that serve as gap spacers. The distance between the upper spacer (U_SP), which acts as a push spacer, and the lower spacer (L_SP), is farther than the distance between the upper spacer (U_SP), which acts as a gap spacer, and the lower spacer (L_SP). For example, the distance between the upper spacer (U_SP), which acts as a gap spacer, and the lower spacer (L_SP) may be 0 (zero). The upper spacer (U_SP) and lower spacer (L_SP), which act as push spacers, are black matrix (BM) arranged along the gate line (GL), as are the upper spacer (U_SP) and lower spacer (L_SP), which act as gap spacers. ) is formed in the light-shielding area.

In FIG. 3D, the upper spacer (U_SP) and the lower spacer (L_SP), which serve as push spacers, are disposed between contact holes of pixels adjacent to each other along the gate line (GL) axis. The upper spacer (U_SP) and lower spacer (L_SP), which serve as push spacers, are each formed to have a smaller area than the upper spacer (U_SP) and lower spacer (L_SP), which serve as gap spacers. The upper spacer (U_SP) and lower spacer (L_SP), which act as push spacers, extend to the gate line (GL) axis and the other extends to the data line (DL) axis. It can be extended and configured. In addition, the upper spacer (U_SP) and the lower spacer (L_SP), which serve as push spacers, may be configured in such a way that the lower spacer (L_SP) extends along the gate line (GL) and covers two or more contact holes.

The upper spacer (U_SP) and the lower spacer (L_SP) may be formed of the same material or may be formed of different materials. When the lower spacer (L_SP) and the upper spacer (U_SP) are formed of the same material, the friction coefficient, elasticity, and restoring force before and after external pressure become the same between the lower spacer (L_SP) and the upper spacer (U_SP), so that the display panel 100 When designing the upper spacer (U_SP) and lower spacer (L_SP), the optimal height, width, and arrangement relationship can be easily set. However, the production line for the first substrate 110 is also equipped with equipment for producing the upper spacer (U_SP) configured in the production line for the second substrate 115, or the first substrate 110 is moved to various production lines. There may be some hassle in producing it.

The upper spacer (U_SP) and the lower spacer (L_SP) may be formed of an organic material or an inorganic material. In terms of controlling the height and shape of the spacer, it may be relatively easier to form the upper spacer (U_SP) and lower spacer (L_SP) from an organic material. For example, the upper spacer (U_SP) and the lower spacer (L_SP) may be formed of an organic material such as photo acryl (PAC) or polyimide (PI). In order to secure the separation distance between the upper spacer (U_SP) and the alignment layer on the second substrate 115, the height of the lower spacer (L_SP) may be 4000Å or more.

According to the structure and arrangement relationship of the above-described upper spacer (U_SP) and lower spacer (L_SP), even if an external force is applied to the display panel 100, the upper spacer (U_SP) and lower spacer (L_SP) do not contact the alignment film. . As a result, it is possible to prevent light leakage defects caused by distortion of the liquid crystal due to damage to the alignment film. Accordingly, as it is possible to prevent light leakage defects without increasing the width of the black matrix (BM), the display panel 100 with a high aperture ratio and high resolution can be implemented.

4A to 4B are diagrams schematically showing the non-display area (NDA) of the display panel 200 according to an embodiment of the present invention. FIG. 4A is an enlarged plan view showing a portion of the gate link portion (G_Link) and gate driver (GIP) included in the non-display area (NDA) on the first substrate 110. FIG. 4B is a cross-sectional view schematically showing the non-display area (NDA) of the display panel 200 along a line extending from point “A” to point “A’” shown in FIG. 4A.

Referring to FIG. 4A, a gate link portion (G_Link) on which a plurality of external signal wires are formed is formed on the outer side of the first substrate 110, and with the gate link portion (G_Link) as a reference, a gate is formed toward the display area (DA). The driver (GIP) is located. As in various embodiments of the present invention, when the gate driver (GIP) is implemented with the thin film transistor 130 formed on the first substrate 110, the gate link portion (G_Link) and the gate At the same time as the driver (GIP) is formed, a connection wire (CL) is formed to transmit an external signal applied from the external signal wire formed in the gate link unit (G_Link) to the gate driver (GIP). The connection wire (CL) may be located between the gate link part (G_Link) and the gate driver (GIP), or may be formed across the gate link part (G_Link) and the gate driver (GIP).

As shown in FIG. 4A, the connection wire (CL) extends toward the gate driver (GIP) across a plurality of external signal wires. Therefore, the external signal wiring and the connection wiring (CL) of the gate link unit (G_Link) are composed of different conductive layers, and an insulating layer is formed between the conductive layer on which the external signal wiring is formed and the conductive layer on which the connection wiring (CL) is formed. This may be involved. As a result, the connection wire (CL) can be connected to an optional external signal wire and extend across other external signal wires to the gate driver (GIP) side. For electrical connection between two different conductive layers, the display panel 100 is provided with a plurality of bridge areas (BRA).

In Figure 4b, for convenience of explanation, the connection structure of one of the various external signal wires described above is shown as an example. Referring to FIG. 4b, the external signal wire is formed of a first metal layer (M1), the connection wire (CL) is formed of a second metal layer (M2), and one or more insulating layers are formed between the external signal wire and the connection wire (CL). This is included.

For example, the external signal wiring may be formed of a metal layer (Gate Metal) that forms the gate electrode 131 of the thin film transistor 130 formed on the first substrate 110. Additionally, the connection wiring CL may be formed of a metal layer (S/D Metal) that forms the source/drain electrodes 133 and 134 of the thin film transistor 130. At this time, the first metal layer (M1) may be a metal layer (Gate Metal) that forms the gate electrode 131 of the thin film transistor 130 formed on the first substrate 110, and the second metal layer (M2) may be It may be a metal layer (S/D Metal) that forms the source/drain electrodes 133 and 134 of the thin film transistor 130.

Alternatively, the external signal wiring may be formed of a metal layer (S/D Metal) that forms the source/drain electrodes 133 and 134 of the thin film transistor 130 formed on the first substrate 110. Additionally, the connection wire CL may be formed of a metal layer (Gate Metal) that forms the gate electrode 131 of the thin film transistor 130. In this case, a gate insulating layer 121 may be interposed between the external signal wire and the connection wire (CL). At this time, the first metal layer (M1) may be a metal layer (S/D Metal) that forms the source/drain electrodes 133 and 134 of the thin film transistor 130 formed on the first substrate 110. 2 The metal layer (M2) may be a metal layer (Gate Metal) that forms the gate electrode 131 of the thin film transistor 130.

Alternatively, the external signal line may be formed of the same conductive layer as the gate line (GL), and the connection line (CL) may be formed of the same conductive layer as the data line (DL). Additionally, one or more insulating layers may be interposed between the external signal wire and the connection wire (CL). At this time, the first metal layer M1 may be the same conductive layer as the gate line GL, and the second metal layer M2 may be the same conductive layer as the data line DL.

Alternatively, the external signal line may be formed of the same conductive layer as the data line DL, and the connection line CL may be formed of the same conductive layer as the gate line GL. Additionally, an insulating layer similar to the insulating layer interposed between the gate line GL and the data line DL in the display area DA may be interposed between the external signal wire and the connection wire. At this time, the first metal layer M1 may be the same conductive layer as the data line DL, and the second metal layer M2 may be the same conductive layer as the gate line GL.

At least one insulating layer may also be provided on the external signal wire and the connection wire (CL). For example, as shown in FIG. 4B, a passivation layer (PAS) and a planarization layer 122 as an insulating layer may be formed on the external signal wiring and the connection wiring CL. In order to electrically connect the external signal wires and connection wires (CL) formed of different conductive layers, a contact area for each of the external signal wires and connection wires (CL) is installed on the insulating layer on top of the external signal wires and connection wires (CL). An exposed contact hole is formed. On the contact area of the external signal wire and the contact area of the connection wire CL, a bridge electrode BRL is formed that simultaneously contacts the contact area of the external signal wire and the contact area of the connection wire CL. The bridge electrode (BRL) electrically connects the external signal wire and the connection wire (CL).

On the contact hole exposing the contact area of the first metal layer (M1) and the second metal layer (M2), the bridge electrode (BRL) extends and simultaneously contacts the contact area of each conductive layer, thereby connecting the first metal layer (M1) and the second metal layer (M2). The area that electrically connects the two metal layers (M2) is referred to as the bridge area (BRA).

Likewise, the signal input terminal of each stage (ST) of the gate driver (GIP) may be formed of a conductive layer different from the connection wire (CL). For example, as shown in FIG. 4B, the signal input terminal (S_In) of the gate driver (GIP) may be formed of a conductive layer such as the conductive layer that forms the external signal wiring. In this case, the insulating layer covering the connection wiring (CL) and the signal input terminal (S_In) of the gate driver (GIP) includes a contact hole that exposes a part of the gate driver (GIP) side of the connection wiring (CL) and the gate driver (GIP). ) A contact hole is formed exposing part of the signal input terminal (S_In). The contact area of the connection wire (CL) located on the gate driver (GIP) side and the contact area of the signal input terminal (S_In) of the gate driver (GIP) are also a bridge area (BRA) that connects the connection wire (CL) and the external signal wire. are connected to each other with the same structure. As a result, the external signal applied from the external signal wiring is transmitted to the gate driver (GIP). That is, through the contact hole of the insulating layer covering the external signal wiring and the connecting wiring (CL), the first metal layer (M1) forming the external signal wiring located below the insulating layer and the second metal layer (M1) forming the connecting wiring (CL). A plurality of bridge electrode (BRL) patterns contacting the metal layer (M2) are formed in the gate link portion (G_Link).

In addition, the signal applied from the driving circuit shown in FIG. 1 is transmitted to the data driver, or the data signal output from the data driver provided in the data pad portion D_Pad in the COG method is transmitted to the data line disposed in the display area DA. The data link wire (D_LL) for transmission to (DL), like the connection wire (CL) formed between the external signal wire and the gate driver (GIP), connects the bridge electrode (BRL) formed on the top of each corresponding contact hole. can be electrically connected through Therefore, not only can a plurality of bridge areas (BRA) be provided around the gate link part (G_Link) and the gate driver (GIP), but also a non-display area ( Multiple bridge areas (BRA) may also be formed in NDA). For example, the bridge area (BRA) may also be applied to the pad area (PAD) shown in FIG. 1.

As described above, in order to implement a narrower bezel width and at the same time reinforce the adhesive force between the first substrate 110 and the second substrate 115, the seal area (Seal) is formed in the non-display area (NDA). It may overlap with the gate link unit (G_Link) or the gate link unit (G_Link) and gate driver (GIP). Additionally, the sealant may be applied on the bridge area BRA to partially cover the bridge area BRA. However, the bridge electrode (BRL) formed in the bridge area (BRA) may be made of a material that has poor adhesion to the sealant. For example, a bridge electrode (BRL) made of indium tin oxide (ITO) not only has poor adhesion to the sealant, but also can easily crack due to external force transmitted through the cured sealant. In other words, even if the sealant extends to a part of the gate driver (GIP), defective adhesion of the first substrate 110 and the second substrate 115 occurs due to weakening of the adhesive force between the sealant and the bridge electrode (BRL). It can happen. Additionally, when a crack occurs in the bridge electrode (BRL) overlapping with the sealant, foreign substances penetrate through the crack and cause corrosion/corrosion of the metal wires under the bridge electrode (BRL).

Accordingly, in the display panel 200 according to an embodiment of the present invention, some of the plurality of lower spacers (L_SP) formed on the first substrate 110 correspond to the bridge area (BRA) of the first substrate 110. It includes a lower spacer (L_SP) formed in position. In other words, some of the lower spacers L_SP provided on the first substrate 110 are formed to cover the bridge electrode BRL located in the non-display area NDA. The lower spacer (L_SP) disposed on the bridge area (BRA) may be provided so that one individual lower spacer (L_SP) covers one bridge area (BRA), as shown in FIGS. 4A and 4B. . In FIG. 4B, the lower spacer (L_SP) covering the bridge electrode (BRL) that electrically connects the external signal wire and the connection wire (CL) fills the contact hole formed for the bridge electrode (BRL) to contact the contact area. is formed Likewise, the lower spacer (L_SP) covering the bridge electrode (BRL), which electrically connects the connection wire (CL) and the signal input terminal (S_In) of the gate driver (GIP), is also used to allow the bridge electrode (BRL) to contact the contact area. It is formed to fill the formed contact hole.

The lower spacer (L_SP) disposed in the non-display area (NDA) and covering the bridge area (BRA) is made of the same material as the lower spacer (L_SP) disposed in the display area (DA) and disposed to correspond to the upper spacer (U_SP). Formed in the same process. Accordingly, the lower spacer L_SP disposed in the non-display area NDA and covering the bridge area BRA and the lower spacer L_SP disposed in the display area DA may be formed at the same height. However, since the structures formed between the first substrate 110 and the second substrate 115 may be different in the display area DA and the non-display area NDA, respectively, they are disposed in the non-display area NDA. The lower spacer L_SP covering the bridge area BRA and the lower spacer L_SP disposed in the display area DA may be formed at different heights as needed. For example, the lower spacer (L_SP) formed in the non-display area (NDA) to cover the bridge area (BRA) may also affect the cell gap between the first substrate 110 and the second substrate 115. there is. Accordingly, the lower spacer L_SP covering the bridge area BRA can be formed at a lower height than the lower spacer L_SP formed in the display area DA. As another example, in terms of protecting the bridge area (BRA), the height of the lower spacer (L_SP) covering the bridge area (BRA) is formed to be higher than the lower spacer (L_SP) formed in the display area (DA). It may be more desirable. A Half-Tone mask can be used to make the heights of the lower spacer (L_SP) covering the bridge area (BRA) and the lower spacer (L_SP) disposed in the display area (DA) different from each other.

In FIG. 4B, the lower spacer L_SP covering the bridge electrode BRL in the bridge area BRA is shown as being covered with a sealant. However, as described above, the seal area (Seal) may overlap with part of the gate link part (G_Link), and the remaining part of the gate link part (G_Link) may not overlap with the seal area (Seal). In addition, even if the seal area (Seal) overlaps the entire gate link part (G_Link), some bridge areas (BRA) provided in the gate driver (GIP) may be located outside of the seal area (Seal). You can. In other words, the bridge area (BRA) may be provided even in a place that does not overlap with the seal area, and the lower spacer (L_SP) may also be provided on the bridge area (BRA) that does not overlap with the seal area. It may be available.

As shown in FIG. 4b, when the lower spacer (L_SP) is formed locally in each bridge area (BRA) located below the sealant, due to the step caused by the lower spacer (L_SP), the spacer is formed around the seal area (Seal). Stains may occur. In order to reduce the step caused by the lower spacer (L_SP) in the seal area (Seal), one lower spacer (L_SP) may be arranged to cover the plurality of bridge areas (BRA).

FIG. 4C is a cross-sectional view schematically showing the display panel 300 provided with lower spacers (L_SP) extended and disposed on a plurality of bridge areas (BRA) according to an embodiment of the present invention. Referring to Figure 4c, a bridge area (BRA) connects the external signal wire and the connection wire (CL), and a bridge area (BRA) connects the connection wire (CL) and the signal input terminal (S_In) of the gate driver (GIP). This is covered by one lower spacer (L_SP). In this way, by forming one lower spacer (L_SP) to correspond to the plurality of bridge areas (BRA), the step caused by the lower spacer (L_SP) disposed below the sealant can be reduced.

The lower spacer (L_SP) placed in the non-display area (NDA) extends not only to the two bridge areas (BRA) located at both ends of the connection wire (CL), but also to other bridge areas (BRA) around it, creating two or more bridge areas. It can be formed to cover (BRA). Considering the adhesion between the material forming the lower spacer (L_SP) and the sealant, the lower spacer (L_SP) in the non-display area (NDA) covers part or the entire surface of the gate link part (G_Link) in a single pattern, or covers the gate link part (G_Link). It may be formed to cover part or the entire driver (GIP). For example, the lower spacer (L_SP) is made of a material such as photo acryl (PAC) or polyimide (PI), and the bridge electrode (BRL) is made of indium tin oxide (ITO). When formed, the lower spacer (L_SP) has better adhesion to the sealant than the bridge electrode (BRL). Therefore, rather than the lower spacer (L_SP) that locally covers each bridge area (BRA) 1:1, a lower spacer (L_SP) of a single pattern with a constant area in proportion to the area of the seal area (Seal) is used in the gate link unit. Arranging it across the (G_Link) and the gate driver (GIP) may be more advantageous for bonding the first substrate 110 and the second substrate 115 and protecting the bridge area (BRA).

Figure 5 is a diagram schematically showing the non-display area (NDA) of the display panel 400 according to an embodiment of the present invention.

Since the same description as the above description applies to the same components as the above-described components, separate descriptions will not be repeated, and only the parts that need to be added to the above-described description will be added.

5 shows a gate insulating layer 121 on the first substrate 110, a first metal layer (M1) on the gate insulating layer 121, an interlayer (Interlayer) 120 on the first metal layer (M1), and an interlayer. A second metal layer (M2) on (120), a first passivation layer (PAS1) covering the second metal layer (M2), a planarization layer 122 on the first passivation layer (PAS1), disposed on the planarization layer 122. A third metal layer (M3) disposed on the trench (T), contact hole, and planarization layer (122) and connected to the second metal layer (M2) by a contact hole, and a second passivation layer covering the third metal layer (M3) (PAS2) may be included. Additionally, a sealant for bonding the first substrate 110 and the second substrate 115 is disposed on the outside of the display panel 400. The sealant is disposed between the overcoating layer OC disposed on the lower portion of the second substrate 115 and the second passivation layer PAS2 disposed on the upper portion of the first substrate 110 . The upper alignment layer (U_AL) is disposed under the overcoating layer (OC) disposed on the lower portion of the second substrate 115 so as not to overlap the sealant. Additionally, the lower alignment layer L_AL is disposed on the second passivation layer PAS2 disposed on the upper part of the first substrate 110 so as not to overlap the sealant. The black matrix BM is disposed in part or the entire non-display area NDA to cover various metal wires disposed in the non-display area NDA.

The upper dam (U_DM) and the lower dam (L_DM) are disposed at a point where the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) may overlap. The upper dam (U_DM) is disposed under the overcoating layer (OC) disposed on the lower portion of the second substrate 115, and the lower dam (L_DM) is disposed on the upper portion of the first substrate 110. It is placed on PAS2). A trench T formed in the planarization layer 122 is formed at a point where the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) may overlap.

In the non-display area (NDA), a touch wiring area (RVcomA) including a plurality of touch wires (RVcom_1, RVcom_2) densely arranged from the end of the display area (DA) toward the outside of the display panel 400, and a gate driver. (GIP) and gate link unit (G_Link) are arranged sequentially. That is, among the touch wiring area (RVcomA), gate driver (GIP), and gate link part (G_Link) included in the non-display area (NDA), the touch wiring area (RVcomA) is placed closest to the display area (DA).

Touch detection performance can be improved by lowering the resistance of the touch wiring (RVcom_1, RVcom_2). However, when the width of the touch wires (RVcom_1, RVcom_2) is widened to lower the resistance of the touch wires (RVcom_1, RVcom_2), there is a disadvantage that the bezel width increases. In order to lower the resistance of the touch wires (RVcom_1, RVcom_2) without increasing the bezel width, the touch wires (RVcom_1, RVcom_2) are arranged as closely as possible, and the touch wires (RVcom_1, RVcom_2) are overlapped in multiple layers. Then, the touch wire (RVcom_2) on the upper floor and the touch wire (RVcom_1) on the lower floor are electrically connected through the contact hole of the planarization layer (122). More specifically, a plurality of first touch wires (RVcom_1) are formed in the touch wire area (RVcomA) by the second metal layer (M2). In addition, in the touch wiring area (RVcomA), a planarization layer 122 is disposed on the first touch wiring (RVcom_1), and has a shape that overlaps the first touch wiring (RVcom_1) on the planarization layer 122, and a third metal layer (M3) is formed. ) to form a plurality of second touch wires (RVcom_2). Also, the first touch wire (RVcom_1) and the corresponding second touch wire (RVcom_2) are connected to each other through a contact hole formed in the planarization layer 122. This has the effect of reducing the resistance of each touch wire (RVcom_1, RVcom_2) while making it possible to narrow the bezel width.

The touch wires (RVcom_1, RVcom_2) can connect the above-described common electrode line and the touch driver. As a result, the display panel 400 capable of detecting a touch can be implemented by applying a signal for detecting a touch input to a common electrode line connected to the touch wires (RVcom_1, RVcom_2).

On the second passivation layer (PAS2), a sealant may be disposed to overlap the entire area of the gate link part (G_Link) and a partial area of the gate driver (GIP). In other words, the seal area (Seal) where the sealant is applied can overlap the gate link part (G_Link) and the gate driver (GIP) among the non-display area (NDA). In any case, the seal-area (Seal) does not overlap with the touch wiring area (RVcomA).

The seal area formed by placing a sealant on the outside of the display panel 400 secures a space for the liquid crystal layer LC between the first substrate 110 and the second substrate 115. do. That is, the first substrate 110 and the second substrate 115 are bonded to each other while securing a cell gap by the sealant of the seal area, and the liquid crystal layer LC defined corresponding to the cell gap is Liquid crystal does not leak out of the display panel 400. Sealant may be composed of a material that is applied in a fluid liquid state and hardened by photocuring. If the sealant is made of a photocurable material, high-energy light such as UV must be irradiated toward the seal area to cure the sealant. At this time, when high-energy light is irradiated from the second substrate 115 to the seal area (Seal), the light does not reach the seal area (Seal) due to the black matrix (BM) that absorbs light. It is not effective because it is not effective. Therefore, it is possible to irradiate high energy light from the first substrate 110 to the seal area. If the sealant is applied to the touch wiring area (RVcomA), or if the sealant is not applied to the touch wiring area (RVcomA) but spreads in the direction (D1) of the display area (DA), the sealant may be applied to the touch wiring area (RVcomA). ) can also be present. In this case, in order to cure the sealant, light is irradiated from the first substrate 110 to the seal area (Seal), not only to the gate link part (G_Link) and gate driver (GIP), but also to the touch wiring area (RVcomA). It may be necessary to irradiate light. However, in the touch wiring area RVcomA, since most of the light is reflected by the plurality of closely spaced touch wirings RVcom_1 and RVcom_2, a sufficient amount of light does not reach the sealant.

More specifically, the degree to which metal wiring is dense in a certain area of the circuit area can be expressed by the open ratio in that area. The aperture ratio in the corresponding area refers to the ratio of the area not covered by the metal wiring among the total area of the corresponding area. Among the circuit areas, the touch wiring area (RVcomA) has an aperture ratio of 20% or less due to a plurality of touch wirings tightly arranged. However, light must be irradiated in an area with an aperture ratio of at least 50% or more for light sufficient to photocure the sealant to reach the sealant. In other words, light sufficient to photocure the sealant does not reach the sealant through the touch wiring area (RVcomA).

Therefore, the sealant should not be applied on the circuit area where metal wiring is arranged at a high density. Additionally, the sealant should not spread over areas where metal wiring is densely arranged in the circuit area. If the sealant is applied or spread to an area in the circuit area where metal wires are arranged at a high density, the amount of light sufficient to photocure the sealant in the area does not reach the sealant due to the metal wires that reflect light. Ultimately, as the sealant in the corresponding area is not cured, it becomes a factor in poor adhesion between the first substrate 110 and the second substrate 115. At this time, among the circuit areas, an area where metal wiring is arranged at a high density means an area where the opening ratio of the area is less than 50%. Therefore, the sealant should not spread over the circuit area where the opening ratio is less than 50%. In other words, the sealant must be placed on the circuit area where the opening ratio is 50% or more. For example, sealant is not applied over the touch wiring area (RVcomA). Additionally, the sealant does not spread over the touch wiring area (RVcomA).

To prevent the sealant from spreading over the touch wiring area (RVcomA), there is an upper dam (U_DM) and a lower dam (L_DM) corresponding to the upper dam (U_DM) between the seal area (Seal) and the touch wiring area (RVcomA). It is placed. The upper dam (U_DM) faces the first substrate 110 and rests on the overcoating layer (OC). In other words, the upper dam (U_DM) is disposed to protrude from the overcoating layer (OC) toward the first substrate 110. The lower dam (L_DM) rises toward the second substrate 115 from the second passivation layer (PAS2), corresponding to the upper dam (U_DM). In other words, the lower dam (L_DM) is disposed to protrude from the second passivation layer (PAS2) toward the second substrate 115, corresponding to the upper dam (U_DM). For example, the upper dam (U_DM) and the lower dam (L_DM) may be arranged across the boundary between the touch wiring area (RVcomA) and the gate driver (GIP). Alternatively, the upper dam (U_DM) and the lower dam (L_DM) may be disposed biased toward the gate driver (GIP) based on the boundary between the touch wiring area (RVcomA) and the gate driver (GIP).

The upper dam (U_DM) may be formed of the same material and in the same process as the above-described upper spacer (U_SP). Additionally, the lower dam (L_DM) may be formed of the same material and in the same process as the above-described lower spacer (L_SP). For example, the upper dam (U_DM) and the lower dam (L_DM) may be formed of polyimide (PI) or photo acryl (PAC).

The upper alignment layer (U_AL) is formed by an alignment material and determines the initial alignment direction of the liquid crystal included in the liquid crystal layer (LC). For example, the alignment material constituting the upper alignment layer (U_AL) may be polyimide (PI). The upper alignment layer (U_AL) is disposed in the display area (DA) under the overcoating layer (OC). Accordingly, the upper alignment layer (U_AL) is surrounded by the sealant disposed in the non-display area (NDA). The alignment material for forming the upper alignment layer (U_AL) is applied in a fluid liquid state to one side of the overcoating layer (OC) corresponding to the display area (DA). Depending on the spreading property of the alignment material, the alignment material may not only be formed in the display area (DA) but may also spread in the non-display area (NDA) direction D2. Accordingly, the upper alignment layer (U_AL) may be formed to extend to the non-display area (NDA).

Like the upper alignment layer (U_AL), the lower alignment layer (L_AL) is also formed of an alignment material and determines the initial alignment direction of the liquid crystal included in the liquid crystal layer (LC). For example, the alignment material constituting the lower alignment layer (L_AL) may be polyimide (PI). The lower alignment layer (L_AL) is disposed in the display area (DA) on the second passivation layer (PAS2). Accordingly, the lower alignment layer (L_AL) is surrounded by the sealant disposed in the non-display area (NDA). The alignment material for forming the lower alignment layer (L_AL) is applied in a fluid liquid state to one side of the overcoating layer (OC) corresponding to the display area (DA). Depending on the spreading property of the alignment material, the alignment material may not only be formed in the display area (DA) but may also spread in the non-display area (NDA) direction D2. Accordingly, the lower alignment layer (L_AL) may be formed to extend to the non-display area (NDA).

The sealant in the seal area is also applied and spread in a fluid liquid state before curing. As the sealant spreads in the display area DA direction D1, there is a possibility that it partially covers the upper alignment layer U_AL or the lower alignment layer L_AL. That is, there is a possibility that the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) overlap. However, when the second passivation layer (PAS2) is made of a silicon-based inorganic material and the upper alignment layer (U_AL) or the lower alignment layer (L_AL) is made of polyimide, the gap between the sealant and the second passivation layer (PAS2) The adhesive force is much stronger than the adhesive force between the sealant and the upper alignment layer (U_AL) or the lower alignment layer (L_AL). That is, in the area where the sealant and the upper alignment layer (U_AL) or lower alignment layer (L_AL) overlap each other, the bonding strength of the first substrate 110 and the second substrate 115 by the sealant is lowered. This causes poor adhesion between the first substrate 110 and the second substrate 115.

Accordingly, the upper dam (U_DM) and the lower dam (L_DM) are arranged so that the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) do not overlap. Alternatively, the upper dam U_DM and the lower dam L_DM are arranged so that the sealant does not spread in the display area DA direction D1. The area where the upper dam (U_DM) and lower dam (L_DM) are placed is called the overlap prevention area (OA). The overlap prevention area (OA) may be placed across the boundary between the touch wiring area (RVcomA) and the gate driver (GIP). Alternatively, the overlap prevention area (OA) may be disposed with a bias toward the gate driver (GIP) based on the boundary between the touch wiring area (RVcomA) and the gate driver (GIP). As a result, it is possible to prevent the bonding strength of the first substrate 110 and the second substrate 115 from being reduced due to the sealant.

A plurality of trenches T are formed in the planarization layer 122 to increase the adhesive strength of the sealant. At a position corresponding to the edge of the sealant, the planarization layer 122 is recessed to form a trench T. The area where a plurality of trenches (T) are arranged is called a trench area (TA). When the applied sealant spreads in the display area DA direction D1, the sealant flows into the trench T. As the sealant fills the curves of the trench (T), the adhesive area of the sealant increases. As the adhesive area of the sealant increases, the adhesive strength of the sealant improves. In addition, even if the sealant spreads in the display area DA direction D1, the degree of spread, that is, the spread width, decreases as it fills the trench T. As the spread width of the sealant is reduced, the phenomenon of overlap between the sealant and the lower alignment layer (L_AL) can be minimized. In addition, the overlapping phenomenon between the sealant and the lower alignment layer (L_AL) is minimized by the trench (T), thereby preventing a decrease in the bonding strength of the first substrate 110 and the second substrate 115 due to the sealant. can do.

The overlap prevention area (OA) and the trench area (TA) are disposed adjacent to the boundary of the touch wiring area (RVcomA) and the gate driver (GIP) and overlap each other.

At this time, the overlap prevention area (OA) and the trench area (TA) may be disposed with a bias toward the gate driver (GIP) based on the boundary between the touch wiring area (RVcomA) and the gate driver (GIP).

Alternatively, the overlap prevention area (OA) is placed across the boundary between the touch wiring area (RVcomA) and the gate driver (GIP), and the trench area (TA) is based on the boundary between the touch wiring area (RVcomA) and the gate driver (GIP). Therefore, it can be placed biased toward the gate driver (GIP). In other words, a portion of the overlap prevention area (OA) and a portion of the trench area (TA) overlap, and the overlap prevention area (OA) may be placed closer to the touch wiring area (RVcomA) than the trench area (TA). That is, the upper dam (U_DM) and lower dam (L_DM) are placed across the boundary between the touch wiring area (RVcomA) and the gate driver (GIP), and the trench (T) is located between the touch wiring area (RVcomA) and the gate driver (GIP). Based on the boundary of , it can be placed biased toward the gate driver (GIP). Since the trench T is constructed by forming a groove in the planarization layer 122, it will be placed in the touch wiring area (RVcomA) where the touch wiring on the upper layer and the touch wiring on the lower layer are connected by the contact hole in the planarization layer 122. On the other hand, the upper dam (U_DM) and the lower dam (L_DM) are located on the touch wiring, so they can be placed in the touch wiring area (RVcomA). As a result, as the sealant spreads in the display area (DA) direction (D1), the trench (T) primarily acts as a pool to receive the sealant, and secondarily, the upper dam (U_DM) and lower dam (L_DM) ) can act as a barrier to prevent the sealant from flowing into the touch wiring area (RVcomA).

Figure 6 is a diagram schematically showing the non-display area (NDA) of the display panel 500 according to an embodiment of the present invention.

Since the same description as the above description applies to the same components as the above-described components, separate descriptions will not be repeated, and only the parts that need to be added to the above-described description will be added.

6 shows a gate insulating layer 121 on the first substrate 110, a first metal layer (M1) on the gate insulating layer 121, an interlayer (Interlayer) 120 on the first metal layer (M1), and an interlayer. A second metal layer (M2) on (120) and a flattening layer (122) covering the second metal layer (M2), a second sub-metal layer (M2_s) and a second sub-metal layer (M2_s) on the planarization layer (122). A covering sub-flattening layer 122_s, a trench T and a contact hole disposed on the sub-flattening layer 122_s, and a third metal layer disposed on the sub-flattening layer 122_s and connected to the second metal layer M2 by a contact hole. It may include a metal layer (M3) and a second passivation layer (PAS2) covering the third metal layer (M3). At this time, the sub-planarization layer 122_s may be made of the same material as the planarization layer 122.

The upper dam (U_DM) and the lower dam (L_DM) are disposed at a point where the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) may overlap. The upper dam (U_DM) is disposed under the overcoating layer (OC) disposed on the lower portion of the second substrate 115, and the lower dam (L_DM) is disposed on the upper portion of the first substrate 110. It is placed on PAS2). A trench (T) formed in the sub-planarization layer is formed at a point where the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) may overlap.

Touch detection performance can be improved by lowering the resistance of the touch wiring (RVcom_1, RVcom_2, RVcom_3). However, when the width of the touch wires (RVcom_1, RVcom_2, RVcom_3) is widened to lower the resistance of the touch wires (RVcom_1, RVcom_2, RVcom_3), there is a disadvantage that the bezel width increases. In order to lower the resistance of the touch wires (RVcom_1, RVcom_2, RVcom_3) without increasing the bezel width, the touch wires (RVcom_1, RVcom_2, RVcom_3) are arranged as closely as possible, and the touch wires (RVcom_1, RVcom_2, RVcom_3) are laid out in multiple layers. Formed by overlapping. Then, electrically connect the touch wires (RVcom_2, RVcom_3) on the upper floor to the touch wires (RVcom_1, RVcom_3) on the lower floor. More specifically, a plurality of first touch wires (RVcom_1) are formed in the touch wire area (RVcomA) by the second metal layer (M2). In addition, in the touch wiring area RVcomA, a planarization layer 122 is disposed on the first touch wiring RVcom_1, and has a shape that overlaps the first touch wiring RVcom_1 on the planarization layer 122, and a second sub-metal layer ( A plurality of third touch wires (RVcom_3) may be formed by M2_s). Additionally, in the touch wiring area (RVcomA), a sub-flattening layer (122_s) is disposed on the third touch wiring (RVcom_3), and has a shape that overlaps the third touch wiring (RVcom_3) on the sub-flattening layer (122_s), and a third metal layer is formed. A plurality of second touch wires (RVcom_2) may be formed by (M3). And the first touch wire (RVcom_1) and the corresponding third touch wire (RVcom_3) are connected to each other through a contact hole formed in the planarization layer 122. And the third touch wire (RVcom_3) and the corresponding second touch wire (RVcom_2) are connected to each other through a contact hole formed in the sub-flattening layer (122_s). By using the three-layer touch wires (RVcom_1, RVcom_2, RVcom_3), the bezel width can be narrowed while reducing the resistance of each touch wire (RVcom_1, RVcom_2, RVcom_3).

FIGS. 7A to 7H are plan views corresponding to the anti-overlap area (OA) shown in FIG. 5.

Referring to FIG. 7A, the upper dam (U_DM) and the lower dam (L_DM) overlap each other and are disposed in a solid line between the seal area (Seal) and the alignment layer (AL). Considering that the upper dam (U_DM) and the lower dam (L_DM) overlap each other to form a pair, there may be two or three pairs of the upper dam (U_DM) and the lower dam (L_DM). When there are multiple pairs of the upper dam (U_DM) and the lower dam (L_DM), the separation distance between the upper dam (U_DM) and the lower dam (L_DM) may be different for each pair. For example, the closer the pair is to the seal area, the farther the separation distance between the upper dam (U_DM) and the lower dam (L_DM) may be. Additionally, for the pair furthest from the seal area (Seal), the separation distance between the upper dam (U_DM) and the lower dam (L_DM) may be substantially 0 (zero). Accordingly, when the sealant spreads in the direction D1 of the display area DA, a certain amount of sealant can be leaked by a pair close to the sealant, thereby preventing the sealant from bursting during bonding. In addition, by completely blocking the sealant by a pair far from the sealant, it is possible to prevent the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7b, the upper dam (U_DM) and the lower dam (L_DM) overlap each other, but the upper dam (U_DM) is arranged in a dotted line between the seal-area (Seal) and the alignment film (AL), and the lower dam (U_DM) is disposed in a dotted line shape. The dam (L_DM) is arranged in a solid line between the seal-area (Seal) and the alignment layer (AL). Considering that the upper dam (U_DM) and the lower dam (L_DM) overlap each other to form a pair, there may be two or three pairs of the upper dam (U_DM) and the lower dam (L_DM). In particular, when the sealant flows along the second passivation layer (PAS2) as the first substrate 110 is placed below and the second substrate 115 is placed above and cemented and cured, the lower dam ( It is advantageous for L_DM) to be arranged in a solid line. Since the lower dam (L_DM) is arranged linearly and the upper dam (U_DM) is arranged in a dotted line, a gap is created in an area where there is no upper dam (U_DM) corresponding to the lower dam (L_DM). As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created in the area where there is no upper dam (U_DM) corresponding to the lower dam (L_DM). This can prevent the sealant from bursting during cementation. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7C, the upper dam (U_DM) and the lower dam (L_DM) overlap each other and are arranged in a dotted line between the seal area (Seal) and the alignment layer (AL). Considering that the upper dam (U_DM) and the lower dam (L_DM) overlap each other to form a pair, there may be two or three pairs of the upper dam (U_DM) and the lower dam (L_DM). As the lower dam (L_DM) and upper dam (U_DM) are arranged in a dotted line, a gap is created in the area where there is no lower dam and upper dam (U_DM). As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created in the area where there is no lower dam and upper dam (U_DM), thereby preventing the sealant from bursting when cemented. can do. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7D, the upper dam (U_DM) and the lower dam (L_DM) are arranged in a solid line between the seal area (Seal) and the alignment layer (AL) while being staggered. Considering that the upper dam (U_DM) and lower dam (L_DM) are arranged alternately to form a pair, the number of pairs formed by the upper dam (U_DM) and lower dam (L_DM) may be two or three. As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created by the upper dam (U_DM) and lower dam (L_DM) being staggered, thereby ensuring cementation. This can prevent the sealant from bursting. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7e, the upper dam (U_DM) and the lower dam (L_DM) are arranged in a staggered manner, with the upper dam (U_DM) arranged in a dotted line shape between the seal-area (Seal) and the alignment film (AL), and the lower dam (U_DM) The dam (L_DM) is arranged in a solid line between the seal-area (Seal) and the alignment layer (AL). Considering that the upper dam (U_DM) and lower dam (L_DM) are arranged alternately to form a pair, the number of pairs formed by the upper dam (U_DM) and lower dam (L_DM) may be two or three. In particular, when the sealant flows along the second passivation layer (PAS2) as the first substrate 110 is placed below and the second substrate 115 is placed above and cemented and cured, the lower dam ( It is advantageous for L_DM) to be arranged in a solid line. As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created by the upper dam (U_DM) and lower dam (L_DM) being staggered, thereby ensuring cementation. This can prevent the sealant from bursting. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7f, the upper dam (U_DM) and the lower dam (L_DM) are arranged in a staggered manner, with the upper dam (U_DM) arranged in a solid line between the seal-area (Seal) and the alignment film (AL), and the lower dam (U_DM) The dam (L_DM) is arranged in a dotted line shape between the seal area (Seal) and the alignment layer (AL). Considering that the upper dam (U_DM) and lower dam (L_DM) are arranged alternately to form a pair, the number of pairs formed by the upper dam (U_DM) and lower dam (L_DM) may be two or three. In particular, when the sealant flows along the overcoating layer (OC) as the first substrate 110 is placed on top and the second substrate 115 is placed below and curing proceeds, the upper dam (U_DM) It is advantageous to arrange this in a solid line. As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created by the upper dam (U_DM) and lower dam (L_DM) being staggered, thereby allowing a certain amount of sealant to leak out during cementation. This can prevent the sealant from bursting. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7G, the upper dam (U_DM) and the lower dam (L_DM) are arranged in a dotted line shape along the seal area (Seal) and the alignment layer (AL) while being staggered. Considering that the upper dam (U_DM) and lower dam (L_DM) are arranged alternately to form a pair, the number of pairs formed by the upper dam (U_DM) and lower dam (L_DM) may be two or three. The lower dam (L_DM) and the upper dam (U_DM) are arranged in a dotted line and staggered, so that the area without the lower dam (L_DM) and the upper dam (U_DM), the upper dam (U_DM) corresponding to the lower dam (L_DM) ) A gap is created in the area where there is no lower dam (L_DM) corresponding to the upper dam (U_DM). As a result, when the sealant spreads in the display area (DA) direction (D1), a certain amount of sealant can leak out through the gap created by the upper dam (U_DM) and lower dam (L_DM) being staggered, thereby allowing a certain amount of sealant to leak out during cementation. This can prevent the sealant from bursting. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

Referring to FIG. 7h, the upper dam (U_DM) and the lower dam (L_DM) are arranged in a dotted line shape along the seal-area (Seal) and the alignment layer (AL), alternating with each other, while simultaneously forming a checkered shape. It is placed. Considering that the upper dam (U_DM) and lower dam (L_DM) are arranged alternately to form a pair, the number of pairs formed by the upper dam (U_DM) and lower dam (L_DM) may be two or three. As the lower dam (L_DM) and upper dam (U_DM) are arranged in a dotted line and staggered to form a checkered shape, the area where there is no upper dam (U_DM) corresponding to the lower dam (L_DM) and the upper dam A gap is created in the area where there is no lower dam (L_DM) corresponding to (U_DM). Accordingly, when the sealant spreads in the display area (DA) direction D1, the upper dam (U_DM) and the lower dam (L_DM) are arranged to form a checkered pattern, allowing a certain amount of sealant to leak out through the gap created. This can prevent the sealant from bursting during cementation. In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

The overlap prevention area (OA) shown in FIGS. 7A to 7H can be applied in combination not only to the display panel shown in FIG. 5 but also to various embodiments of the present invention.

Figures 8a to 8d are plan views corresponding to the overlap prevention area (OA) and trench area (TA) shown in Figure 5.

As for the overlap prevention area (OA) shown in FIG. 5, a plan view of the overlap prevention area (OA) shown in FIG. 7A is shown, but this is only an example and is not limited thereto. That is, any one of FIGS. 7B to 7H can be applied to FIG. 8A as the overlap prevention area (OA) shown in FIG. 5. In addition, even if not shown, any type of overlap prevention area (OA) that falls within the scope described as the present invention through the detailed description of the invention can be applied to FIG. 8A.

Referring to FIG. 8A, the upper dam (U_DM) and the lower dam (L_DM) overlap each other and are disposed in a solid line between the seal area (Seal) and the alignment layer (AL). In contrast, the plurality of trenches T are arranged in a plurality of solid lines intersecting the upper dam U_DM and the lower dam L_DM. When the sealant spreads in the display area (DA) direction (D1), the pair formed by the upper dam (U_DM) and the lower dam (L_DM) sequentially comes into contact with the sealant, while the plurality of trenches (T) are all exposed in no order. It comes into contact with the sealant under equal conditions. Additionally, the sealant first fills a plurality of trenches (T) before leaking beyond the upper dam (U_DM) and lower dam (L_DM). Therefore, as the area in contact with the sealant increases with the trench (T), the adhesive strength of the sealant increases, and the trench (T) provides a space where the sealant can stay without exceeding the overlap prevention area (OA). The spread width of the sealant can be controlled. The path of the trench (T) can be made longer by the plurality of trenches (T) crossing the solid or dotted upper dam (U_DM) and lower dam (L_DM) diagonally rather than perpendicular to them. By making the path of the trench (T) longer, the space where the sealant can stay without crossing the overlap prevention area (OA) can be increased.

Referring to FIG. 8B, the upper dam and the lower dam (L_DM) overlap each other and are arranged in a solid line between the seal area (Seal) and the alignment film (AL). In contrast, the plurality of trenches (T) are arranged in a plurality of solid lines orthogonal to the upper dam (U_DM) and the lower dam (L_DM) in the form of solid or dotted lines. When the sealant spreads in the display area (DA) direction (D1), the pair formed by the upper dam (U_DM) and the lower dam (L_DM) sequentially comes into contact with the sealant, while the plurality of trenches (T) are all exposed in no order. It comes into contact with the sealant under equal conditions. Additionally, the sealant first fills a plurality of trenches (T) before leaking beyond the upper dam (U_DM) and lower dam (L_DM). Therefore, as the area in contact with the sealant increases with the trench (T), the adhesive strength of the sealant increases, and the trench (T) provides a space where the sealant can stay without exceeding the overlap prevention area (OA). The spread width of the sealant can be controlled.

Referring to FIG. 8C, the upper dam (U_DM) and the lower dam (L_DM) overlap each other and are disposed in a solid line between the seal area (Seal) and the alignment layer (AL). In contrast, the plurality of trenches T are arranged in a plurality of solid lines adjacent to the upper dam U_DM and the lower dam L_DM in the solid line shape. When the sealant spreads in the display area (DA) direction (D1), the pair formed by the upper dam (U_DM) and the lower dam (L_DM) sequentially comes into contact with the sealant, and the plurality of trenches (T) are also sequentially sealed. comes into contact with Additionally, the sealant first fills the trench (T) before leaking beyond the upper dam (U_DM) and lower dam (L_DM). Therefore, as the area in contact with the sealant increases with the trench (T), the adhesive strength of the sealant increases, and the trench (T) provides a space where the sealant can stay without exceeding the overlap prevention area (OA). The spread width of the sealant can be controlled.

Referring to FIG. 8D, the upper dam (U_DM) and the lower dam (L_DM) overlap each other and are arranged in a solid line between the seal area (Seal) and the alignment layer (AL). In contrast, the plurality of trenches (T) are arranged in a plurality of V shapes intersecting the solid upper dam (U_DM) and lower dam (L_DM). When the sealant spreads in the display area (DA) direction (D1), the pair formed by the upper dam (U_DM) and the lower dam (L_DM) sequentially comes into contact with the sealant, while the plurality of trenches (T) are all exposed in no order. It comes into contact with the sealant under equal conditions. Additionally, the sealant first fills a plurality of trenches (T) before leaking beyond the upper dam (U_DM) and lower dam (L_DM). Therefore, as the area in contact with the sealant increases with the trench (T), the adhesive strength of the sealant increases, and the trench (T) provides a space where the sealant can stay without exceeding the overlap prevention area (OA). The spread width of the sealant can be controlled. The path of the trench (T) can be made longer by the plurality of trenches (T) crossing the solid or dotted upper dam (U_DM) and lower dam (L_DM) diagonally rather than perpendicular to them. By making the path of the trench (T) longer, the space where the sealant can stay without crossing the overlap prevention area (OA) can be increased. In addition, since the plurality of trenches T are formed in a V shape, the flow rate of the sealant can be lowered by bending the spreading direction of the sealant flowing into the trench T.

The trench area TA shown in FIGS. 8A to 8D can be applied in combination to various embodiments of the present invention as well as the display panel shown in FIG. 5.

In various embodiments of the present invention described with reference to the drawings, the sealant has improved adhesion in the area where the gate link part (G_Link) and gate driver (GIP) arranged in the seal area and the non-display area (NDA) overlap. By having it, not only can the occurrence of bonding defects between the first substrate 110 and the second substrate 115 be reduced, but at the same time, the bezel width of the display device can be reduced to below a certain level.

In addition, in the area where the seal area and the non-display area (NDA) overlap, the occurrence of corrosion/corrosion of the first metal layer (M1) and the second metal layer (M2) due to damage to the bridge electrode (BRL) at the bottom of the sealant is minimized. As a result, a more robust display panel can be provided.

In addition, in reducing the bezel width of the display device, avoidance design of the seal-area and bridge area (BRA) and bonding of the first substrate 110 and the second substrate 115 without a separate process or addition of a new mask are performed. It is possible to provide a display panel that can reduce the occurrence of defects and corrosion/corrosion of wiring.

Additionally, in order to lower the resistance of the touch wires (RVcom_1, RVcom_2, RVcom_3), the touch wires (RVcom_1, RVcom_2, RVcom_3) are arranged as closely as possible, and the touch wires (RVcom_1, RVcom_2, RVcom_3) are overlapped in multiple layers. Then, electrically connect the touch wires (RVcom_2, RVcom_3) on the upper floor to the touch wires (RVcom_1, RVcom_3) on the lower floor. This has the effect of reducing the resistance of each touch wire (RVcom_1, RVcom_2, RVcom_3) while making it possible to narrow the bezel width.

In addition, the upper dam (U_DM) and the lower dam (L_DM) are arranged to prevent the sealant from spreading in the display area (DA) direction (D1), so that the sealant and the upper alignment layer (U_AL), or the sealant and the lower alignment layer (L_AL) ) can provide a display panel that does not overlap.

In addition, the overlap prevention area (OA) is placed across the boundary between the touch wiring area (RVcomA) and the gate driver (GIP), or the gate driver (GIP) is placed based on the boundary between the touch wiring area (RVcomA) and the gate driver (GIP). By designing the display panel to be disposed biased toward the side, it is possible to provide a display panel in which the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL) do not overlap.

In addition, by not overlapping the sealant and the upper alignment layer (U_AL) or the sealant and the lower alignment layer (L_AL), it is possible to prevent the bonding strength of the first substrate 110 and the second substrate 115 from decreasing. there is.

In addition, as the adhesive area of the sealant increases as the sealant spreads and fills the curves of the trench T, the adhesive strength of the sealant is improved, and the bond between the first substrate 110 and the second substrate 115 is improved. The cementation strength may increase.

In addition, even if the sealant spreads in the display area (DA) direction (D1), as the spread sealant fills the trench (T), the spread width of the sealant decreases, causing the sealant and the lower alignment layer (L_AL) to overlap. can be minimized.

In addition, the overlapping phenomenon between the sealant and the lower alignment layer (L_AL) is minimized by the trench (T), thereby preventing a decrease in the bonding strength of the first substrate 110 and the second substrate 115 due to the sealant. can do.

In addition, as the sealant spreads in the display area (DA) direction (D1), the trench (T) primarily acts as a pool to receive the sealant, and secondarily, the upper dam (U_DM) and lower dam (L_DM) ) can act as a barrier to prevent the sealant from flowing into the touch wiring area (RVcomA).

In addition, by allowing a certain amount of sealant to leak out through the gap created by the upper dam (U_DM) and lower dam (L_DM), the sealant can be prevented from bursting during cementation.

In addition, as the sealant flows through gaps avoiding the upper dam (U_DM) and lower dam (L_DM), the flow rate decreases, thereby preventing the sealant from ultimately exceeding the overlap prevention area (OA).

In addition, as the area in contact with the sealant increases with the trench (T), the adhesive strength of the sealant increases, and the trench (T) provides a space where the sealant can stay without exceeding the overlap prevention area (OA). The spread width of the sealant can be controlled.

In addition, the path of the trench T can be made longer by the plurality of trenches T crossing the solid or dotted upper dam U_DM and lower dam L_DM diagonally rather than perpendicular to them. By making the path of the trench (T) longer, it is possible to increase the space where the sealant can stay without crossing the overlap prevention area (OA).

A display device according to various exemplary embodiments of the present invention may be described as follows.

A display device divided into a display area for displaying an image and a non-display area around the display area according to an embodiment of the present invention, comprising: a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween; a sealant disposed in a non-display area between the first and second substrates so that the first and second substrates are bonded to each other; An upper and lower alignment layer disposed facing each other in the display area between the first and second substrates, which are positions that determine the initial alignment direction of the liquid crystal of the liquid crystal layer; A gate link unit, gate driver, and touch wiring area arranged in a non-display area; an overlap prevention area including a lower dam rising from the first substrate toward the second substrate and an upper dam extending from the second substrate toward the first substrate; and a trench region including a plurality of trenches through which the sealant flows. At this time, the overlap prevention area and the trench area are disposed adjacent to the boundary of the touch wiring area and the gate driver and overlap each other.

In addition, in the display device according to an embodiment of the present invention, a touch wiring area, a gate driver, and a gate link unit are sequentially arranged from the end of the display area toward the outside of the display device, and the trench area is an area between the touch wiring area and the gate driver. It is characterized by being arranged biased toward the gate driver based on the boundary.

In addition, in the display device according to an embodiment of the present invention, a touch wiring area, a gate driver, and a gate link are sequentially arranged from the end of the display area toward the outside of the display device, and the overlap prevention area is a touch wiring area and a gate driver. It is characterized by being placed across the border of.

In addition, the display device according to an embodiment of the present invention includes a plurality of first touch wires composed of a second metal layer in the touch wire area, an insulating planarization layer disposed on the first touch wire, and a first touch wire on the planarization layer. A plurality of second touch wires composed of a third metal layer are further disposed in a shape that overlaps the wire, and the first touch wire and the second touch wire corresponding to the first touch wire are formed by contact holes disposed in the planarization layer. They are connected to each other, and the trenches include contact holes arranged in the planarization layer and grooves formed in the planarization layer separately, so that they do not overlap with the touch wiring area, and the upper dam and lower dam are located on the touch wiring, thereby creating an overlap prevention area. and the touch wiring area partially overlap.

In addition, in the display device according to an embodiment of the present invention, the trench is primarily placed at a position to receive the spread of the sealant, and the upper dam and lower dam prevent the spread of the sealant from flowing into the touch wiring area. It is characterized by being placed secondarily in the location.

Additionally, the display device according to an embodiment of the present invention is characterized in that the aperture ratio of the touch wiring area is 20% or less.

In addition, the display device according to an embodiment of the present invention is characterized in that the lower dam is made of either polyimide or photo acryl.

Additionally, the display device according to an embodiment of the present invention is characterized in that the sealant is disposed in an area where the aperture ratio is 50% or more among the non-display area.

In addition, the display device according to an embodiment of the present invention is characterized in that the touch wiring area belongs to an area with an aperture ratio of less than 50% among the non-display areas.

In addition, in the display device according to an embodiment of the present invention, the second substrate includes a black matrix and a color filter layer that separate light blocking areas and opening areas in a plurality of pixels, and an overcoating layer that covers and flattens the black matrix and the color filter layer, , the first substrate has a thin film transistor, a planarization layer disposed to cover the thin film transistor, and a plurality of upper spacers disposed on the overcoating layer of the second substrate in the display area between the first substrate and the second substrate; and a plurality of lower spacers disposed on the planarization layer of the first substrate in the display area between the first substrate and the second substrate. At this time, the upper spacer is placed in the light-shielding area where the black matrix is disposed, and the lower spacer maintains the cell gap or is spaced with the upper spacer to minimize the phenomenon of the cell gap being reduced below a certain value even if the cell gap is momentarily reduced. They are arranged opposite each other, and the lower dam is made of the same material as the lower spacer, and the upper dam is made of the same material as the upper spacer.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam are arranged in a solid line or dotted line along the area between the area where the sealant is applied and the lower alignment film by overlapping each other, and the path of the trench is long. , the trench is not perpendicular to the upper dam and the lower dam, but is arranged to intersect obliquely.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam are arranged in a solid line or dotted line along the area between the area where the sealant is applied by overlapping each other and the lower alignment film, and the sealant flowing into the trench The trench is arranged in a V shape so that the spreading direction is bent.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam are arranged in a solid line or dotted line along the area between the area where the sealant is applied and the lower alignment film while alternating with each other, so that a certain amount of sealant is applied. It is characterized by a gap through which leakage can occur.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam overlap each other and are arranged in a solid line or dotted line along the seal-region and the alignment film, and the overlapping upper dam and lower dam are When there are a plurality of pairs of an upper dam and a lower dam, the closer the pair is to the area where the sealant is applied, the greater the separation distance between the upper dam and the lower dam.

Additionally, the display device according to an embodiment of the present invention is characterized in that the sealant is a photocuring sealant.

In another aspect, a display device divided into a display area for displaying an image and a non-display area around the display area according to an embodiment of the present invention, comprising: a first substrate; UV curing slant placed around the outside of the display device; an alignment film surrounded by a UV cured sealant; It is characterized in that it includes a first structure disposed at a position to prevent overlap of the UV curing sealant and the alignment layer in the non-display area to minimize the bezel width of the display device.

Additionally, the display device according to an embodiment of the present invention further includes a gate link unit, a gate driver, and a touch wiring area disposed in a non-display area. At this time, the first structure is characterized as a lower dam.

Additionally, the display device according to an embodiment of the present invention is characterized in that the lower dam is disposed across the boundary between the touch wiring area and the gate driver.

Additionally, the display device according to an embodiment of the present invention further includes a gate link unit, a gate driver, and a touch wiring area disposed in a non-display area. At this time, the first structure is characterized as a trench.

Additionally, the display device according to an embodiment of the present invention is characterized in that the trench is disposed with a bias toward the gate driver based on the boundary between the touch wiring area and the gate driver.

Although various embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. there is. Accordingly, the various embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the various embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

10: Display device 100, 200, 300, 400: Display panel
110: first substrate 115: second substrate
120: middle layer 121: gate insulating layer
122: Flattening layer 122_s: Sub-flattening layer
123: Insulating layer 130: Thin film transistor
131: gate electrode 132: active layer
133: first electrode 134: second electrode
140: common electrode 150: pixel electrode
BM: Black matrix OC: Over coating layer
U_SP: Upper spacer L_SP: Lower spacer
G_Link: Gate link GIP: Gate driver
D_LL: Data link wiring CL: Connection wiring
GL: Gate line DL: Data line
ST: Stage LC: Liquid crystal layer
DA: Display area NDA: Non-display area
BRA: Bridge area BRL: Bridge electrode
PAD: Pad section D_Link: Data link section
CLK1, CLK2, CLK3, CLK4: Clock signal Seal: Seal-area
G_Pad: Gate pad part D_Pad: Data pad part
S_In: Signal input terminal CF1, CF2, CF3: Color filter
CF: Color filter layer PAS, PAS1, PAS2: Passivation layer
M1: first metal layer M2: second metal layer
M2_s: second sub-metal layer M3: third metal layer
OA: Overlap prevention area TA: Trench area
T: Trench P: Pixel
D1: Display area direction D2: Non-display area direction
U_DM: Upper dam L_DM: Lower dam
U_AL: Upper alignment layer L_AL: Lower alignment layer
RVcomA: Touch wiring area RVcom_1: First touch wiring (RVcom_1)
RVcom_2: 2nd touch wire (RVcom_2) RVcom_3: 3rd touch wire (RVcom_3)

Claims (17)

A display device comprising a display area for displaying an image and a non-display area around the display area,
an upper substrate and a lower substrate facing the upper substrate;
a black matrix and color filter layer disposed below the upper substrate;
An over coating layer disposed below the black matrix and color filter layer;
an upper alignment layer disposed below the overcoating layer;
a lower alignment layer disposed on the lower substrate;
In the display area, a plurality of pixels, a plurality of gate lines, and a plurality of data lines arranged on the lower substrate;
In the non-display area, a gate driver and a gate link unit disposed on the lower substrate;
a sealant disposed between the lower substrate and the upper substrate in the non-display area;
a plurality of upper spacers disposed below the overcoating layer; and
It includes a plurality of lower spacers disposed to overlap the upper spacer, the plurality of gate lines, and the plurality of data lines,
The gate link unit includes an external signal wire, a connection wire, and a bridge electrode,
The connection wiring includes at least two layers,
A portion of the connection wire overlaps the sealant. According to claim 1,
A display device further comprising a trench area where a plurality of trenches are disposed. According to clause 2,
Each of the sealant and the lower alignment layer fills at least one of the plurality of trenches. According to claim 1,
A display device wherein at least one insulating layer is formed between the external signal wire and the connection wire. According to clause 4,
An insulating layer is formed on the external signal wire and the connection wire,
The insulating layer includes a contact hole exposing a contact area of each of the external signal wire and the connection wire,
The bridge electrode is simultaneously in contact with the contact area of the external signal wire and the contact area of the connection wire. According to clause 5,
At least one of the plurality of lower spacers covers the bridge electrode and fills the contact hole. According to claim 1,
Each of the plurality of pixels includes a transistor and a first electrode electrically connected to the transistor,
A display device wherein the transistor includes a gate electrode, an active layer, and source/drain electrodes. According to clause 7,
The bridge electrode is formed of the same material as the first electrode. According to clause 7,
The connection wiring includes a lower wiring and an upper wiring formed on the lower wiring,
The lower wiring is formed of the same material as the active layer,
The display device wherein the upper wiring is formed of the same material as the source/drain electrodes. According to clause 9,
The display device wherein the upper wiring exposes an end of the lower wiring. According to claim 1,
In the non-display area, a portion of the black matrix and overcoating layer overlaps the gate driver. According to claim 1,
A display device, wherein an area of at least one of the plurality of lower spacers is different from an area of the other one. According to claim 1,
In the non-display area, a portion of the black matrix and the overcoating layer overlap the gate driver. According to claim 1,
In the non-display area, a portion of the black matrix and the overcoating layer overlap the gate driver. According to claim 1,
The black matrix has an opening,
The display device wherein the opening overlaps the gate link portion. According to claim 1,
The sealant overlaps the black matrix and the overcoating layer. According to claim 1,
The upper alignment layer and the lower alignment layer are spaced apart from the sealant.