KR102596850B1 - Narrow bezel display device - Google Patents

Abstract

The display device includes a lower substrate divided into a display area and a non-display area, and an upper substrate that corresponds to the lower substrate and includes a black mattress (BM). In addition, the display device is located on the non-display area, and in the direction away from one side of the display area, a GIP driver, a plurality of signal transmission wires, connection wires connecting the GIP driver and a plurality of signal transmission wires, and a sealant are installed. A bezel including a seal area, located on the non-display area, and a plurality of bridges that electrically connect the GIP driver and the connection wiring and the connection wiring and a plurality of signal transmission wires. It includes a pattern and a plurality of shield patterns surrounding each of the plurality of bridge patterns. Multiple shield patterns minimize the area where the sealant and multiple bridge patterns are in direct contact.

Description

Narrow bezel display device {NARROW BEZEL DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, the sealant that bonds the upper and lower substrates can be arranged to extend to the signal wiring area or the GIP (Gate In Panel) driver, thereby forming a bezel. This relates to a display device that can reduce the width.

Display devices include liquid crystal displays and organic electroluminescent displays that include an upper substrate, a lower substrate, and a liquid crystal layer or organic light emitting element formed between the two substrates. A liquid crystal display device is a device that displays images by adjusting the arrangement of the liquid crystal layer depending on whether an electric field is applied and the light transmittance is adjusted accordingly.

Typically, organic electroluminescent displays (OLEDs) are classified into passive matrix OLEDs (PMOLEDs) and active matrix OLEDs (AMOLEDs) depending on the method of driving the organic light emitting elements.

The AMOLED includes a plurality of gate electrode lines, a plurality of data lines, a plurality of power lines, and a plurality of pixels connected to the lines and arranged in a matrix form. In addition, each pixel includes an organic light-emitting element composed of an organic light-emitting layer between an anode and a cathode, and a pixel circuit that independently drives the OLED. The pixel circuit mainly includes a switching transistor for transmitting a data signal, a driving transistor for driving the EL element according to the data signal, and a capacitor for maintaining the data voltage. The switching transistor charges the data voltage to the capacitor in response to the scan pulse. The driving transistor is a device that controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

A sealant is applied to a seal area located in a non-display area (bezel area) corresponding to the outer periphery of the display area of the display device, and the upper substrate and lower substrate are bonded.

Recently, efforts have been made to reduce the bezel width of display devices in order to meet the diverse needs of users and improve aesthetics. As the bezel width in display devices continues to decrease, the size of the seal area for bonding the upper and lower substrates of the display device must also be reduced. However, as the width of the seal area decreases, the adhesive force between the upper and lower substrates also decreases.

In order to implement a narrower bezel width and at the same time strengthen the adhesive force between the upper and lower substrates, the sealant is sometimes arranged to extend to the top of the external signal wiring formed in the non-display area of the panel or even to the top of the gate driver. However, since some areas of the circuit in these non-display areas may be made of a material that has poor adhesion to the sealant, even if the sealant extends to the circuit area, poor adhesion between the upper and lower substrates may occur due to weakened adhesion. You can. Additionally, the circuit part overlapping with the sealant is prone to damage by external force applied to the panel. In this case, foreign substances penetrate through the damaged area, causing problems such as corrosion/corrosion of metal wiring. For example, among the circuit areas overlapped with the sealant, the area formed of ITO not only has poor adhesion to the sealant, but is also vulnerable to cracks due to external forces. As the area formed of ITO increases among the areas overlapping with the sealant, it causes poor adhesion of the panel, and when cracks occur in the ITO area, a penetration path for external contaminants such as moisture and salt is formed, leading to corrosion/corrosion of the wiring of the panel. It causes defects.

Ultimately, the seal area must be designed to avoid areas that have poor adhesion to the sealant or areas that are prone to damage from external forces transmitted to the sealant, so the bezel can be reduced by overlapping the seal area and the circuit part. There is a limit to what you can do.

The present invention is intended to solve the above-described conventional problems. In the area where the seal area and the circuit part overlap, the sealant can have more improved adhesion compared to the existing structure, thereby preventing defective adhesion between the upper and lower substrates. The purpose is to provide a display device that can reduce the occurrence of and at the same time reduce the bezel width below a certain level.

In addition, the purpose is to provide a display device that can reduce the bezel width below a certain level by reducing the occurrence of metal corrosion/corrosion due to damage to the circuit under the sealant in the area where the seal area and the circuit part overlap.

In addition, in reducing the bezel width of the display device, design to avoid the seal area and specific circuit area, and without adding a separate independent process or mask, can cause damage due to poor adhesion of the upper and lower substrates and damage to the circuit under the sealant. The purpose is to provide a display device with a high degree of design/process freedom by providing a structure that can reduce the occurrence of metal corrosion/corrosion.

In order to achieve the above object, a display device according to an embodiment of the present invention includes a lower substrate divided into a display area and a non-display area, an upper substrate having a black mattress (BM), and a non-display area. Located on the top, in the direction away from one side of the display area, a seal area equipped with a GIP driver, a plurality of signal transmission wires, connection wires connecting the GIP driver and a plurality of signal transmission wires, and a sealant. A bezel including a bezel, located on the non-display area, a plurality of bridge patterns that electrically connect the GIP driver and the connection wiring and the connection wiring and a plurality of signal transmission wires, and a plurality of bridge patterns, respectively. It includes a plurality of shield patterns surrounding the , and the plurality of shield patterns minimize the area where the sealant and the plurality of bridge patterns directly contact.

In order to achieve the above object, a liquid crystal display device according to another embodiment of the present invention includes an upper substrate and a lower substrate arranged to face each other with liquid crystal interposed, a plurality of upper spacers provided on the upper substrate, and a plurality of upper spacers provided on the lower substrate. a lower spacer, a gate link part in which a plurality of external signal wires are arranged, a GIP driving part equipped with a shift register, a plurality of bridge areas electrically connecting a plurality of external signal wires and the GIP driving part, and a part of the gate link part and the GIP driving part. The sealant provided in the overlapping seal area, and each of the plurality of bridge areas is disposed on the first contact hole where the first metal layer is exposed and the second contact hole where the second metal layer is exposed, so as to form the first contact hole and the second contact hole. It includes a bridge electrode connecting the first metal layer and the second metal layer through a contact hole, wherein a portion of the plurality of lower spacers is disposed at a position corresponding to the upper spacer, and another portion of the plurality of lower spacers is in one of the plurality of bridge regions. It is placed overlapping with at least one bridge area.

In order to achieve the above object, an organic light emitting display device according to another embodiment of the present invention is located on a substrate including a display area and a non-display area on which a plurality of pixels equipped with organic light emitting elements are arranged, and a non-display area. In the direction away from one side of the display area, a bezel includes a GIP driver, a plurality of signal transmission wires, connection wires connecting the GIP driver and a plurality of signal transmission wires, and a seal area equipped with a sealant. , located on the non-display area, a plurality of bridge patterns that electrically connect the GIP driver and the connection wiring and the connection wiring and a plurality of signal transmission wires, and a plurality of shields surrounding each of the plurality of bridge patterns ( Shield) pattern.

1 is a schematic plan view of a display device according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view of a pixel located in the display area of a display device according to an embodiment of the present invention.
Figure 3 is a plan view showing an enlarged portion of a non-display area of a display device according to an embodiment of the present invention.
FIG. 4A is a cross-sectional view of a corresponding portion along a line extending from A to A' shown in FIG. 3.
FIG. 4B is a cross-sectional view of a corresponding portion along a line extending from A to A' shown in FIG. 3 according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of a pixel located in a display area of the display device according to an embodiment of the present invention.

Referring to FIGS. 1 and 2 , the display device includes a display panel 100 including a plurality of pixels (P) that output light. When the display panel 100 is implemented as a liquid crystal panel, the display panel 100 includes a first substrate 110 (upper substrate or lower substrate) and a second substrate 115 ( It consists of a structure filled with liquid crystal (LC) between the upper or lower substrates. At this time, one of the first substrate 110 and the second substrate 115 is a TFT array substrate on which a plurality of thin film transistors (TFTs) are formed, and the other substrate corresponds to a plurality of pixels (P). Preferably, it may be a color filter substrate on which a color filter (CF) is formed. Additionally, a color filter (CF) and a TFT array may be provided simultaneously on one of the first substrate 110 and the second substrate 115. At least one of the first and second substrates is provided with a common electrode 140 and a pixel electrode 150, and a vertical or horizontal electric field generated by the difference in voltage applied to each electrode is positioned between the two substrates. It is driven by controlling the direction of liquid crystal (LC). Additionally, the display device includes a backlight device disposed below the liquid crystal panel and used as a light source, and a driving circuit located outside the liquid crystal panel to drive the liquid crystal panel. The driving circuit part is located in the non-display area (NDA), and is connected to the gate pad part (G_Pad) formed on one side of the liquid crystal panel, and the GIP driving part (GIP-DP) and non-display area (NDA) are involved in driving the liquid crystal panel. It is located in and includes a data driver (not shown) connected to a data pad portion (D-Pad) formed on one side of the liquid crystal panel. Data drivers can be implemented on a printed circuit board (PCB).

Referring to FIGS. 1 and 2 , a plurality of gate lines (GL) and data lines (DL) are arranged to intersect each other in the display area (DA) of the first substrate 110, and the gate lines (GL) and data lines A thin film transistor 130 is provided in each pixel (P) defined by the intersection of (DL). For example, in the display panel 100, N gate lines (GL) and M data lines (DL) may intersect to form MxN pixels (P). However, in some embodiments of the display panel 100, adjacent pixels may be designed in a structure in which they share the gate line (GL) or data line (DL), so a larger number of pixels (P) than MxN may be provided. It may be possible. The thin film transistor 130 provided in each pixel (P) is connected to the gate line (GL) and the data line (DL) and is switched according to the gate signal applied from the gate line (GL). A data signal is supplied to the pixel electrode 150. The pixel electrode 150 is connected to the thin film transistor 130 and generates an electric field according to the data signal supplied from the thin film transistor 130 to rearrange the liquid crystals of the liquid crystal layer LC.

In Figure 2, only red pixels, green pixels, and blue pixels are shown for convenience of explanation. The thin film transistor (TFT) formed in each pixel (R, G, B) is formed on the first substrate 110, the gate electrode 131, the active layer 132, the first electrode 134, and the second electrode ( 133). Specifically, a gate electrode 131 electrically connected to the gate line GL is formed on the first substrate 110, and a gate insulating layer 121 is formed on the gate electrode 131. An active layer 132 in which a channel is formed is formed on the gate insulating layer 121, and a first electrode 134 electrically connected to the data line DL and a pixel electrode 150 are formed on the active layer 132. A second electrode 133 connected to is formed. The active layer 132 may be formed of amorphous silicon, polycrystalline silicon, oxide semiconductor, etc.

A planarization layer 122 is formed to cover the thin film transistor 130 on the first substrate 110 to form a flat surface on the thin film transistor 130. The planarization layer 122 may be formed of an organic insulating material such as photo-acryl (PAC). Although not shown in FIG. 2, a separate passivation film (PAS) may be provided between the thin film transistor 130 and the planarization layer 122. The passivation film provided between the thin film transistor 130 and the planarization layer 122 may be a silicon-based inorganic material.

A common electrode 140 is formed on the planarization layer 122. The common electrode 140 drives the liquid crystal by forming an electric field in response to the pixel electrode 150. In Figure 2, since the pixel electrode 150 shows a portion electrically connected to the second electrode 133 of the thin film transistor 130 through a contact hole, the common electrode 140 is shown separately for each pixel. However, the common electrode 140 is provided across a plurality of pixels (P) in a single pattern connected in areas excluding the area where the pixel electrode 150 and the thin film transistor 130 are connected through contact holes. The common electrode 140 may be electrically connected to the common electrode line through a separate contact hole.

Additionally, the common electrode 140 may be divided into a plurality of common electrode blocks (not shown), and may be configured in a structure where a plurality of pixels (P) share one common electrode block. In this case, the display panel 100 capable of touch recognition can be implemented by time-dividing one frame period of the screen and applying a signal for detecting a touch input to a common electrode line in one section. Each common electrode block may be connected to an individual common electrode line that extends to at least partially overlap the gate line (GL) or the data line (DL). The common electrode 140 may be disposed below the thin film transistor 130. When the common electrode 140 is disposed below the thin film transistor 130, additional planarization is provided between the common electrode 140 and the thin film transistor 130, which is different from the planarization layer 122 formed on the top of the thin film transistor 130. A layer may be provided. For example, a plurality of common electrodes 140 are formed on the first substrate 110, a silicon-based planarization layer (Silicon on Glass: SOG) is formed on the top, and a thin film transistor 130 is formed on the top. can be formed.

An insulating layer 123 is formed between the common electrode 140 and the pixel electrode 150 to insulate the two electrodes. The insulating layer 123 protects the common electrode 140 and simultaneously flattens the top of the common electrode 140. The insulating layer 123 may be formed of the same material as the planarization layer 122, or may be formed of an insulating material different from the planarization layer 122.

The pixel electrode 150 is electrically connected to the second electrode 133 of the thin film transistor 130 through a contact hole formed in the planarization layer 122 and the insulating layer 123. The pixel electrode 150 and the common electrode 140 may be formed of a transparent conductive material (e.g., ITO), and the pixel electrode 150 may have a plurality of slits (Slit) to form a horizontal electric field with the common electrode 140. ) can be formed. However, the structure and arrangement relationship between the common electrode 140 and the pixel electrode 150 are not limited to this. Accordingly, in some embodiments, the common electrode 140 may be disposed on top of the pixel electrode 150, or the pixel electrode 150 and the common electrode 140 may be disposed on the same layer. Additionally, in some embodiments, the common electrode 140 may be formed to have a plurality of slits instead of the pixel electrode 150.

In the embodiment shown in FIG. 2, the second substrate 115 disposed opposite to the above-described first substrate 110 is a color filter substrate of the display panel 100, and provides a light blocking area and a plurality of pixels P. A black matrix (BM) and a color filter layer (CF) defining the opening area are provided. The area where the black matrix (BM) is formed is defined as a light blocking area, and the area where the black matrix (BM) is not formed is defined as an opening area. Various driving elements and wiring, such as the thin film transistor 130, data line (DL), and gate line (GL), are formed in the light blocking area by the black matrix (BM), and the pixel electrode 150 is formed in the area defined as the opening area. and a common electrode 140 are formed. Since FIG. 2 shows a cross section cut along the gate line GL of the display panel 100, the black matrix BM is continuously extended. However, in the opening area, the black matrix BM is disposed between two adjacent pixels to block the data line DL, thin film transistor 130, or components that reflect external light below it.

A color filter layer (CF) is formed on the second substrate 115 to correspond to the pixels of the display panel 100. Specifically, color filters CF1, CF2, and CF3 are formed to correspond to the opening areas of the red pixel, green pixel, and blue pixel, respectively. Some areas of each of the color filters CF1, CF2, and CF3 may overlap with the black matrix BM. In the embodiment shown in FIG. 2, the black matrix BM is disposed closer to the second substrate 115 than the color filters. However, in some other embodiments, in order to reduce light leakage between adjacent pixels P, the color filters CF1, CF2, and CF3 are formed closer to the second substrate 115, and the black matrix BM is formed as a color filter. It may be formed on the surface of the filter layer (CF). Here, the surface of the color filter layer (CF) refers to a surface that faces the first substrate 110 and is close to the first substrate 110 among the surfaces of the color filter layer (CF).

An over coating layer (OC) is formed on the second substrate 115 to cover the black matrix (BM) and the color filter layer (CF). The overcoating layer (OC) is a layer for providing a flat surface on the side opposite the first substrate 110 from the second substrate 115 on which the black matrix (BM) and the color filter layer (CF) are formed, and the planarization layer 122 It may be formed of the same material as.

Referring to FIG. 2, a spacer is provided between the first substrate 110 and the second substrate 115 to maintain a constant distance between the two substrates. When the display panel 100 receives an external force, the spacers move in various directions.

At this time, the moving spacer may damage the alignment film provided on the surface of the substrate facing the liquid crystal layer LC, and as a result, light leaks due to unintended distortion of the liquid crystal arrangement. The light leaking in this way causes light leakage defects that appear reddish, greenish, or bluish depending on the location of the spacer in the black image of the display panel 100. It can cause it.

In order to reduce light leakage due to movement of the above-mentioned spacer, the size of the black matrix (BM) may be designed to be enlarged based on the formation position of the spacer, but this becomes a factor that makes it difficult to implement high resolution and high aperture ratio in the display panel. Accordingly, in the display panel 100 of the present invention, a plurality of spacers are provided on each of the first substrate 110 and the second substrate 115.

Referring to FIG. 2 , a plurality of upper spacers U_SP are disposed between the first substrate 110 and the second substrate 115 on the overcoating layer OC of the second substrate. The upper spacer (U_SP) is formed in the light blocking area where the black matrix (BM) is formed. In addition, between the first substrate 110 and the second substrate 115, the upper surface of the insulating layer 123 of the first substrate 110 has a lower surface to correspond to the upper spacer (U_SP) provided on the second substrate 115. A spacer (L_SP) is placed.

Some of the plurality of spacers provided on each of the first substrate 110 and the second substrate 115 may be formed to have a longer or shorter height than other spacers. For example, as shown in FIG. 2, some of the upper spacers (U_SP) may be formed to have a longer height than other upper spacers (U_SP). That is, the distance between some upper spacers (U_SP) and the corresponding lower spacers (L_SP) may be shorter than the distance between other upper spacers (U_SP) and the corresponding lower spacers (L_SP).

Likewise, some of the lower spacers (L_SP) may also be formed to have a longer height than other lower spacers (L_SP). The upper spacer (U_SP), which is formed to have a longer height than other spacers, maintains the cell gap of the display panel 100. For example, the height of each of the lower spacer (L_SP) and the upper spacer (U_SP) for maintaining the cell gap between the first substrate 110 and the second substrate 115 is equal to the upper surface of the lower spacer (L_SP) The lower surfaces of the upper spacers (U_SP) may be formed at a height where they can be in contact with each other.

A spacer formed at a shorter height than other spacers formed on the same substrate and placed at a wider distance from the corresponding spacer on the opposite substrate maintains the flexibility of the display panel 100 when external pressure is applied to the display panel 100. At the same time, it serves to prevent the distance between the two substrates from getting closer than a certain distance.

Additionally, the upper spacer (U_SP) and lower spacer (L_SP) are implemented in the form of a bar. The bar-shaped upper spacer (U_SP) and lower spacer (L_SP) may be formed in a light blocking area by the black matrix (BM) disposed along the gate line (GL). The upper spacer (U_SP) overlaps the gate line (GL) and is formed to extend in the same direction as the extension direction of the gate line (GL). The lower spacer (L_SP) formed at a position corresponding to the upper spacer (U_SP) overlaps the data line (DL) on the first substrate 110 and extends in the same direction as the extension direction of the data line (DL).

The upper spacer (U_SP) may be formed to extend along the gate line (GL) within a range that does not pass through the contact holes of the two adjacent pixels (P). However, the length of the upper spacer (U_SP) is not limited to this, and may be formed to extend along the gate line (GL) to pass through the contact holes of a plurality of pixels.

The upper spacer (U_SP) and the lower spacer (L_SP) are formed in a light blocking area by the black matrix (BM) disposed along the gate line (GL).

The upper spacer (U_SP) extends in the same direction as the extension direction of the data line (DL) and overlaps the data line (DL). The lower spacer (L_SP) formed at a position corresponding to the upper spacer (U_SP) extends in the same direction as the extending direction of the gate line (GL) on the first substrate 110 and overlaps the gate line (GL). When the upper spacer (U_SP) is moved by external pressure and positioned at the top of the contact hole, the upper spacer (U_SP) may not return to its original position even after the external pressure on the display panel 100 disappears. Therefore, to prevent the upper spacer (U_SP) from falling into the contact hole, the length of the upper spacer (U_SP) can be made longer than the width of the contact hole.

Alternatively, the lower spacer L_SP may be formed to extend further along the gate line GL to cover a plurality of contact holes. A lower spacer (L_SP) may be formed on the front surface along the gate line (GL). When the lower spacer (L_SP) is formed on the front surface of the gate line (GL), it may become difficult to optimize the amount of liquid crystal layer (LC) between the first and second substrates. Accordingly, the lower spacer (L_SP) may be formed to cover only a certain number of contact holes adjacent to each other. For example, the lower spacer L_SP may be formed to have a length that covers only two adjacent contact holes.

The upper spacer (U_SP) and lower spacer (L_SP) may be formed in a circular shape, different from the bar shape. The upper spacer (U_SP) and the lower spacer (L_SP) are formed in a light blocking area by the black matrix (BM) disposed along the gate line (GL). The upper spacer (U_SP) is formed in a cone shape from the second substrate 115 toward the first substrate side 110. The lower spacer (L_SP) opposite to the upper spacer (U_SP) extends in the same direction as the extension direction of the gate line (GL) on the first substrate 110 and overlaps the gate line (GL). At this time, a portion of the lower spacer (L_SP) corresponding to the upper spacer (U_SP) may have a circular shape with a diameter larger than that of the upper spacer (U_SP). Additionally, the lower spacer L_SP may be formed to cover the contact holes of a plurality of pixels along the gate line GL or to cover only the contact holes of two pixels adjacent to each other.

The upper spacer (U_SP) and the lower spacer (L_SP) may be formed of an organic material or an inorganic material. However, in terms of controlling the height and shape of the spacer, it may be relatively easier to form the upper spacer (U_SP) and lower spacer (L_SP) from an organic material. For example, the upper spacer (U_SP) and the lower spacer (L_SP) may be formed of an organic material such as photo acryl (PAC) or polyimide (PI). In order to secure the separation distance between the upper spacer (U_SP) and the alignment layer on the second substrate 115, the height of the lower spacer (L_SP) may be 4000A or higher.

According to the above-described structure of the upper spacer (U_SP) and lower spacer (L_SP) and the arrangement between the two spacers, the upper spacer (U_SP) and lower spacer (L_SP) are prevented from contacting the alignment film even when an external force is applied to the display panel 100. By doing so, light leakage defects due to damage to the alignment film can be prevented. Accordingly, the size of the black matrix (BM), which was set to reduce image quality problems due to poor light leakage, can be reduced, and the display panel 100 with a more improved aperture ratio and higher resolution can be implemented.

Referring to FIG. 1, the narrow bezel display device according to an embodiment of the present invention includes a pad portion (PAD), a data link portion (D_Link), and a gate link portion in the non-display area (NDA) of the first substrate 110. (G_Link), connection wiring (CL), bridge area (BRA), shield pattern, seal area, and GIP driving part (GIP-DP) are provided.

The pad portion (PAD) includes a data pad portion (D_Pad) and a gate pad portion (G_Pad). The gate pad part (G_Pad) is formed on one side of the data pad part (D_Pad) and is connected to an external driving circuit part. The data pad portion D_Pad may be formed on one side of the non-display area NDA of the first substrate 110 and connected to an external driving circuit portion (not shown). Additionally, a data driver with an integrated circuit (IC) structure may be provided in the data pad portion (D_Pad) by directly connecting to the first substrate 110 in a chip-on-glass (COG) method.

In addition to the data pad part (D_Pad) and gate pad part (G_Pad) described above, the pad part (PAD) includes input and output of signals necessary to drive the pixel (P) of the display panel 100 or implement various other additional functions. Pads may be provided for. For example, a common voltage pad connected to the common voltage generator of the driving circuit part or a touch sensor pad connected to a touch driver for performing a touch recognition function of the display panel may be provided. The location of each pad part described above is not limited to the upper side of the non-display area (NDA) as shown in FIG. 1, but may be provided on another side of the non-display area (NDA) or on multiple sides.

The data link unit (D_Link) is provided with a data link wire (D_LL) that extends between the data line (DL) disposed in the display area (DA) and the data pad unit (D_Pad) and electrically connects them to each other.

The gate link unit (G_Link) is provided with signal transmission wires through which external signals are supplied to drive the GIP driver unit (GIP-DP). For example, as shown in Figure 1, a gate start signal (VST), a plurality of clock signals (CLK1, CLK2, CLK3, CLK4), a reset signal (RESET), a plurality of voltages (VSS, VDD, VDD1), etc. A plurality of signal transmission wires that transmit may be provided in the gate link unit (G_Link). One of the plurality of signal transmission wires of the gate link unit (G_Link) may be made of the same material as the gate electrode of the thin film transistor 130.

The connection wire (CL) connects each signal transmission wire of the gate link unit (G_Link) electrically connected to the gate pad unit (G_Pad) and the GIP driver unit (GIP-DP). Therefore, in the non-display area (NDA), each signal transmission wire of the gate link unit (G_Link) and the connection wire (CL) are contacted, and the connection wire (CL) and the GIP driving unit (GIP-DP) are contacted. The connection wiring CL may be made of the same material as the source/drain of the thin film transistor 130.

The GIP driver (GIP-DP) is gated-in by thin film transistors formed in the non-display area (NDA) of the first substrate 110 during the process of forming the thin film transistor 130 of the pixel P described above. It is composed of a panel (Gate-In-Panel; GIP) method. The GIP driver (GIP-DP) generates a gate signal and sequentially supplies it to the gate lines (GL) arranged in the display area (DA). For this purpose, the GIP driving unit (GIP-DP) is provided with a plurality of stages (ST) connected to each gate line (GL). Accordingly, each external signal wire of the gate link unit (G_Link) is selectively connected to the stages (ST) of the GIP driving unit (GIP-DP) through the connection wire (CL).

Each of the plurality of stages (ST) responds to the gate start signal (VST) or the gate start signal supplied from the previous stage, and sends any one of the plurality of clock signals (CLK1, CLK2, CLK3, CLK4) to the gate signal. and supplies it to the gate line (GL). Each of these plural stages (ST) operates sequentially according to the gate start signal (VST) or the gate start signal supplied from the previous stage, thereby sequentially transmitting the gate signal from the first gate line (GL) to the last gate line (GL). It is supplied sequentially from the last gate line (GL) to the first gate line (GL).

The bridge area (BRA) is provided with a bridge pattern (BRP) for contacting each signal transmission wire of the gate link unit (G_Link) and the connection wire (CL) with each other. Additionally, the bridge pattern (BRP) can contact the connection wiring (CL) and the GIP driving unit (GIP-DP).

The bridge pattern (BRP) is located in the display area and the data signal line and can be used to contact the data line that transmits the data voltage to the pixel.

The seal area is formed on the edge of the first substrate 110 and the second substrate 115 along the non-display area (NDA) and on the outside of the display area (DA), and is formed between the liquid crystal layer (LC). A sealant is provided to bond the first substrate 110 and the second substrate 115 to each other. Since the seal area and the non-display area (NDA) of the first substrate 110 are not areas that display images, they are obscured by the housing of the display device. At this time, the part covered by the housing is also called a bezel. In order to reduce the width of the bezel, the seal area may overlap with a part of the gate link part (G_Link) described above, or further overlap with the area where the connection wire (CL) is placed or the area where the GIP driving part (GIP-DP) is formed. there is.

As the bezel width in the display device continues to decrease, the size of the seal area for bonding the upper and lower substrates of the display device may also be reduced. However, as the width of the seal area decreases, the adhesive force between the upper and lower substrates also decreases.

Referring to FIG. 1, the display device according to an embodiment of the present invention has a gate link in which a sealant is formed in the non-display area of the panel in order to realize a narrower bezel width and at the same time reinforce the adhesive force between the upper and lower substrates. It may be arranged to extend to the upper part of the plurality of signal transmission wires and connection wires (CL) or further to the upper part of the GIP driving unit (GIP-DP).

Since the gate link part and connection wiring (CL) or even the GIP driving part (GIP-DP) may be made of a material that has poor adhesion to the sealant, the sealant may be used on the gate link part's multiple signal transmission wiring and connection wiring (GIP-DP). Even if it extends to the top of the CL) or even to the top of part of the GIP driving part (GIP-DP), poor adhesion of the upper and lower substrates may occur due to weakened adhesive strength.

In the non-display area, a shield pattern is provided to improve these bonding defects. The shield pattern located in the non-display area is located in the display area and may be formed simultaneously with the spacer for maintaining a constant distance between the first substrate 110 and the second substrate 115. The shield pattern may be composed of polyimide (PI) or photo-acryl (PAC).

Additionally, the wiring and driving unit located in the non-display area and overlapping with the sealant are easily damaged by external force applied to the panel. In this case, foreign substances penetrate through the damaged area, causing problems such as corrosion/corrosion of metal wiring. For example, among the wiring areas overlapping with the sealant, the bridge pattern (BRP) formed of ITO not only has poor adhesion to the sealant, but is also vulnerable to cracks due to external forces. As the area formed by the bridge pattern (BRP) increases among the areas overlapping with the sealant, it causes poor adhesion of the panel, and when cracks occur in the bridge pattern area, a penetration path for external contaminants such as moisture and salt is formed, damaging the panel. This results in electrical/corrosive defects in the wiring. Therefore, in the display device according to an embodiment of the present invention, the shield pattern can improve the adhesion between the sealant and the bridge pattern (BRP) and minimize cracks occurring in the bridge pattern.

Figure 3 is a plan view showing an enlarged portion of a non-display area of a display device according to an embodiment of the present invention. FIG. 4A is a cross-sectional view of a corresponding portion along a line extending from A to A' shown in FIG. 3.

Figure 3 is an enlarged view of the contact between each signal transmission wire of the gate link unit (G_Link) and the connection wire (CL) and the contact between the connection wire (CL) and the GIP driving unit (GIP-DP) in the non-display area (NDA). This is a floor plan shown as follows. FIG. 4A is a cross-sectional view schematically showing a portion of the non-display area (NDA) and the display area (DA) of the display panel 100 along a line extending from point A to point A' shown in FIG. 3.

Referring to FIG. 3, a gate link portion (G_Link) including a plurality of signal transmission wires is formed on the outer side of the first substrate 110, and a GIP is formed further toward the display area DA than the gate link portion (G_Link). The driving part (GIP-DP) is located. As in the embodiments of the present invention, when the GIP driver (GIP-DP) is implemented with a thin film transistor formed on the first substrate 110, the gate link portion (G_Link) and the GIP driver ( At the same time as forming the GIP-DP), a connection wire (CL) is formed to transmit signals applied from a plurality of signal transmission wires formed in the gate link unit (G_Link) to the GIP driving unit (GIP-DP). The connection wire (CL) may be located between the gate link part (G_Link) and the GIP driving part (GIP-DP) or may be formed across two areas.

As shown in FIG. 3, the connection wire (CL) extends toward the GIP driving unit (GIP-DP) across a plurality of signal transmission wires. Therefore, the signal transmission wire and the connection wire (CL) of the gate link unit (G_Link) are composed of different conductive layers, and an insulating layer is interposed between the conductive layer where the signal transmission wire and the connection wire (CL) are formed, so that the connection wire (CL) is connected to an optional signal transmission wire and may extend across other signal transmission wires to the GIP drive unit (GIP-DP). For electrical connection between the two different conductive layers, the display panel 100 is provided with a plurality of bridge areas (BRA).

For convenience of explanation, FIG. 4A exemplarily illustrates the connection structure between one of the signal transmission wires described above and the connection wire CL. Referring to FIG. 4A, the signal transmission wire is formed of a first conductive layer (M1) and the connection wire (CL) is formed of a second conductive layer (M2), and one or more wires are formed between the signal transmission wire and the connection wire (CL). An insulating layer is interposed. For example, the signal transmission wiring is formed of a metal layer (Gate Metal) that forms the gate electrode 131 of the thin film transistor 130 formed on the first substrate 110, and the connection wiring CL is formed on the thin film transistor 130. It may be formed of a metal layer (S/D Metal) that forms source/drain electrodes. Conversely, the signal transmission wiring is formed of a metal layer (S/D Metal) that forms the source/drain electrodes of the thin film transistor 130 formed on the first substrate 110, and the connecting wiring CL is of the thin film transistor 130. It may be formed of a metal layer (Gate Metal) that forms a gate electrode. In this case, a gate insulation (GI) film may be interposed between the signal transmission wire and the connection wire (CL).

In addition, the signal transmission wiring is formed of the same conductive layer as the gate line (GL), the connection wiring (CL) is formed of the same conductive layer as the data line (DL), and there is a single layer between the signal transmission wiring and the connection wiring (CL). The above insulating layer may be interposed. Conversely, the signal transmission line may be formed of the same conductive layer as the data line DL, and the connection line CL may be formed of the same conductive layer as the gate line GL. In this case, an insulating layer similar to the insulating layer interposed between the gate line GL and the data line DL in the display area DA may be interposed between the signal transmission wire and the connection wire CL.

At least one insulating layer may also be provided on the signal transmission wire and the connection wire (CL). For example, as shown in FIG. 4A, a passivation film (PAS) and a planarization layer 122 may be formed on the signal transmission wire and the connection wire CL. In order to electrically connect the signal transmission wiring and connection wiring (CL) formed of different conductive layers, the signal transmission wiring and connection wiring (CL) are connected to the insulating layer on top of the signal transmission wiring and connection wiring (CL). A first contact area exists. First and second contact holes H1 and H2 are formed in the first contact area. A bridge pattern (BRP) is formed in the first contact hole (H1) of the first contact area where a part of the signal transmission wire is located and the second contact hole (H2) of the first contact area where a part of the connection wire (CL) is located. It is formed to electrically connect the signal transmission wire and the connection wire (CL). A bridge pattern (BRP) is formed on the contact holes (H1, H2) exposing the first contact area where the above-described first conductive layer (M1) and a portion of the second conductive layer (M2) are located, thereby forming the first conductive layer (M1) The area electrically connecting the layer M1 and the second conductive layer M2 is referred to as the bridge area BRA.

That is, in the non-display area, a first conductive layer (M1) and a first conductive layer (M1) forming the signal transmission wire and the connection wire (CL) located below through the contact hole of the insulating layer covering the signal transmission wire and the connection wire (CL). 2 A plurality of bridge patterns (BRP) patterns are formed that simultaneously contact the conductive layer (M2).

Likewise, the signal input terminal (S_In) at each stage (ST) of the GIP driving unit (GIP-DP) may be formed of a conductive layer different from the connection wiring (CL).

The GIP driver (GIP-DP) is equipped with a plurality of thin film transistors (TFTs) including a gate electrode, an active layer, and source/drain electrodes, and the gate driving signal applied by the signal transmission line of the thin film transistor is located in the display area. It is configured to be sequentially output to a plurality of gate wires. The signal input terminal (S_In) of each stage (ST) of the GIP driver (GIP-DP) may correspond to the gate electrode of the thin film transistor.

One of the plurality of signal transmission wires may be made of the same material as the gate electrode of the thin film transistor. Accordingly, the first conductive layer M1 may be the same metal layer as the gate electrode of the thin film transistor.

One of the plurality of connection wires CL may be made of the same material as the source/drain electrodes of the thin film transistor. Accordingly, the second conductive layer M2 may be the same metal layer as the source/drain electrodes of the thin film transistor.

The bridge pattern (BRP) is formed to connect one of a plurality of signal transmission wires made of the same material as the gate electrode and one of a plurality of connection wires made of the same material as the source/drain electrodes.

As shown in FIG. 4A, the signal input terminal (S_In) of the GIP driving unit (GIP-DP) may be formed of a conductive layer similar to the conductive layer that forms the signal transmission wiring. In this case, in order to electrically connect the signal input terminal (S_In) of the GIP driver (GIP-DP) formed of different conductive layers and the connection wire (CL), the signal input terminal (S_In) of the GIP driver (GIP-DP) is connected to the signal input terminal (S_In) of the GIP driver (GIP-DP). In the insulating layer above the wiring (CL), there is a second contact area where the signal input terminal (S_In) of the GIP driver (GIP-DP) and the connection wiring (CL) are connected. Third and fourth contact holes H3 and H4 are formed in the second contact area. The third contact hole (H3) in the second contact area where part of the connection wire (CL) is located and the fourth contact hole in the second contact area where part of the signal input terminal (S_In) of the GIP driver (GIP-DP) is located. A bridge pattern (BRP) is formed at (H4) to electrically connect the signal input terminal (S_In) of the GIP driver (GIP-DP) and the connection wire (CL). Therefore, the insulating layer covering the connection wiring (CL) and the signal input terminal (S_In) of the GIP driving unit (GIP-DP) includes a third contact hole exposing a part of the connecting wiring (CL) and a third contact hole of the GIP driving unit (GIP-DP). A fourth contact hole is formed exposing a portion of the signal input terminal (S_In).

In addition, a bridge pattern (BRP) is formed on the contact holes (H3, H4) exposing the second contact area, and the area that electrically connects the first conductive layer (M1) and the second conductive layer (M2) is called a bridge. It is referred to as an area (BRA). The contact area of the connecting wire (CL) located on the GIP driving part (GIP-DP) side and the contact area of the signal input terminal (S_In) of the GIP driving part (GIP-DP) are also bridge areas that connect the connecting wiring (CL) and the signal transmission wiring. They are connected to each other in the same structure as the (BRA) and transmit the signal applied from the signal transmission wire to the GIP driver (GIP-DP).

In addition, the signal applied from the driving circuit shown in FIG. 1 is transmitted to the data driver, or the data signal output from the data driver provided in the data pad portion D_Pad in the COG method is transmitted to the data line disposed in the display area DA. The data link wire (D_LL) for transmission to (DL) also has a bridge pattern (not shown) formed on the top of each corresponding contact hole (not shown), like the connection wire (CL) formed between the signal transmission wire and the GIP driver (GIP-DP). It can be electrically connected through BRP).

The data link wire (D_LL) may be a data signal transmission wire that transmits a signal to the data line (DL) located in the display area (DA).

Therefore, not only can a plurality of bridge areas (BRA) be provided in each of the surrounding areas of the gate link part (G_Link) and the GIP driving part (GIP-DP), but also the gate link part (G_Link) and the GIP driving part (GIP-DP) area. Multiple bridge areas (BRA) may be formed in other non-display areas (NDA). For example, the bridge area BRA described above may also be applied to the pad portion PAD shown in FIG. 1.

As described above, in order to implement a narrower bezel width and at the same time reinforce the adhesive force between the first substrate 110 and the second substrate 115, the seal area is formed by a gate link portion (G_Link) or more formed in the non-display area (NDA). Furthermore, it can be designed to overlap with the area where the GIP driving part (GIP-DP) is formed. In this case, sealant may be applied on some bridge areas (BRAs). However, the bridge pattern (BRP) formed in the bridge area (BRA) may be made of a material that has poor adhesion to the sealant. For example, in the case of a bridge pattern (P) formed of ITO, not only does it have poor adhesion to the sealant, but cracks can easily occur due to external force transmitted through the cured sealant. Ultimately, even if the sealant extends to a part of the GIP driving part (GIP-DP), defective adhesion of the first substrate 110 and the second substrate 115 may occur due to weakened adhesive strength between the sealant and the bridge pattern (BRP). You can. Additionally, when a crack occurs in the bridge pattern (BRP) overlapping with the sealant, foreign substances penetrate through the damaged area, causing corrosion/corrosion of the wiring formed in the metal layer below the bridge pattern (BRP).

Therefore, in the display panel 100 according to embodiments of the present invention, a shield pattern (SHP) formed of the same material as the plurality of lower spacers (L_SP) formed in the display area (DA) of the first substrate 110 It is formed in a position corresponding to the bridge area (BRA) of the non-display area (NDA). In other words, the shield pattern (SHP) is formed to cover the bridge pattern (BRP) located in the non-display area (NDA). One individual shield pattern (SHP) disposed on the bridge area (BRA) may be formed to cover one bridge pattern (BRP), as shown in FIGS. 3 and 4A. In Figure 4a, the shield pattern (SHP) covering the upper part of the bridge pattern (BRP) that electrically connects the signal transmission wire and the connection wire is the contact hole (H1, H2) formed to contact the bridge pattern (BRP) to the first contact area. ) is formed to fill the Likewise, a shield pattern (SHP) is formed on the top of the bridge pattern (BRP) that electrically connects the connection wire (CL) and the signal input terminal (S_In) of the GIP driver (GIP-DP) in the same form as the bridge pattern (BRP) on the opposite side. It is formed to fill the contact holes (H3, H4).

In addition, the data signal transmission wiring shown in FIG. 1 for transmitting the data signal output from the data driver to the data line (DL) disposed in the display area (DA) is also formed between the signal transmission wiring and the GIP driving unit (GIP-DP). Like the connection wire CL, a bridge pattern BRP may be formed to be electrically connected to the data line DL. A third contact area may be provided in which the data signal transmission wiring and the data line (DL) are contacted by a bridge pattern (BRP).

A third contact area may be formed at both ends of the bridge pattern (BRP) where contact holes through which the data signal transmission line and the data line (DL) contact each other are located.

Referring to FIG. 4A, the shield pattern (SHP) disposed on top of the bridge pattern (BRP) is made of the same material as the lower spacer (L_SP) disposed to correspond to the upper spacer (U_SP) in the display area (DA) during the same process. can be formed. Accordingly, the shield pattern SHP disposed in the bridge area BRA and the lower spacer L_SP disposed in the display area DA may be formed at the same height. However, since the structures formed between the first substrate 110 and the second substrate 115 may be different between the display area DA and the non-display area NDA, the shield pattern disposed in the bridge area BRA ( The lower spacer (L_SP) disposed in the SHP) and display area (DA) may be formed at different heights as needed. For example, the shield pattern (SHP) formed in the bridge area (BRA), that is, the non-display area (NDA), may also affect the cell gap between the first substrate 110 and the second substrate 115. Therefore, the shield pattern (SHP) formed in the upper part of the bridge area (BRA) can be formed at a lower height than the lower spacer (L_SP) formed in the display area (DA). As another example, in terms of protecting the bridge area (BRA), it may be more desirable to increase the height of the shield pattern (SHP) covering the bridge area (BRA). In order to make the height of the shield pattern (SHP) of the bridge area (BRA) and the lower spacer (L_SP) of the display area (DA) different from each other, a shield pattern (SHP) is formed in one of the two areas using a Half-Tone mask. ), or the lower spacer (L_SP) may be formed to have a higher or lower height than the shield pattern (SHP) or lower spacer (L_SP) in other areas.

In FIG. 4A, it is shown that the entire shield pattern (SHP) covering the bridge pattern (BRP) of the bridge area (BRA) is covered by the sealant. However, as described above, the seal area may overlap with a portion of the gate link part (G_Link), and other parts of the gate link part (G_Link) may not overlap with the seal area. In addition, even if the seal area overlaps the entire area of the gate link part (G_Link), some bridge areas (BRA) provided in the GIP driving part (GIP-DP) area may be located outside the seal area. A bridge area (BRA) may be provided even in a place that does not overlap with the seal area, and a shield pattern (SHP) may be provided on the bridge area (BRA) that does not overlap the seal area.

As shown in FIG. 4A, when the shield pattern (SHP) is locally formed in each bridge area (BRA) located below the sealant, stains may occur around the seal area due to the step of the shield pattern (SHP). In order to reduce the step caused by the shield pattern (SHP) in the seal area, one shield pattern (SHP) may be arranged to cover a plurality of bridge areas (BRA).

Additionally, referring to FIG. 4A, the upper spacer (U_SP) and the lower spacer (L_SP) may be positioned on the upper and lower substrates facing each other with the liquid crystal interposed therebetween. Among these, the lower spacer (L_SP) may be a shield pattern (SHP) covering the bridge pattern (BRP) of the bridge area (BRA).

In each of the plurality of bridge areas (BRA), the first contact hole (H1) in which the first metal layer (M1) is exposed and the second contact hole (H2) in which the second metal layer (M2) is exposed are disposed on the first contact hole (H1) A bridge pattern (BRP) may be provided that connects the first metal layer (M1) and the second metal layer (M2) through (H1) and the second contact hole (H2).

A portion of the lower spacer (L_SP) may be disposed at a position corresponding to the upper spacer (U_SP), and another portion of the lower spacer (L_SP) may be disposed to overlap with at least one bridge area among the plurality of bridge areas (BRA). .

The first metal layer (M1) is a gate metal layer, the second metal layer (M2) is a source/drain metal layer, and the bridge electrode (BRP) is made of ITO.

At least one bridge area among the plurality of bridge areas is located within the seal area.

The lower spacer (L_SP) provided on the lower substrate and the upper spacer (U_SP) provided on the upper substrate may be made of the same material.

The spacer may be composed of polyimide (PI) or photo-acryl (PAC).

In addition, the shield pattern (SHP) covering the bridge pattern (BRP) of the bridge area (BRA) according to an embodiment of the present invention is a plurality of pixels in an organic light emitting display device in which a plurality of pixels with organic light emitting elements are arranged. It can be a bank pattern that distinguishes each.

FIG. 4B is a cross-sectional view of a corresponding portion along a line extending from A to A' shown in FIG. 3 according to another embodiment of the present invention.

FIG. 4B is a cross-sectional view schematically showing the display panel 100 provided with a shield pattern (SP) arranged to cover a plurality of bridge areas (BRA) according to another embodiment of the present invention. Referring to Figure 4b, a bridge pattern (BRP) connects the signal transmission wire and the connection wire (CL), and a bridge pattern (BRP) connects the connection wire (CL) and the signal input terminal (S_In) of the GIP driver (GIP-DP). This is covered by a single shield pattern (SHP). In this way, by forming the shield pattern (SHP) to cover several bridge patterns (BRP), the step caused by the shield patterns (SHP) disposed below the sealant can be reduced.

The shield pattern (SHP) placed in the non-display area (NDA) extends not only to the two bridge patterns (BRP) located at both ends of the connection wire (CL), but also to other bridge patterns (BRP) around it, creating two or more bridge patterns. (BRP) can be formed to cover them. Depending on the adhesion between the material forming the shield pattern (SHP) and the sealant, the shield pattern (SHP) in the non-display area (NDA) covers part or the entire gate link part (G_Link) in a single pattern, or covers the GIP driver part (GIP). -DP) may be formed over part or the entire area. In particular, when the shield pattern (SHP) is formed of a material that has better adhesive properties with the sealant compared to the bridge electrode (BRL) formed of ITO, the sealant pattern (SHP) that locally covers each bridge pattern (BRP) A single pattern shield pattern (SHP) with a constant area in proportion to the area is disposed across the gate link part (G_Link) and the GIP driver part (GIP-DP) to form the first substrate 110 and the second substrate 115. ) may be more advantageous for cementation and protection of the bridge pattern (BRP). Materials that form this shield pattern (SHP) include Photo Acryl (PAC) or Polyimide (PI).

In the embodiments of the present invention described with reference to the drawings, the gate link part (G_Link), connection wiring, and GIP driving part (GIP-DP) arranged in the seal area and non-display area (NDA) overlap. By allowing the sealant to have more improved adhesion compared to the existing structure, it not only reduces the occurrence of bonding defects between the first substrate 110 and the second substrate 115, but also reduces the bezel width of the display device below a certain level. It can be reduced to

In addition, in the area where the seal area and the non-display area (NDA) overlap, corrosion/corrosion of the first metal layer (M1) and the second metal layer (M2) due to damage to the bridge pattern (BRP) at the bottom of the sealant is suppressed. Accordingly, a more robust display panel 100 can be provided.

Furthermore, in reducing the bezel width of the display device, the first substrate 110 and the second substrate 115 are designed to avoid the seal area and bridge area (BRA) and without adding a separate process or new mask. ), and the occurrence of corrosion/corrosion of wiring can be reduced, making it possible to manufacture the display panel 100 with a high degree of design/process freedom.

The display device of the present invention has a lower substrate divided into a display area and a non-display area, corresponding to the lower substrate, and an upper substrate including a black mattress (BM), located on the non-display area and in a direction away from one side of the display area. A bezel including a GIP driving unit, a plurality of signal transmission wires, a seal area equipped with a connection wire and sealant connecting the GIP driving unit and a plurality of signal transmission wires, and a non-display area. Located in the GIP driver and connection wiring, a plurality of bridge patterns that electrically connect the connection wiring and a plurality of signal transmission wires, and a plurality of shield patterns surrounding each of the plurality of bridge patterns. In addition, the multiple shield patterns minimize the area where the sealant and the multiple bridge patterns are in direct contact.

In the seal area, the sealant can bond the lower substrate and upper substrate.

The sealant is placed to locally overlap with the signal transmission wiring, thereby minimizing the bezel area.

The GIP driver includes a plurality of thin film transistors (TFTs) including a gate electrode, an active layer, a source electrode, and a drain electrode, and the thin film transistors have a plurality of gate driving signals applied by a plurality of signal transmission wires located in the display area. It can be configured to be output sequentially to the gate wiring of .

One of the plurality of signal transmission wires may be made of the same material as the gate electrode of the thin film transistor.

One of the plurality of connection wires may be made of the same material as the source electrode or drain electrode of the thin film transistor.

The plurality of bridge patterns may be arranged so that one of a plurality of signal transmission wires made of the same material as the gate electrode is connected to one of a plurality of connection wires made of the same material as the source electrode or the drain electrode.

Both ends of the bridge pattern may be provided with a first contact area to connect signal transmission wires and connection wires.

A portion of the first contact area may be disposed within the seal area.

The bridge pattern may be made of ITO (Indium Tin Oxide).

The shield pattern may be arranged to cover the first contact area.

The adhesion between the shield pattern and the sealant may be greater than the adhesion between the sealant and the bridge pattern.

The plurality of shield patterns may be made of polyimide (PI) or photo-acryl (PAC).

The bridge pattern can connect any one of a plurality of connection wires to the gate electrode of the thin film transistor.

Both ends of the bridge pattern may be provided with a second contact area to connect the signal transmission wire and the thin film transistor.

A portion of the second contact area may be disposed within the seal area.

It is located in the non-display area and may further include a plurality of data signal transmission wires that transmit data signals input from the outside to data lines in the display area.

One of the plurality of data signal transmission wires may be made of the same material as the gate electrode of the thin film transistor.

Any one of the plurality of data signal transmission wires made of the same material as the gate electrode may be electrically connected to the data line through a bridge pattern.

A third contact area may be provided at both ends of the bridge pattern to contact each of the data signal transmission line and the data line.

The liquid crystal display device of the present invention includes an upper substrate and a lower substrate arranged to face each other with liquid crystal interposed, a plurality of upper spacers provided on the upper substrate, a plurality of lower spacers provided on the lower substrate, and a plurality of external signal wires. A gate link unit, a GIP driver equipped with a shift register, a plurality of bridge areas electrically connecting a plurality of external signal wires and the GIP driver, a sealant provided in the seal area overlapping with a portion of the gate link unit and the GIP driver, and Each of the plurality of bridge regions is disposed on a first contact hole where the first metal layer is exposed and a second contact hole where the second metal layer is exposed, so that the first metal layer and the second metal layer are connected through the first contact hole and the second contact hole. It includes a connecting bridge electrode, where a portion of the plurality of lower spacers is disposed at a position corresponding to the upper spacer, and another portion of the plurality of lower spacers is disposed to overlap with at least one bridge region among the plurality of bridge regions.

The seal area may at least partially overlap the gate link unit or the GIP driver unit.

The first metal layer is a gate metal layer, the second metal layer is a source/drain metal layer, and the bridge electrode may be formed of ITO.

At least one bridge area among the plurality of bridge areas may be located within the seal area.

The lower spacer provided on the lower substrate and the upper spacer provided on the upper substrate may be made of the same material.

The lower spacer provided on the lower substrate and the upper spacer provided on the upper substrate are made of different materials, and the spacer provided on the lower substrate may be made of polyimide (PI) or photo-acryl (PAC). You can.

The organic light emitting display device of the present invention includes a substrate including a display area and a non-display area on which a plurality of pixels equipped with organic light emitting elements are arranged, located on the non-display area, and a GIP driver in a direction away from one side of the display area. Bezel including a seal area equipped with multiple signal transmission wires, connection wires connecting the GIP driver and multiple signal transmission wires, and sealant, located on the non-display area and connected to the GIP driver. It includes a plurality of bridge patterns that electrically connect the wiring and connection wiring and a plurality of signal transmission wires, and a plurality of shield patterns surrounding each of the plurality of bridge patterns.

The display area may further include a bank pattern that separates each of the plurality of pixel areas.

The shield pattern may be made of the same material as the bank pattern.

The shield pattern may be configured to cover a portion of each of the plurality of signal transmission wires, connection wires, and the GIP driver.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

10: display device 100: display panel
110: first substrate 115: second substrate
121: gate insulating film 122: planarization layer
123: Insulating layer 130: Thin film transistor
131: gate electrode 132: active layer
133: second electrode 134: first electrode
140: common electrode 150: pixel electrode
BM: Black matrix OC: Overcoat layer
U_SP: Upper spacer L_SP: Lower spacer
G_Link: Gate link part GIP-DP: GIP driving part
D_LL: Data link wiring CL: Connection wiring
DA: Display area NDA: Non-display area
BRA: Bridge area BRP: Bridge pattern
G_Pad: Gate pad part D_Pad: Data pad part
S_In: Signal input terminal CF1-CF3: Color filter
M1: first conductive layer M2: second conductive layer
SHP: Shield pattern H1, H2, H3, H4: 1st, 2nd, 3rd, 4th contact holes

Claims (30)

A lower substrate divided into a display area and a non-display area;
an upper substrate corresponding to the lower substrate;
Located on the non-display area, it includes a GIP driver, a plurality of signal transmission wires, a seal area equipped with a connection wire and sealant connecting the GIP driver and the plurality of signal transmission wires. Bezel;
a plurality of lower spacers disposed on the lower substrate between the lower substrate and the upper substrate;
A plurality of first bridge patterns located on the non-display area and electrically connecting the GIP driver and the connection wire, and the connection wire and the plurality of signal transmission wires, respectively; and
It is disposed on the same layer as the lower spacer and includes a plurality of shield patterns surrounding each of the plurality of first bridge patterns,
The display device wherein the plurality of shield patterns minimize the area where the sealant and the plurality of first bridge patterns are in direct contact. According to claim 1,
In the seal area, the sealant bonds the lower substrate and the upper substrate,
The sealant is disposed to locally overlap the signal transmission wire, thereby minimizing the area of the bezel. delete According to claim 1,
The GIP driver includes a plurality of thin film transistors (TFTs) including a gate electrode, an active layer, a source electrode, and a drain electrode, and the thin film transistor is configured to transmit a gate driving signal applied by the plurality of signal transmission wires to the display. A display device configured to sequentially output output to a plurality of gate lines located in an area. According to clause 4,
One signal transmission wire among the plurality of signal transmission wires is made of the same material as the gate electrode of the thin film transistor,
A display device, wherein any one of the plurality of connection wires is made of the same material as the source electrode or drain electrode of the thin film transistor. delete According to clause 5,
The plurality of first bridge patterns are arranged so that one of the signal transmission wires made of the same material as the gate electrode and the one connection wire made of the same material as the source electrode or the drain electrode are connected. Device. According to clause 4,
Both ends of the first bridge pattern are provided with a first contact area to connect the signal transmission wire and the connection wire,
A portion of the first contact area is disposed within the seal area. delete delete According to clause 8,
The shield pattern is arranged to cover the first contact area. According to claim 1,
A display device wherein an adhesive force between the shield pattern and the sealant is greater than an adhesive force between the sealant and the first bridge pattern. According to claim 1,
A display device wherein the plurality of shield patterns are made of polyimide (PI) or photo-acryl (PAC). According to clause 4,
The first bridge pattern connects one of the plurality of connection wires to a gate electrode of the thin film transistor. According to claim 14,
Both ends of the first bridge pattern are provided with second contact areas to connect the signal transmission wire and the thin film transistor,
A portion of the second contact area is disposed within the seal area. delete According to clause 4,
Located in the non-display area, it further includes a plurality of data signal transmission wires that transmit data signals input from the outside to data lines in the display area,
A display device, wherein one of the plurality of data signal transmission wires is made of the same material as a gate electrode of the thin film transistor. delete According to claim 17,
A display device, wherein the one data signal transmission wire is electrically connected to the data line through a second bridge pattern. According to claim 1,
The shield pattern and the lower spacer have different heights. An upper substrate and a lower substrate disposed facing each other with liquid crystal interposed therebetween;
a plurality of upper spacers provided on the upper substrate;
a plurality of lower spacers provided on the lower substrate;
A gate link unit in which a plurality of external signal wires are arranged;
GIP driving unit equipped with a shift register;
Bridge electrodes located in a plurality of bridge areas and electrically connecting the plurality of external signal wires and the GIP driver; and
It includes a sealant provided in a seal area overlapping with a portion of the gate link portion and the GIP driving portion,
The bridge electrode is disposed on the first contact hole where the first metal layer is exposed and the second contact hole where the second metal layer is exposed, and connects the first metal layer and the second contact hole through the first contact hole and the second contact hole. Connects the metal layers,
A portion of the plurality of lower spacers is disposed at a position corresponding to the upper spacer, and another portion of the plurality of lower spacers is disposed to overlap at least one bridge region among the plurality of bridge regions. According to claim 21,
The seal area is at least partially overlapped with the gate link unit or the GIP driver unit. According to claim 21,
The first metal layer is a gate metal layer, the second metal layer is a source/drain metal layer, and the bridge electrode is formed of ITO. According to claim 21,
At least one bridge area among the plurality of bridge areas is located within the seal area. delete delete delete According to claim 1,
In the display area, a plurality of pixels equipped with organic light-emitting elements are arranged,
In the display area, further comprising a bank pattern that distinguishes each of the plurality of pixels,
The display device wherein the shield pattern is made of the same material as the bank pattern. delete According to claim 1,
The shield pattern is configured to cover a portion of each of the plurality of signal transmission wires, the connection wires, and the GIP driver.

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