KR102469224B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and the display device according to the present invention includes: a substrate including a display area having deformed corners and a non-display area adjacent to the display area; a plurality of pixels in the display area, each including a transistor; A gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, and a plurality of gate wires disposed on at least one side of the display area. and a plurality of power supply wires branched off from the power supply wires and supplying a high potential voltage to a plurality of pixels, and the gate driver is located in an area excluding the deformed corner. Accordingly, the size of the bezel of the display device can be minimized and luminance uniformity of the display device can be improved.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device in which luminance uniformity is improved and the width of a bezel at a corner portion is minimized.

Currently, various display devices are being developed and marketed. For example, a liquid crystal display device (LCD), a field emission display device (FED), an electrophoretic display device (EPD), an electro-wetting display device There are display devices such as a display device (EWD), an organic light emitting display device (OLED), and a quantum dot display device (QD).

The display device includes a display area where a plurality of pixels are arranged to display an image and a non-display area surrounding the display area and not displaying an image. In this case, a plurality of pixels may be defined in the display area. Also, wires and circuits for transmitting various signals to a plurality of pixels are disposed in the non-display area.

As technology for realizing such a display device develops and many products are mass-produced, display devices are being developed with a focus on technology for realizing a design desired by consumers. One of them is the diversification of the form of a display area in which an image is implemented. Specifically, the display area is required to have various shapes beyond the rectangular shape. For example, efforts are needed to secure flexibility in product design by diversifying the shape of a display area of a display device having various purposes, such as a wearable display device. In addition, as the shape of the display area diversifies, it is also necessary to change the design of the shape of the non-display area surrounding the display area and wires arranged in the non-display area.

The inventors of the present invention developed a display device having a display area with deformed corners according to various design changes of consumers. The deformed corner means a corner of various shapes such as a round corner, not a corner having a rectangular shape. Also, it has been invented that the display area has a molded corner, so that the corner of the non-display area corresponding to the molded corner also has a shape corresponding to the molded corner. However, it was recognized that there is a limit to reducing the area of the non-display area by the gate driver positioned on both sides of the display area.

And, the inventors of the present invention recognized that it is important to uniformly supply a power supply voltage to a plurality of pixels. However, when the inventors of the present invention implement the corner of the display area as a molded corner, since the number of wires to be disposed is greater than that of the conductive layer disposed in the non-display area corresponding to the molded corner, the horizontal line for supplying the power voltage It was recognized that it was difficult to route the wiring to the deformed corner.

Accordingly, the inventors of the present invention minimize the width of the non-display area corresponding to the deformed corner and simultaneously change the design of the gate driver and the wiring for the non-display area corresponding to the display area having the deformed corner. A display device with a new structure capable of uniformly supplying power voltage to pixels has been developed.

An object to be solved by the present invention is to provide a display device in which the width of a bezel in a deformed corner area is reduced by arranging a gate driver in a non-display area that does not correspond to the deformed corner.

Further, an object to be solved by the present invention is to provide a display device in which contact holes are disposed so that data wires and gate wires disposed in the non-display area corresponding to the deformed corner do not cross each other.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes a substrate including a display area having a shaped corner and a non-display area adjacent to the display area, a plurality of pixels in the display area and each including a transistor, and a plurality of pixels in the non-display area. , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, a plurality of gate wires in a non-display area, and extending in the same direction as the plurality of gate wires. A power supply wire and a plurality of power supply wires branched off from the power supply wire and supplying a high potential voltage to a plurality of pixels, and the gate driver is located in an area other than the deformed corner. Accordingly, the size of the bezel of the display device may be minimized by changing the location of the gate driver, and a high-potential power supply voltage may be supplied to a plurality of pixels.

In addition, a display device according to another embodiment of the present invention includes a substrate including a display area having a shaped corner and a non-display area adjacent to the display area, a plurality of pixels in the display area, each including a transistor, and a non-display area. , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver and supplying gate signals to a plurality of pixels, located in the non-display area and in the same direction as the plurality of gate wires. It includes an extended power supply wiring and a plurality of power supply wirings branched from the power supply wirings and supplying a high potential voltage to a plurality of pixels, and the gate driver includes a plurality of stages supplying gate signals to the plurality of gate wirings. Including, some of the plurality of stages are disposed to correspond to the molded corner, and a gate signal is supplied to a gate wire disposed in a region corresponding to the molded corner among the plurality of gate wires. Accordingly, a stable gate signal may be supplied to each of the pixels disposed at the molded corner.

In addition, a display device according to another embodiment of the present invention has a substrate having a shape corner and including a display area in which a plurality of pixels provided with transistors are defined and a non-display area adjacent to the display area, on both sides of the display area. A gate driver formed in an area other than the deformed corner to minimize the area of the non-display area corresponding to the deformed corner, a power supply wire in the non-display area, and a plurality of power supply wires integrally formed with the power supply wire, the power supply wire is formed in an area corresponding to the entire display area to supply a power supply voltage to a plurality of pixels. Accordingly, the uniformity of luminance of the display device may be improved by supplying the power supply voltage to all of the plurality of pixels defined in the display device. Also, the width of the non-display area may be reduced.

Other embodiment specifics are included in the detailed description and drawings.

The present invention can reduce the bezel width by not disposing the gate driver in the non-display area corresponding to the deformed corner.

In addition, since the present invention can supply a uniform power supply voltage to the entire pixel by arranging the power supply wiring in the display area, the uniformity of luminance can be improved.

Further, the present invention arranges the contact hole so that the data line and the gate line disposed in the non-display area corresponding to the deformed corner do not cross each other, so that a high potential voltage can be supplied to each pixel.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is an enlarged plan view of regions A and B of FIG. 1 .
FIG. 3 is a cross-sectional view of IIIa-IIIa' and IIIb-IIIb' of FIG. 2 .
4 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view of Va-Va' and Vb-Vb' of FIG. 4 .
6 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention.
7 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention.
8 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, and as those skilled in the art can fully understand, various interlocking and driving operations are possible, and each embodiment can be implemented independently of each other. It may be possible to implement together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the display device 100 includes a substrate 110 , a gate driver 120 and a power supply wire 130 .

The substrate 110 is a substrate 110 for supporting and protecting various components of the display device 100 . The substrate 110 may be made of glass or a plastic material having flexibility. When the substrate 110 is made of a plastic material, it may be made of, for example, polyimide (PI). However, it is not limited thereto.

The substrate 110 includes a display area AA and a non-display area NA adjacent to the display area AA.

The display area AA is an area where an image is displayed in the display device 100, and a display element and various driving elements for driving the display element are disposed in the display area AA. A corner of the display area AA may be a molded corner. The deformed corner means a corner of various shapes, not a rectangular corner like the corner of the general display area AA. For example, the deformed corner may be a round corner or may be a partial shape of a pentagon or hexagon, but is not limited thereto.

The non-display area NA is an area adjacent to the display area AA. The non-display area NA is an area adjacent to and surrounding the display area AA. The non-display area NA is an area where no image is displayed, and wiring and circuit parts are formed. For example, the gate driver 120 and the power supply line 130 may be disposed in the non-display area NA. As shown in FIG. 1 , the non-display area NA may have an irregular corner. However, it is not limited thereto and may have a corner having two perpendicular sides.

The gate driver 120 is a circuit for supplying a gate signal to the pixel PX. As shown in FIG. 1 , the gate driver 120 may be disposed on both sides of the display area AA, but may also be disposed on one side of the display area AA. The gate driver 120 may supply a gate signal to each pixel of the display area AA.

The power supply line 130 is in the non-display area NA and is a line for supplying a power voltage to a pixel. For example, the power supply line 130 may supply a power voltage to each pixel of the display area AA.

Although not shown in FIG. 1 , the display device 100 may include an external module, for example, a Chip On Film (COF). The COF may be bonded to the non-display area NA and electrically connected to the substrate 110 through a pad. The COF may include a base film made of an insulating material and a driving IC formed on the base film. The COF may supply power voltages and data voltages to the display area AA through pads.

Hereinafter, FIGS. 2 and 3 will be referred to together for a more detailed description of the display device 100 .

FIG. 2 is an enlarged plan view of regions A and B of FIG. 1 . FIG. 3 is a cross-sectional view of IIIa-IIIa' and IIIb-IIIb' of FIG. 2 . Areas A and B of FIG. 2 are enlarged plan views of deformed corners of the display area AA. Areas A and B can be configured symmetrically, so duplicate descriptions are omitted.

Referring to FIGS. 2 and 3 , the display area AA includes a plurality of pixels PX. The plurality of pixels PX are in the display area AA and include elements such as the transistor 140 . Each of the plurality of pixels PX is connected to a gate line GL, a data line DL, and a power line VDDL. The gate line GL is a line that transmits a gate signal to the plurality of pixels PX, the data line DL is a line that transmits a data signal to the plurality of pixels PX, and the power line VDDL is a line that transmits a plurality of data signals to the plurality of pixels PX. It is a wire for supplying a power supply voltage to the pixel PX.

Referring to FIG. 3 for a description of the structure of each pixel PX of the display area AA, the transistor 140 is disposed on the substrate 110 . Specifically, the active layer 141 in which the channel of the transistor 140 is formed is formed on the substrate 110 , and the gate insulating layer 111 is formed on the active layer 141 . The gate insulating layer 111 is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), and may be a single layer or a plurality of layers thereof, but is not limited thereto. A gate electrode 142 is formed on the gate insulating layer 111 . A first interlayer insulating layer 112 is formed on the gate electrode 142 . The first interlayer insulating layer 112 may be made of, for example, silicon nitride (SiNx), but is not limited thereto. A second interlayer insulating layer 113 is formed on the first interlayer insulating layer 112 . The second interlayer insulating layer 113 may be formed of the same material as the first interlayer insulating layer 112, but is not limited thereto. A source electrode 143 and a drain electrode 144 of the transistor 140 may be formed on the second interlayer insulating layer 113 . The source electrode 143 and the drain electrode 144 are electrically connected to the active layer 141 through contact holes formed in the gate insulating layer 111, the first interlayer insulating layer 112, and the second interlayer insulating layer 113. Connected. Although the transistor 140 is illustrated in FIG. 3 as a top gate type coplanar structure, the multilayer structure of the transistor 140 is not limited thereto. In addition, in FIG. 3, it is shown that the gate insulating layer 111 and the second interlayer insulating layer 113 planarize the top, but is not limited thereto, and the gate insulating layer 111 and the second interlayer insulating layer 113 It may be disposed conformally along the shape of the surface of the elements disposed below.

A conductive layer 150 may be disposed between the first interlayer insulating layer 112 and the second interlayer insulating layer 113 . For example, in the display device 100 according to an exemplary embodiment of the present invention, two interlayer insulating layers 112 and 113 are used to form a gap between the first interlayer insulating layer 112 and the second interlayer insulating layer 113. As the additional conductive layer 150 is disposed, the conductive layer 150 may be disposed between the source electrode 143 and the drain electrode 144 of the transistor 140 and the gate electrode 142 of the transistor 140. . Accordingly, as the number of conductive patterns and wires that can be additionally disposed increases, a higher resolution display device 100 can be provided, wires with lower resistance can be provided, and capacitors in the display device 100 can be provided. The capacitance may be improved by additionally connecting in parallel.

Also, referring to FIG. 2 , the power supply line 130 extends in the same direction as the plurality of gate lines GL and is disposed in the non-display area NA. For example, the power supply line 130 may extend in the same direction as the direction in which the plurality of second gate lines GL2 disposed in the display area among the plurality of gate lines GL extend.

And, the power supply wiring 130 is connected to a plurality of power wiring VDDL. The plurality of power lines VDDL are lines branched from the power supply line 130 and supply high potential voltages to the plurality of pixels PX. The plurality of power supply wires VDDL are made of the same material as the power supply wires 130 and may be branched from the power supply wires 130 . For example, the power supply line 130 and the plurality of power lines VDDL may be formed in one process. In this case, the power supply line 130 and the plurality of power lines VDDL may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 .

Further, the width W1 of the power supply wiring 130 in the direction in which the plurality of gate lines GL extends is equal to the distance D2 between the outermost power lines VDDL among the plurality of power lines VDDL. may be ideal The width W1 of the power supply line 130 means the width of the power supply line 130 in a direction parallel to the direction in which the plurality of gate lines GL extend. The distance D2 between the outermost power lines VDDL may be the distance between the two outermost power lines VDDL among the plurality of power lines VDDL branched from the power supply line 130. . Also, the power supply wiring 130 may be arranged to correspond to the entire display area AA. The width W3 of the display area AA may be the maximum width of the display area AA in the direction in which the plurality of gate lines GL extend. For example, as shown in FIG. 2 , the width W1 of the power supply line 130 may be the same as the width W3 of the display area AA and may correspond to the entire display area AA.

Alternatively, the power supply wiring 130 may be formed to be larger than the width W3 of the display area AA. For example, the width W1 of the power supply line 130 may be greater than the width W3 of the display area AA.

When the width W1 of the power supply wiring 130 is greater than the distance D2 between the outermost power lines VDDL or greater than the width W3 of the display area AA, the branched power supply wiring 130 The outermost power lines VDDL among the plurality of power lines VDDL may supply power voltage to the outermost pixel PX among the plurality of pixels PX. Accordingly, all of the plurality of pixels PX may receive a high potential voltage through the plurality of power lines VDDL branched from the power supply line 130 .

Referring to FIG. 2 , the gate driver 120 disposed on both sides of the display area AA includes a plurality of stages 121 and 122 . Each of the plurality of stages 121 and 122 may be connected to each of a plurality of gate lines GL to transfer gate signals to the plurality of pixels PX. The gate driver 120 is located on both sides of the display area AA except for the molded corner of the display area AA. For example, the corner area CA may be a non-display area NA corresponding to the irregular corner of the display area AA, and the plurality of stages 121 and 122 of the gate driver 120 may be the corner area CA. ) may be disposed only in the non-display area NA except for.

Referring to FIGS. 2 and 3 , the plurality of gate lines GL are connected to the plurality of stages 121 and 122 of the gate driver 120, respectively, and transmit a gate signal from the gate driver 120 to a plurality of pixels PX. ) is a wire that is transmitted to each. The plurality of gate lines GL includes a plurality of first gate lines GL1 and a plurality of second gate lines GL2 . The plurality of first gate lines GL1 refer to lines extending from the gate driver 120 and are made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 . In addition, the plurality of second gate lines GL2 refer to lines that are connected to the plurality of first gate lines GL1 and extend into the display area AA, and are made of the same material as the gate electrode 142 of the transistor 140 . to be. Referring to FIG. 3 , the plurality of first gate lines GL1 and the plurality of second gate lines GL2 are the plurality of second contacts formed on the first interlayer insulating layer 112 and the second interlayer insulating layer 113 . They are electrically connected through each of the holes CH2.

Referring to FIG. 2 , each of the plurality of second contact holes CH2 contacting each of the plurality of first gate lines GL1 and each of the plurality of second gate lines GL2 includes a plurality of power lines VDDL and a plurality of second gate lines GL2. located outside the data line DL of Specifically, the plurality of second contact holes CH2 may be positioned outside the outermost power line VDDL among the plurality of power lines VDDL. Also, the plurality of second contact holes CH2 may be located outside the outermost data line DL among the plurality of data lines DL.

Accordingly, the plurality of first gate lines GL1 may be disposed in an area different from an area in which the plurality of power lines VDDL and the plurality of data lines DL are disposed. Specifically, the plurality of first gate lines GL1 are connected to each of the plurality of stages 121 and 121 and connected to the plurality of second gate lines GL2 through each of the plurality of second contact holes CH2. . Accordingly, the plurality of first gate lines GL1 are positioned outside the plurality of second contact holes CH2. Since the plurality of second contact holes CH2 are located outside the plurality of power lines VDDL and the plurality of data lines DL, the plurality of first gate lines GL1 are different from the plurality of power lines VDDL. can be placed in an area. Also, the plurality of first gate lines GL1 may be disposed in different regions from the plurality of data lines DL.

Referring to FIG. 2 , the plurality of data lines DL are disposed parallel to the plurality of power lines VDDL and are connected to each of the plurality of pixels PX to supply data signals. The plurality of data lines DL may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 .

A plurality of data lines DL may be connected to a plurality of data link lines DLL. The plurality of data link lines DLL are disposed in the non-display area NA, and may supply data signals to the plurality of data lines DL. The plurality of data link wires (DLL) include a first data link wire (DLL1), a second data link wire (DLL2), a third data link wire (DLL3), a fourth data link wire (DLL4), and a fifth data link wire. (DLL5). The number of the plurality of data link wires (DLL) is not limited thereto, and a larger number of the plurality of data link wires (DLL) may exist.

Also, some of the plurality of data link lines (DLL) may be made of the same material as the gate electrode 142 of the transistor 140, and other parts may be made of the same material as the conductive layer 150. For example, the first data link and the third data link may be made of the same material as the gate electrode 142 , and the second data link and the fourth data link may be made of the same material as the conductive layer 150 . For example, data link wires DLL1 , DLL3 , and DLL5 made of the same material as the gate electrode 142 and data link wires DLL2 , DLL4 made of the same material as the conductive layer 150 may be alternately disposed. However, it is not limited thereto.

Referring to FIG. 2 , the plurality of first contact holes CH1 contacted by each of the plurality of data lines DL and each of the plurality of data link lines DLL are power supply lines 130 of the plurality of gate lines GL. ) and is located between the gate line GL closest to the power supply line 130. Specifically, the plurality of first contact holes CH1 may be positioned above the uppermost wiring among the plurality of gate lines GL, that is, the gate line GL closest to the power supply line 130. . And, it may be located lower than the power supply wire 130 .

For example, each of the first data link wire DLL1 , the third data link wire DLL3 , and the fifth data link wire DLL5 made of the same material as the gate electrode 142 is formed by the first interlayer insulating layer 112 and Each of the plurality of data lines DL is connected through the plurality of first contact holes CH1 formed in the second interlayer insulating layer 113 . In addition, each of the second data link line DLL2 and the fourth data link line DLL of the same material as the conductive layer 150 includes a plurality of first contact holes CH1 formed in the second interlayer insulating layer 113. Through this, it is connected to each of the plurality of data lines DL. Since the plurality of first contact holes CH1 are positioned between the gate line GL closest to the power supply line 130 among the plurality of gate lines GL and the power supply line 130, the plurality of data link lines ( DLL) may not be formed in the same area as the plurality of gate lines GL.

In the case of a general display device, since the number of conductive layers is smaller than the number of wires in the non-display area, power supply wires cannot be disposed up to the non-display area corresponding to the deformed corner of the display area. Accordingly, the power supply wiring is disposed in the non-display area except for the deformed corner. Accordingly, the power supply voltage could be supplied only to the pixels disposed in the display area excluding the molded corner. Accordingly, in the case of the pixel disposed at the molded corner, the power supply voltage was supplied using a conductive layer different from that of the power supply wiring. Accordingly, a greater voltage drop may occur in the power supply voltage supplied to the pixel disposed at the irregular corner compared to the power supply voltage supplied to the pixel disposed in a region other than the irregular corner. As a result, the intensity of the power supply voltage supplied to the plurality of pixels is uneven, reducing the uniformity of luminance.

In the display device 100 according to an embodiment of the present invention, the width W1 of the power supply line 130 is greater than the distance D2 between the outermost power lines VDDL or the display area AA ) may be formed to be greater than the width W3 of the display area AA. Accordingly, luminance uniformity of the display device 100 may be improved. For example, when the width W1 of the power supply wiring 130 is smaller than the distance D2 between the outermost power wiring lines VDDL or smaller than the width W3 of the display device 100, the power supply wiring The plurality of power lines VDDL branching from 130 may not directly apply a high potential voltage to all of the plurality of pixels PX. That is, among the plurality of pixels PX, the pixel PX disposed at the corner cannot be directly connected to the plurality of power lines VDDL, and cannot be directly connected to the plurality of power lines VDDL from the power line VDDL disposed in the middle area excluding the corner area CA. The power supply voltage may be supplied through the branched wiring. Accordingly, a greater voltage drop may occur in the power supply voltage applied to the plurality of pixels PX disposed in the irregular corner than the power supply voltage applied to the plurality of pixels PX disposed in a region other than the irregular corner. Accordingly, luminance may be reduced compared to the pixel PX disposed in the center of the display area AA, and luminance uniformity of the entire display device 100 may be reduced. Therefore, in the display device 100 according to an embodiment of the present invention, the width W1 of the power supply line 130 is formed to be equal to or greater than the distance D2 between the outermost power lines VDDL, or the display area It may be formed to be equal to or larger than the width W3 of the display area AA to correspond to the entirety of (AA). Accordingly, the power line VDDL branched from the power supply line 130 may be directly connected to the pixel PX disposed at the corner, and the high potential power voltage may be supplied to all pixels PX. To this end, luminance uniformity of the entire display area AA may be improved.

Further, the display device 100 according to an exemplary embodiment of the present invention includes a plurality of second contact holes CH2 through which each of the plurality of first gate lines GL1 and each of the plurality of second gate lines GL2 contact each other. By being positioned outside the power supply line VDDL and the plurality of data lines DL, a high potential voltage can be supplied to all of the plurality of pixels PX. For example, as described above, as the power supply wiring 130 is formed long to correspond to the display area AA, the plurality of power supply wirings VDDL branching from the power supply wiring 130 may include a plurality of pixels ( PX) can supply high potential voltage. Accordingly, the outermost power line VDDL among the plurality of power lines VDDL may also be connected to the outermost pixel PX among the plurality of pixels PX. At this time, the second contact hole CH2 where each of the plurality of first gate lines GL1 and each of the plurality of second gate lines GL2 contact is inside the plurality of power lines VDDL and the plurality of data lines DL. , the plurality of first gate lines GL1 may be disposed in the same area as the plurality of power lines VDDL and the plurality of data lines DL. In this case, the plurality of first gate lines GL1 , the plurality of power lines VDDL, and the plurality of data lines DL are formed of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 . . Therefore, a problem may occur in that a plurality of power lines VDDL, a plurality of data lines DL, and a plurality of first gate lines GL1 are disposed in the same area. Accordingly, the display device 100 according to an exemplary embodiment of the present invention includes a plurality of second contact holes CH2 through which each of the plurality of first gate lines GL1 and each of the plurality of second gate lines GL2 contact each other. By being positioned outside the power supply line VDDL and the plurality of data lines DL of the pixel PX, a high potential voltage may be supplied to each of the plurality of pixels PX.

Also, in the display device 100 according to an exemplary embodiment of the present invention, some of the plurality of data link lines (DLL) are made of the same material as the gate electrode 142 and other parts are made of the same material as the conductive layer 150. . Accordingly, the area occupied by the plurality of data link lines (DLL) may be reduced. For example, when all of the plurality of data link wires (DLLs) are made of the same material and disposed on the same layer, due to limitations of the photoresist process for forming the plurality of data link wires (DLLs), between the respective data link wires (DLLs) The spacing of cannot be reduced to less than the minimum spacing. However, when some of the plurality of data link wires (DLL) are made of the same material as the gate electrode 142 and other parts are made of the same material as the conductive layer 150, the plurality of data link wires (DLL) are in different layers. can be placed. Accordingly, the distance between each data link line (DLL) may be smaller than the above-described minimum distance. Accordingly, the area occupied by the plurality of data link lines (DLL) can be reduced.

4 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view of Va-Va' and Vb-Vb' of FIG. 4 . Since the display device 400 shown in FIG. 4 is substantially the same as the display device 100 shown in FIGS. 1 to 3 except for the configuration of the plurality of gate lines GL being different, duplicate descriptions are omitted. or briefly described.

Referring to FIGS. 4 and 5 , the plurality of gate lines GL includes a plurality of first gate lines GL1 , a plurality of second gate lines GL2 , and a plurality of third gate lines GL3 .

The plurality of first gate lines GL1 refer to lines extending from the gate driver 120 among the plurality of gate lines GL. The plurality of first gate lines GL1 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 .

Also, the plurality of second gate lines GL2 refer to lines extending to the display area AA among the plurality of gate lines GL. The plurality of second gate lines GL2 may be made of the same material as the gate electrode 142 of the thin film transistor.

Further, the plurality of third gate lines GL3 means a wire connecting the plurality of first gate lines GL1 and the plurality of second gate lines GL2 among the plurality of gate lines GL. Some of the plurality of third gate lines GL3 may be made of the same material as the gate electrode 142 of the transistor 140 , and other parts may be made of the same material as the conductive layer 150 . For example, the plurality of third gate lines GL3 may include a third sub-gate line GL3a and a third sub-gate line GL3b. The third sub-gate line GL3a may be made of the same material as the gate electrode 142 of the transistor 140 , and the third sub-gate line GL3b may be made of the same material as the conductive layer 150 . For example, in the plurality of third gate lines GL3 , lines made of the same material as the gate electrode 142 of the transistor 140 and lines made of the same material as the conductive layer 150 may be alternately disposed.

In the display device 400 according to another embodiment of the present invention, some of the plurality of third gate lines GL3 (GL3a) are made of the same material as the gate electrode 142 of the transistor 140, and other portions (GL3b) is made of the same material as the conductive layer 150, so that the gate signal, the data signal, and the power signal can be stably supplied to each of the plurality of pixels PX. For example, when the positions of the plurality of first gate contact units C1 are disposed on the right side of the outermost data line DL or the outermost power line VDDL, unlike the positions shown in FIG. 4 , the plurality of data lines The wiring DL and the plurality of third gate wirings GL3 may overlap each other. If the plurality of third gate wires GL3 are made of the same material as the source electrode 143 and the drain electrode 144 of the plurality of transistors 140, the gate signal may overlap the data signal or the power signal, causing a problem. do. Accordingly, in the display device 400 according to another embodiment of the present invention, some of the plurality of third gate lines GL3 (GL3a) are made of the same material as the gate electrode 142 of the transistor 140, and other portions ( GL3b) is made of the same material as the conductive layer 150, so that gate signals, data signals, and power signals can be stably supplied to each of the plurality of pixels PX.

Referring to FIG. 4 , each of the plurality of first gate lines GL1 and each of the plurality of third gate lines GL3 may be electrically connected through each of the plurality of second contact holes CH2 . For example, the third sub-gate line GL3a and the first gate line GL1 are electrically connected through second contact holes CH2 formed in the first interlayer insulating layer 112 and the second interlayer insulating layer 113. can be connected to Also, the third sub-gate line GL3b and the first gate line GL1 may be electrically connected through the second contact hole CH2 formed in the second interlayer insulating layer 113 .

Referring to FIGS. 4 to 5 , each of the plurality of second gate lines GL2 and each of the plurality of third gate lines GL3 may be electrically connected through the plurality of first gate contact portions C1 . The plurality of first gate contact portions C1 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 . Among the plurality of third gate lines GL3, a line GL3a formed of the same material as the gate electrode 142 of the transistor 140 is provided in the first interlayer insulating layer 112 and the second interlayer insulating layer 113. It is electrically connected to the plurality of first gate contact units C1 through the formed contact holes. Among the plurality of third gate wires GL3, the wire GL3b formed of the same material as the conductive layer 150 passes through a contact hole formed in the second interlayer insulating layer 113 to form a plurality of first gate contact units C1. ) is electrically connected to

In addition, each of the plurality of third gate lines GL3 and each of the plurality of second gate lines GL2 and each of the lines GL3a having the same material as the gate electrode 142 of the transistor 140 are connected to a plurality of first gate contacts. It is also possible to form a single wire without using the portion C1. Further, each of the plurality of third gate lines GL3 and each of the plurality of second gate lines GL2 and each of the lines GL3b having the same material as the conductive layer 150 are formed through contact holes formed in the first interlayer insulating layer 112 . You can also connect via . In this case, the resistance of the plurality of third gate wires GL3 and the plurality of second gate wires GL2 formed of one wire is the resistance of the plurality of third gate wires GL3 connected by using the plurality of contact holes, respectively. The resistance of each wire GL3b and each of the plurality of second gate wires GL2 may be lower than that of the conductive layer 150 . When the variation in the resistance of each of the plurality of gate lines GL is large, the variation in the time for the gate signal to be transmitted to each of the plurality of pixels PX may increase, and thus driving stability of the display device 400 may deteriorate. have.

Therefore, in the display device 400 according to another embodiment of the present invention, each of the plurality of first gate contact portions C1 made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 is used. Since each of the plurality of second gate lines GL2 and each of the plurality of third gate lines GL3 are electrically connected, each of the plurality of gate lines GL is connected through the same number of contact holes. It is possible to minimize the resistance deviation between the gate lines GL of the . For example, when electrically connecting each of the plurality of third gate wires GL3 and each of the plurality of second gate wires GL2 using each of the plurality of first gate contact units C1, the plurality of gate wires ( GL) The variation of each resistance can be reduced. As a result, a variation in gate signal transmission speed between the plurality of gate lines GL can be minimized, and driving stability of the display device 400 can be increased.

Also, referring to FIG. 4 , the plurality of first gate contact units C1 may be positioned outside the plurality of power lines VDDL and the plurality of data lines DL. For example, the plurality of first gate contact portions C1 and the plurality of second contact holes CH2 may be positioned outside the outermost power line VDDL among the plurality of power lines VDDL. It may be positioned outside the outermost data line DL among the plurality of data lines DL.

Further, the plurality of first contact holes CH1, through which each of the plurality of data lines DL and each of the plurality of data link lines DLL make contact, are closest to the power supply line 130 among the plurality of gate lines GL. It is located between the gate line GL and the power supply line 130 . For example, the plurality of first contact holes CH1 may be located above the uppermost gate line GL among the plurality of gate lines GL, that is, the gate line GL closest to the power supply line 130. have. And, it may be positioned lower than the power supply wire 130 .

Therefore, in the display device 400 according to another embodiment of the present invention, the plurality of third gate lines GL3 and the plurality of data link lines DLL may be disposed in different regions. For example, the plurality of third gate lines GL3 include some lines GL3a made of the same material as the gate line GL of the transistor 140 and other lines made of the same material as the conductive layer 150 ( GL3b). In addition, the plurality of data link wirings include some wirings DLL1, DLL3, and DLL5 made of the same material as the gate wiring GL of the transistor 140 and other wirings DLL2, made of the same material as the conductive layer 150. DLL4). Therefore, the plurality of third gate lines GL3 and the plurality of data link lines DLL may not be disposed together in the same area of the non-display area NA. Accordingly, the plurality of third gate lines GL3 and the plurality of data link lines DLL may be disposed in different regions.

6 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention. Since the display device 600 shown in FIG. 6 has a different and substantially the same configuration of the plurality of gate lines GL compared to the display device 400 shown in FIGS. can explain

Referring to FIG. 6 , the plurality of first gate lines GL1 may be made of the same material as the conductive layer 150 or the gate electrode 142 of the transistor 140 . For example, the plurality of first gate lines GL1 may be made of the same material as the conductive layer 150 or the same material as the gate electrode 142 of the transistor 140 .

Further, each of the plurality of first gate lines GL1 may be in contact with each of the plurality of third gate lines GL3 using the plurality of second gate contact units C2 . The plurality of second gate contact portions C2 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140 . For example, when the plurality of first gate lines GL1 are made of the same material as the gate electrode 142 of the transistor 140, each of the plurality of first gate lines GL1 includes the first interlayer insulating layer 112 and Each of the plurality of second gate contact portions C2 may be electrically connected through contact holes formed in the second interlayer insulating layer 113 . Also, when the plurality of first gate lines GL1 are made of the same material as the conductive layer 150, each of the plurality of first gate lines GL1 passes through a contact hole formed in the second interlayer insulating layer 113 to form a plurality of first gate lines GL1. It may be electrically connected to each of the second gate contact portions C2.

Further, each of the portions GL3a of the third gate line GL3 made of the same material as the gate electrode 142 of the transistor 140 is formed on the first interlayer insulating layer 112 and the second interlayer insulating layer 113. It may be electrically connected to each of the plurality of second gate contact units C2 through the contact hole. Also, each of the other part GL3b of the third gate line GL3 made of the same material as the conductive layer 150 passes through a contact hole formed in the second interlayer insulating layer 113 to form a plurality of second gate contact units C2. ) can be electrically connected to each other.

In the display device 600 according to another embodiment of the present invention, each of the plurality of first gate lines GL1 and each of the plurality of third gate lines GL3 are connected through the plurality of second gate contact units C2. By connecting, resistance variation in the plurality of gate lines GL can be reduced.

For example, when the plurality of first gate lines GL1 are made of the same material as the gate electrode 142 of the transistor 140, the plurality of third gate lines are made of the same material as the gate electrode 142 of the transistor 140. Each of the part GL3a of GL3 and each of the plurality of first gate lines GL1 may be formed with the same wire. In addition, each of the plurality of third gate lines GL3 and each of the plurality of first gate lines GL1 and each of the plurality of third gate lines GL3 made of the same material as the conductive layer 150 are contact holes formed in the first interlayer insulating layer 112 . can be connected through

Further, when the plurality of first gate lines GL1 are made of the same material as the conductive layer 150, each of the plurality of third gate lines GL3 and the plurality of third gate lines GL3b made of the same material as the conductive layer 150. Each of the first gate wires GL1 may be formed of the same wire. Further, each of a portion GL3a of the plurality of third gate lines GL3 made of the same material as the gate electrode 142 of the transistor 140 may be connected through a contact hole formed in the first interlayer insulating layer 112 .

That is, for example, the first gate line GL1 and the third gate line GL3 include a part that is one line and another part that is two lines connected through a contact hole.

Accordingly, the display device 600 according to another embodiment of the present invention electrically connects each of the plurality of first gate lines GL1 and each of the plurality of third gate lines GL3 using a plurality of third gate contact units. By connecting to , it is possible to reduce the resistance deviation of the plurality of gate lines GL. Accordingly, the deviation of the transmission speed of the gate signal transmitted to each of the plurality of pixels PX can be minimized, and driving stability of the display device 600 can be increased.

7 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention. Since the display device 700 shown in FIG. 7 has a different and substantially the same structure of the power supply wiring 730 than the display device 100 shown in FIGS. can do.

Referring to FIG. 7 , the power supply wiring 730 extends to one end of the plurality of gate driving units 120 . In detail, the power supply wiring 730 is formed to correspond to the display area AA and may further extend to correspond to the deformed corner of the display area AA.

In the case of a general display device, since the number of conductive layers is smaller than the number of wires in the non-display area, power supply wires cannot be disposed up to the non-display area corresponding to the deformed corner of the display area. Accordingly, the power supply wiring is disposed in the non-display area except for the deformed corner. Accordingly, the power supply voltage could be supplied only to the pixels disposed in the display area excluding the molded corner. Therefore, in the case of the pixel disposed at the molded corner, the power supply voltage was supplied using a conductive layer different from the power supply wiring. Therefore, the high potential voltage was not applied to the pixels disposed at the molded corners. As a result, the intensity of the power supply voltage supplied to the plurality of pixels is uneven, reducing the uniformity of luminance.

Therefore, in the display device 700 according to another embodiment of the present invention, the power supply line 730 is formed to extend to one end of the plurality of gate driver 120, thereby providing a plurality of lines from the plurality of power lines VDDL. A drop phenomenon of a voltage supplied to the pixel PX may be reduced. For example, since the power supply wiring 730 extends to one end of the plurality of gate driver 120, each of the plurality of power supply wirings VDDL branching from the power supply wiring 730 forms a plurality of pixels PX. can be connected to each. Accordingly, in the display device 700 according to another exemplary embodiment of the present invention, the power supply line 730 is formed to extend to one end of the plurality of gate driving units 120, and thus a plurality of pixels PX disposed at the molded corners. ) can reduce the voltage drop phenomenon of the voltage supplied to Accordingly, each of the plurality of pixels PX may receive a high potential voltage, and thus, luminance uniformity of the display device 700 may be improved.

8 is an enlarged plan view of a display device according to another exemplary embodiment of the present invention. Since the display device 800 shown in FIG. 8 has a different gate driver 820 and a plurality of gate wires GL compared to the display device 100 shown in FIGS. 1 to 3 and is substantially the same, Redundant descriptions may be omitted or briefly described.

Referring to FIG. 8 , some 821 , 822 , and 823 of the plurality of stages 821 , 822 , 823 , 824 , and 825 included in the gate driving unit 820 are disposed to correspond to irregular corners of the display area AA. and supplies a gate signal to the gate line GL disposed in the region corresponding to the deformed corner among the plurality of gate lines GL. For example, the power supply wiring 130 may be arranged to correspond to the display area AA, and an area in which the power supply wiring 130 is not disposed may exist in the non-display area NA corresponding to the deformed corner. have. Accordingly, some 821 , 822 , and 823 of the plurality of stages 821 , 822 , 823 , 824 , and 825 may be disposed to correspond to irregular corners of the display area AA. Also, the gate driver 820 includes a first stage 821 to a fifth stage 825 . The first stage 821 to the third stage 823 are disposed in regions corresponding to the irregular corners of the display area AA. Also, the fourth stage 824 and the fifth stage 825 are disposed in areas not corresponding to the irregular corners of the display area AA. Each of the first stage 821 to the third stage 823 is connected to each of a plurality of first gate lines GL1 , and each of the plurality of first gate lines GL1 is connected to each of a plurality of second gate lines GL2 . connected with The first stage 821 to the third stage 823 transfer gate signals to each of the plurality of gate lines GL, and each of the plurality of gate lines GL to the plurality of pixels PX disposed at the irregular corner. A gate signal can be passed. In addition, the fourth stage 824 and the fifth stage 825 disposed in an area not corresponding to an anomaly corner transmit a gate signal to a pixel PX disposed in an area not corresponding to an anomaly corner through a gate line GL. can supply

In the display device 800 according to another embodiment of the present invention, some 821 , 822 , and 823 of the plurality of stages 821 , 822 , 823 , 824 , and 825 correspond to irregular corners of the display area AA. As such, a stable gate signal can be supplied to the plurality of pixels PX disposed at the irregular corners of the display area AA. For example, when some 821, 822, and 823 of the plurality of stages 821, 822, 823, 824, and 825 are arranged to correspond to the irregular corner of the display area AA, the ratio that does not correspond to the irregular corner The lengths of the plurality of gate lines GL connected to some of the plurality of stages 821 , 822 , 823 , 824 , and 825 821 , 822 , and 823 may be reduced compared to those disposed in the display area NA. . Also, the plurality of gate lines GL may be formed in a straight line. Therefore, the gate signal supplied from each of the plurality of stages 821, 822, and 823 disposed to correspond to the irregular corner of the display area AA can be stably supplied to each of the plurality of pixels PX disposed in the irregular corner. have.

Also, referring to FIG. 8 , the plurality of stages 821 , 822 , and 823 arranged to correspond to the deformed corners of the display area AA may be arranged in a stair shape. Also, it may be disposed adjacent to the display area AA. Specifically, the plurality of stages 821, 822, and 823 disposed to correspond to the irregular corners of the display area AA may be arranged in a stair shape along the irregular corners of the display area AA. It may be disposed adjacent to and corresponding to the shape of the deformed corner of the display area AA. For example, the plurality of stages 821 , 822 , and 823 may be disposed adjacent to the display area AA so as to correspond to the deformed corner, instead of being arranged in a line, and slightly staggered and stair-shaped. In the display device 800 according to another embodiment of the present invention, the plurality of stages 821, 822, and 823 arranged to correspond to the deformed corner are arranged in a stair shape, thereby forming a plurality of stages 821, 822, and 823. can be flexibly arranged to correspond to the deformed corners of various shapes. For example, when a corner of the display area AA has a partial circle shape as shown in FIG. 8 , the plurality of stages 821 , 822 , and 823 may be disposed in a stepwise manner corresponding to the corner. Accordingly, the corner of the non-display area NA may also be formed as a molded corner corresponding to the molded corner of the display area AA.

Also, referring to FIG. 8 , the plurality of stages 821 , 822 , and 823 arranged to correspond to the irregular corners of the display area AA may have a small width in a horizontal direction and a large width in a vertical direction. Specifically, the plurality of stages 821, 822, and 823 arranged to correspond to the molded corners of the display area AA are arranged to correspond to areas other than the molded corners of the display area AA, the fourth stage 824 And it may be formed in a shape different from that of the fifth stage 825 . For example, as shown in FIG. 8 , the plurality of stages 821, 822, and 823 arranged to correspond to the irregular corners of the display area AA may have a small width in the horizontal direction and a large width in the vertical direction. have. Accordingly, in the display device 800 according to another embodiment of the present invention, a plurality of stages 821, 822, and 823 having a small width in the horizontal direction and a large width in the vertical direction are deformed corners of the display area AA. By arranging to correspond to , a stage designed to correspond to the deformed corner of the display area AA may be disposed.

A display device according to embodiments of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display area having a shaped corner and a non-display area adjacent to the display area, a plurality of pixels in the display area and each including a transistor, and a plurality of pixels in the non-display area. , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, a plurality of gate wires in a non-display area, and extending in the same direction as the plurality of gate wires. A power supply wire and a plurality of power wire branched from the power supply wire and supplying a high potential voltage to a plurality of pixels may be included, and the gate driver may be located in an area other than the deformed corner.

According to another feature of the present invention, the width of the power supply wires in the direction in which the plurality of gate wires extend may be equal to or greater than the distance between the outermost power wires among the plurality of power wires.

According to another feature of the present invention, the power supply wiring may extend to one end of the plurality of gate driving units.

According to another feature of the present invention, a conductive layer between the source electrode and drain electrode of the transistor and the gate electrode of the transistor, a plurality of data wires parallel to the plurality of power supply wires, and supplying data signals to a plurality of pixels, and It is in the display area and further includes a plurality of data link wires for supplying data signals to the plurality of data wires, and the power supply wires and the plurality of power wires may be made of the same material as the source and drain electrodes of the transistor.

According to another feature of the present invention, the plurality of data lines are made of the same material as the source and drain electrodes of the transistors, some of the plurality of data link lines are made of the same material as the gate electrodes of the transistors, and other of the plurality of data link lines are made of the same material. Part of the material is the same as the conductive layer, and the contact hole through which each of the plurality of data wires and each of the plurality of data link wires is in contact may be located between the gate wire closest to the power supply wire and the power supply wire among the plurality of gate wires. .

According to another feature of the present invention, the plurality of gate wires extend from the gate driver and are connected to the plurality of first gate wires and the plurality of first gate wires made of the same material as the source electrode and the drain electrode of the transistor to form a display area. , and includes a plurality of second gate wires made of the same material as the transistor gate electrode, and a contact hole through which each of the plurality of first gate wires and each of the plurality of second gate wires contacts a plurality of power wires and a plurality of data wires. It can be located outside the wiring.

According to another feature of the present invention, the plurality of gate wires extend from the gate driver, and the plurality of first gate wires made of the same material as the conductive layer, the gate electrode of the transistor, or the source and drain electrodes of the transistor, the display area to connect a plurality of second gate wires, a plurality of first gate wires, and a plurality of second gate wires made of the same material as the gate electrode of the transistor, some of which are made of the same material as the gate electrode of the transistor, and some of them are of the same material as the gate electrode of the transistor. includes a plurality of third gate wires made of the same material as the conductive layer, and the display device further includes a plurality of first gate contact portions electrically connecting each of the plurality of second gate wires and each of the plurality of third gate wires. And, the first gate contact unit may be positioned outside the plurality of power lines and the plurality of data lines.

According to another feature of the present invention, the plurality of first gate contact units may be made of the same material as the source electrode and the drain electrode of the transistor, and may contact the plurality of second gate wires and the plurality of third gate wires through contact holes. have.

According to another feature of the present invention, when the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor, the plurality of gate wires are made of the same material as the source electrode and the drain electrode of the transistor, and form a contact hole. A plurality of second gate contact portions contacting the plurality of first gate wires and the plurality of second gate wires may be further included.

A display device according to another embodiment of the present invention includes a substrate including a display area having a shaped corner and a non-display area adjacent to the display area, a plurality of pixels in the display area and each including a transistor, and a plurality of pixels in the non-display area. , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, a plurality of gate wires in a non-display area, and extending in the same direction as the plurality of gate wires. A power supply wire and a plurality of power supply wires branched from the power supply wire and supplying a high potential voltage to a plurality of pixels, and the gate driver includes a plurality of stages for supplying gate signals to the plurality of gate wires. In addition, some of the plurality of stages are disposed to correspond to the molded corners, and gate signals may be supplied to gate wires disposed in regions corresponding to the molded corners among the plurality of gate wires.

According to another feature of the present invention, some of the plurality of stages may be arranged in a stair shape.

According to another feature of the present invention, some of the plurality of stages may have a smaller width in the horizontal direction and a larger width in the vertical direction than other parts of the plurality of stages arranged to correspond to areas other than the deformed corner.

According to another feature of the present invention, the molded corner may have a round shape.

A display device according to another embodiment of the present invention includes a substrate having a release corner and including a display area in which a plurality of pixels including transistors are defined and a non-display area adjacent to the display area, and release corners on both sides of the display area. and a gate driver formed in an area other than the deformed corner to minimize the area of the non-display area corresponding to , a power supply wire in the non-display area, and a plurality of power supply wires integrally formed with the power supply wire, wherein the power supply wire includes a plurality of power supply wires. It may be formed in an area corresponding to the entire display area to supply a power supply voltage to the pixels of .

According to another feature of the present invention, the width of the power supply wiring in the direction in which the plurality of gate wires extend may be greater than or equal to the width of the display area.

According to another feature of the present invention, the power supply wiring may extend to one end of the gate driver to reduce a drop in the power supply voltage.

According to another feature of the present invention, a plurality of data wires parallel to the plurality of power supply wires in the conductive layer between the source electrode and drain electrode of the transistor and the gate electrode of the transistor, and supplying data signals to a plurality of pixels, a plurality of It further includes a plurality of gate wires extending in a direction different from the data wires and a plurality of data link wires in the non-display area and supplying data signals to the plurality of data wires, wherein the power supply wires and the plurality of power wires are transistors It may be the same material as the source electrode and the drain electrode.

According to another feature of the present invention, the plurality of data lines are made of the same material as the source and drain electrodes of the transistors, some of the plurality of data link lines are made of the same material as the gate electrodes of the transistors, and others are made of the same material as the conductive layer. material, and the plurality of gate wires extend from the gate driver and are connected to the plurality of first gate wires and the plurality of first gate wires, which are the same material as the source electrode and the drain electrode of the transistor, and extend into the display area, and the transistor gate It includes a plurality of second gate wires made of the same material as the electrode, and a contact hole where each of the plurality of data wires and each of the plurality of data link wires contact each other, and each of the plurality of first gate wires and each of the plurality of second gate wires contact each other. The contact hole may be positioned such that the plurality of first gate wires are disposed in a region different from the plurality of data wires and the plurality of power supply wires.

According to another feature of the present invention, the plurality of data lines are made of the same material as the source and drain electrodes of the transistors, some of the plurality of data link lines are made of the same material as the gate electrodes of the transistors, and others are made of the same material as the conductive layer. material, and the plurality of gate wires extend from the gate driver and extend to a plurality of first gate wires and a display region of the same material as the conductive layer, the gate electrode of the transistor, or the source and drain electrodes of the transistor, A plurality of second gate wires of the same material as the gate electrode, connecting the plurality of first gate wires and the plurality of second gate wires, some of which are of the same material as the gate electrode of the transistor, and the other of which are of the same material as the conductive layer. The display device includes a plurality of third gate wires, and the display device electrically connects a contact hole through which each of the plurality of data wires and each of the plurality of data link wires contact each other, and each of the plurality of second gate wires and each of the plurality of third gate wires. A plurality of first gate contact units may be further included, and the first gate contact units may be positioned such that the plurality of data link wires and the plurality of third gate wires are disposed in different regions.

According to another feature of the present invention, the plurality of first gate contact units are made of the same material as the source electrode and the drain electrode of the transistor to minimize resistance variation in the plurality of gate wires, and the plurality of second gate contacts are formed through contact holes. wiring and a plurality of third gate wirings.

According to another feature of the present invention, when the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor, each of the plurality of gate wires is a plurality of first gate wires and each of a plurality of third gate wires. It further includes a plurality of second gate contact units for electrically connecting the plurality of second gate contacts, the plurality of second gate contacts are made of the same material as the source electrode and the drain electrode of the transistor to minimize the resistance variation in the plurality of gate wires, , and may contact the plurality of second gate wires and the plurality of third gate wires through the contact hole.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100, 400, 600, 700, 800: display device
110: substrate
111: gate insulating layer
112: first interlayer insulating layer
113: second interlayer insulating layer
120, 820: gate driver
121, 821: first stage
122, 822: second stage
130, 730: power supply wiring
140: thin film transistor
141: active layer
142: gate electrode
143: source electrode
144: drain electrode
150: conductive layer
823: third stage
824: fourth stage
825: 5th stage

Claims (21)

a substrate including a display area having a release corner and a non-display area adjacent to the display area;
a plurality of pixels in the display area including the shape corner, each including a transistor;
a gate driver in the non-display area and disposed on at least one side of the display area;
a plurality of gate wires electrically connected to the gate driver to supply gate signals to the plurality of pixels;
a power supply wire in the non-display area and extending in the same direction as the plurality of gate wires; and
a plurality of power supply wires branched from the power supply wires and supplying a high potential voltage to the plurality of pixels;
The non-display area includes at least two deformed corners,
The gate driver is located in an area excluding the deformed corner,
and a conductive layer between the source and drain electrodes of the transistor and the gate electrode of the transistor. According to claim 1,
A width of the power supply wires in a direction in which the plurality of gate wires extend is greater than or equal to a distance between outermost power wires among the plurality of power wires. According to claim 1,
The power supply wire extends to one end of the plurality of gate driving units. According to claim 1,
a plurality of data wires parallel to the plurality of power supply wires and supplying data signals to the plurality of pixels; and
a plurality of data link wires in the non-display area and supplying the data signals to the plurality of data wires;
The power supply wiring and the plurality of power wirings are made of the same material as a source electrode and a drain electrode of the transistor. According to claim 4,
The plurality of data wires are made of the same material as the source and drain electrodes of the transistor,
Some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and some of the plurality of data link wires are made of the same material as the conductive layer;
The display device of claim 1 , wherein a contact hole through which each of the plurality of data wires and each of the plurality of data link wires is in contact is located between a gate wire closest to the power supply wire and the power supply wire among the plurality of gate wires. According to claim 5,
The plurality of gate wires,
a plurality of first gate wires extending from the gate driver and made of the same material as the source and drain electrodes of the transistor; and
a plurality of second gate wires connected to the plurality of first gate wires to extend into the display area and made of the same material as a gate electrode of the transistor;
and a contact hole through which each of the plurality of first gate wires and each of the plurality of second gate wires contact each other is located outside the plurality of power supply wires and the plurality of data wires. According to claim 5,
The plurality of gate wires,
a plurality of first gate wires extending from the gate driver and made of the same material as the conductive layer, the gate electrode of the transistor, or the source and drain electrodes of the transistor;
a plurality of second gate wires extending into the display area and made of the same material as the gate electrode of the transistor; and
a plurality of third gate wires connecting the plurality of first gate wires and the plurality of second gate wires, some of which are made of the same material as the gate electrode of the transistor, and the other are made of the same material as the conductive layer; ,
The display device further includes a plurality of first gate contact units electrically connecting each of the plurality of second gate wires and each of the plurality of third gate wires,
The first gate contact unit is positioned outside the plurality of power lines and the plurality of data lines. According to claim 7,
The plurality of first gate contact portions are made of the same material as source and drain electrodes of the transistor, and contact the plurality of second gate wires and the plurality of third gate wires through contact holes. According to claim 7,
When the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor,
The plurality of gate wires,
and a plurality of second gate contact portions made of the same material as a source electrode and a drain electrode of the transistor and contacting the plurality of first gate wires and the plurality of second gate wires through contact holes. a substrate including a display area having a release corner and a non-display area adjacent to the display area;
a plurality of pixels in the display area, each including a transistor;
a gate driver in the non-display area and disposed on at least one side of the display area;
a plurality of gate wires electrically connected to the gate driver to supply gate signals to the plurality of pixels;
a power supply wire in the non-display area and extending in the same direction as the plurality of gate wires; and
a plurality of power supply wires branched from the power supply wires and supplying a high potential voltage to the plurality of pixels;
The gate driver includes a plurality of stages supplying gate signals to the plurality of gate lines,
Some of the plurality of stages are disposed to correspond to the molded corners, and supply gate signals to gate wires disposed in regions corresponding to the molded corners among the plurality of gate wires;
Among the plurality of stages, a stage arranged to correspond to an area of the deformed corner has a smaller width in a horizontal direction and a larger width in a vertical direction than some other stages arranged to correspond to an area excluding the deformed corner. According to claim 10,
Some of the plurality of stages are disposed in a stair shape. delete According to claim 10,
The irregular corner has a round shape. a substrate having at least two or more molded corners and including a display area in which a plurality of pixels equipped with transistors are defined, and a non-display area adjacent to the display area;
a gate driver formed in an area excluding the deformed corner to minimize an area of the non-display area corresponding to the deformed corner on both sides of the display area;
a power supply wire in the non-display area; and
Including a plurality of power supply wiring integrally formed with the power supply wiring,
The power supply wiring is formed in an area corresponding to the entire display area to supply a power voltage to the plurality of pixels;
A display device comprising a conductive layer between the source and drain electrodes of the transistor and the gate electrode of the transistor. According to claim 14,
A width of the power supply wiring in a direction in which the plurality of gate wires extend is greater than or equal to a width of the display area. According to claim 14,
The power supply wire extends to one end of the gate driver to reduce a drop in the power supply voltage. According to claim 14,
a plurality of data wires parallel to the plurality of power supply wires and supplying data signals to the plurality of pixels;
a plurality of gate wires extending in a direction different from that of the plurality of data wires; and
a plurality of data link wires in the non-display area and supplying data signals to the plurality of data wires;
The power supply wiring and the plurality of power wirings are made of the same material as a source electrode and a drain electrode of the transistor. According to claim 17,
The plurality of data wires are made of the same material as the source and drain electrodes of the transistor,
Some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and some are made of the same material as the conductive layer;
The plurality of gate wires,
a plurality of first gate wires extending from the gate driver and made of the same material as the source and drain electrodes of the transistor; and
a plurality of second gate wires connected to the plurality of first gate wires to extend into the display area and made of the same material as a gate electrode of the transistor;
A contact hole through which each of the plurality of data wires and each of the plurality of data link wires contact each other and a contact hole through which each of the plurality of first gate wires and each of the plurality of second gate wires contact each of the plurality of first gate wires wherein the wiring is disposed in a different area from the plurality of data wires and the plurality of power supply wires. According to claim 17,
The plurality of data wires are made of the same material as the source and drain electrodes of the transistor,
Some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and some are made of the same material as the conductive layer;
The plurality of gate wires,
a plurality of first gate wires extending from the gate driver and made of the same material as the conductive layer, the gate electrode of the transistor, or the source and drain electrodes of the transistor;
a plurality of second gate wires extending into the display area and made of the same material as the gate electrode of the transistor;
a plurality of third gate wires connecting the plurality of first gate wires and the plurality of second gate wires, some of which are made of the same material as the gate electrode of the transistor, and the other are made of the same material as the conductive layer; ,
The display device may include a plurality of first contact holes through which each of the plurality of data lines and each of the plurality of data link wires contact each other and electrically connecting each of the plurality of second gate wires and each of the plurality of third gate wires. Further comprising a gate contact unit,
The first gate contact unit is positioned so that the plurality of data link wires and the plurality of third gate wires are disposed in different regions. According to claim 19,
The plurality of first gate contact portions are made of the same material as the source electrode and the drain electrode of the transistor to minimize resistance variation in the plurality of gate wires, and the plurality of second gate wires and the plurality of gate contacts are formed through contact holes. A display device that contacts the third gate wiring. According to claim 20,
When the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor,
The plurality of gate wires further include a plurality of second gate contact portions electrically connecting each of the plurality of first gate wires and each of the plurality of third gate wires,
The plurality of second gate contact units are made of the same material as the source electrode and the drain electrode of the transistor to minimize resistance variation in the plurality of gate wires, and the plurality of second gate wires and the plurality of second gate wires and the plurality of gate contacts are formed through contact holes. A display device that contacts a plurality of third gate wires.

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