KR20190047565A - Display device - Google Patents

Abstract

The present invention relates to a display device. According to the present invention, the display device comprises: a substrate including a display region and a non-display region surrounding the display region; a plurality of pixels located in the display region, and each including a transistor; a gate driving part located in the non-display region and arranged so as to be adjacent to at least one side of the display region; and a blocking structure located in the non-display region and arranged between the outermost part of the gate driving part and the display region.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device including a structure that blocks moisture permeation into a display area by moisture permeation from a non-display area.

As the era of informationization becomes full-scale, the field of display devices for visually displaying electrical information signals is rapidly developing. Accordingly, various display devices have been developed and commercialized. For example, a liquid crystal display device (LCD), a field emission display device (FED), an electrophoretic display device (EPD), an electro-wetting display devices (EWDs), organic light emitting display devices (OLEDs), and quantum dot display devices (QDs).

In particular, the organic light emitting display device is a self light emitting display device, and unlike a liquid crystal display device, a separate light source is not required, and thus it can be manufactured in a light and thin shape. Further, the organic light emitting display device is advantageous not only in power consumption but also in response speed, viewing angle, and contrast ratio, and is being studied as a next generation display. However, in spite of these advantages, there is a disadvantage that the organic light emitting display device is particularly vulnerable to moisture and oxygen, so that it is difficult to secure reliability compared with other display devices.

The inventors of the present invention have recognized the problem that elements disposed in the display region are damaged by the moisture permeation from the lower portion of the substrate in the non-display region of the display apparatus. Specifically, foreign matter that may be present on the substrate in the non-display area or layers of inorganic materials disposed on the substrate in the non-display area due to an external impact may be cracked, Moisture and the like can be infiltrated. In addition, moisture penetrated from the bottom of the substrate in the non-display area can penetrate into the display area through the organic layer such as the planarizing layer, and the cathode of the organic light emitting device may be oxidized by such moisture .

Therefore, the inventors of the present invention have found that by separating a layer made of an organic material disposed in a non-display area and a layer made of an organic material disposed in the display area, A display device of a new structure has been invented.

A problem to be solved by the present invention is to provide a display device capable of preventing moisture permeation from a non-display area to a display area by disposing a structure separating a planarization layer of the non-display area from a planarization layer of the display area.

Another object of the present invention is to provide a display device capable of reducing parasitic capacitances between a structure and other conductive components arranged in a non-display area by applying a constant voltage to a structure blocking moisture permeation from a non- Device.

Another problem to be solved by the present invention is to provide a method of forming a low potential supply wiring electrically connected to a structure by forming a plurality of layers so as to overlap a structure blocking moisture permeation from a non- And to provide a display device capable of reducing a total resistance and supplying a stable low potential voltage to the entire display region.

Another object of the present invention is to provide a structure in which a low potential voltage is applied to a structure for suppressing moisture permeation disposed between an outermost portion of a gate driver of a non-display region and a display region, It is an object of the present invention to provide a display device capable of preventing an increase in the size of an additional bezel due to the arrangement of a structure that suppresses moisture permeation by simultaneously performing functions of wiring.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes a substrate including a display region and a non-display region surrounding the display region, a plurality of pixels each including a transistor in a display region, a non-display region, And a moisture-proof restraining structure disposed between the outermost portion of the gate driver and the display region in the gate driver and the non-display region arranged to be adjacent to at least one side. Thus, the planarization layer made of the organic material in the non-display area can be separated from the planarization layer disposed in the display area, so that the penetration of moisture from the non-display area to the display area can be suppressed.

A display device according to another embodiment of the present invention includes a substrate including a display region and a non-display region surrounding the display region, a planarization layer disposed in the display region and the non-display region, and a non- And a blocking structure disposed in the gate driver and the non-display area disposed on one side for isolating a portion of the flattening layer overlapping the gate driver and a portion disposed in the display area to block moisture permeation from the non-display area to the display area . Thus, the penetration of moisture into the display area can be suppressed, and the reliability of the display device can be improved.

The details of other embodiments are included in the detailed description and drawings.

The present invention can suppress the permeation of moisture from the non-display area to the display area and improve the reliability of the display device.

The present invention can reduce the formation of parasitic capacitors between structures and other conductive materials by applying a constant voltage to a structure that suppresses moisture permeation into the display area.

Further, the present invention can suppress the moisture permeation into the display area without increasing the size of the bezel area.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II-II 'of FIG.
3 is a cross-sectional view of a display device according to another embodiment of the present invention.
4 is a plan view of a display device according to another embodiment of the present invention.
5 is a cross-sectional view taken along line V-V 'of FIG.
6 is a plan view of a display device according to another embodiment of the present invention.
7 is a sectional view taken along line VII-VII 'of FIG.
8 is a cross-sectional view of a display device according to another embodiment of the present invention.
9 is a sectional view taken along line VII-VII 'of FIG. 6 according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer " on ", including both intervening layers or other elements directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II 'of FIG. 1 and 2, a display device 100 includes a substrate 110, a gate driver 120, a low-potential supply wiring 130, a blocking structure 140, and a pad region PA.

The substrate 110 is a substrate 110 for supporting and protecting various components of the display device 100. The substrate 110 may be made of glass, or plastic material having flexibility. When the substrate 110 is made of a plastic material, it may be made of, for example, polyimide (PI). However, it is not limited thereto.

The substrate 110 includes a display area AA and a non-display area NA surrounding the display area AA.

The display area AA is an area where the display device 100 displays an image, and various display elements and driving elements for driving the display elements are disposed in the display area AA. The display area AA includes a plurality of pixels PX. The plurality of pixels PX are in the display area AA and include elements such as the transistor 150 and the like. Each of the plurality of pixels PX is connected to the gate wiring GL, the data wiring DL, and the power supply wiring VDDL. The gate wiring GL is a wiring for transmitting a gate signal to the plurality of pixels PX and the data wiring DL is a wiring for transmitting a data signal to a plurality of pixels PX. And supplies the high potential voltage VDD to the pixel PX.

Referring to FIG. 2 for explaining the structure of each pixel PX of the display area AA, a transistor 150 is disposed on the substrate 110. FIG.

Specifically, an active layer 151 on which a channel of the transistor 150 is formed is formed on the substrate 110. The active layer 151 may be made of low temperature poly-silicon (LTPS) or an oxide semiconductor, but is not limited thereto. A gate insulating layer 111 is formed on the active layer 151. The gate insulating layer 111 is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), and may be a single layer or a plurality of layers thereof, but is not limited thereto.

A gate electrode 152 is formed on the gate insulating layer 111. The gate electrode 152 may be formed of a conductive material.

A first interlayer insulating layer 112 is formed on the gate electrode 152. The first interlayer insulating layer 112 is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), and may be a single layer or a plurality of layers thereof, but is not limited thereto.

A second interlayer insulating layer 113 is formed on the first interlayer insulating layer 112. The second interlayer insulating layer 113 is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) in the same manner as the first interlayer insulating layer 112, and may be a single layer or a plurality of layers thereof However, the present invention is not limited thereto.

The source electrode 153 and the drain electrode 154 of the transistor 150 may be formed on the second interlayer insulating layer 113. [ The source electrode 153 and the drain electrode 154 are electrically connected to the active layer 151 through the contact hole formed in the gate insulating layer 111, the first interlayer insulating layer 112, and the second interlayer insulating layer 113 Lt; / RTI > The source electrode 153 and the drain electrode 154 may be made of a conductive material and the source electrode 153 and the drain electrode 154 may be formed of the same material through the same process.

Although the transistor 150 is shown as a top gate type coplanar transistor in FIG. 2, the stacked structure of the transistor 150 is not limited thereto.

A conductive layer 160 is disposed between the first interlayer insulating layer 112 and the second interlayer insulating layer 113. For example, in the display device 100 according to an embodiment of the present invention, two interlayer insulating layers 112 and 113 may be used to provide an additional electric field between the first interlayer insulating layer 112 and the second interlayer insulating layer 113 The conductive layer 160 may be disposed between the source electrode 153 and the drain electrode 154 of the transistor 150 and the gate electrode 152 of the transistor 150 as the layer 160 is disposed. Accordingly, in the display device 100 according to an embodiment of the present invention, as the number of conductive patterns and wirings that can be additionally disposed increases, it can be realized as a display device of higher resolution, You may. Further, since the additional capacitor can be implemented using the conductive layer 160, the capacitance of the capacitor that can be used in the display device 100 may be increased.

Referring to FIG. 2, a planarization layer 114 is disposed on the transistor 150 and the second interlayer insulating layer 113. The planarization layer 114 may be an insulating layer for planarizing an upper portion of the transistor 150, and may be formed of an organic film layer.

In FIG. 2, the planarization layer 114 is shown as a single layer, and the planarization layer 114 may be formed as a double layer. When the planarization layer 114 is formed as a double layer, a connection electrode may be further formed on the lower layer of the planarization layer 114. The connection electrode may be formed on the drain electrode 154 of the transistor 150, Can be connected. An anode 171 is disposed on an upper layer of the planarization layer 114 and an anode 171 and a connection electrode can be connected to each other through a contact hole in an upper layer. Accordingly, the connection electrode formed on the lower layer of the planarization layer 114 can electrically connect the drain electrode 154 of the transistor 150 and the anode 171.

The organic light emitting device 170 is disposed on the planarization layer 114. The organic light emitting device 170 includes an anode 171 electrically connected to the drain electrode 154 of the transistor 150, an organic layer 172 disposed on the anode 171, and a cathode 173 formed on the organic layer 172. [ . When the display device 100 is a top emission type organic light emitting diode display, the anode 171 includes a reflective layer for reflecting the emitted light toward the cathode 173, and a transparent conductive layer for supplying holes to the organic layer 172. [ As shown in FIG. In FIG. 2, the organic layer 172 is formed by FMM (Fine Metal Mask) method and is patterned for each pixel PX in an organic layer for emitting light of a specific color such as green, blue, or red. However, The organic layer 172 may be formed throughout the display area AA.

A bank 115 is disposed on the anode 171 and the planarization layer 114. The bank 115 is a structure for distinguishing the adjacent pixels PX in the display area AA, and can define a plurality of pixels PX. The bank 115 may be made of an organic material.

Referring to FIG. 1, the non-display area NA is an area surrounding the display area AA adjacent to the display area AA. The non-display area NA is an area where no image is displayed, and wiring and a circuit part are formed. The pad region PA is a region where a plurality of pads are formed. The pad area PA is disposed on one side of the non-display area NA. The pad region PA is an area where a plurality of pads and an external module, for example, a chip on film (COF), are bonded. The low potential supply wiring 130, the gate driver 120, the blocking structure 140, and the pad area PA may be disposed in the non-display area NA.

1 and 2, the low potential supply wiring 130 is a wiring for applying a low potential voltage to the plurality of pixels PX. The low potential supply wiring 130 may be connected to a pad extending in the pad area PA disposed on one side of the non-display area NA and disposed in the pad area PA. 2, the low potential supply wiring 130 is electrically connected to the cathodes 173 of the plurality of pixels PX through the blocking structure 140 to apply a low potential voltage to the plurality of pixels PX . The low-potential supply wiring 130 may be the same material as the source electrode 153 and the drain electrode 154 of the transistor 150, but is not limited thereto.

When the planarization layer 114 is a double layer, an auxiliary blocking structure may be additionally formed on the lower layer of the planarization layer 114, and the auxiliary blocking structure may be connected to the low-potential supply wiring 130 through the contact holes of the lower layer. have. The blocking structure 140 is disposed on the upper layer of the planarization layer 114 and the blocking structure 140 may be connected to the auxiliary blocking structure through the contact holes of the upper layer. Accordingly, the auxiliary blocking structure formed on the lower layer of the planarization layer 114 can electrically connect the lower power supply wiring 130 and the blocking structure 140. The auxiliary blocking structure may be formed to overlap with the low potential supply wiring 130 and the blocking structure 140.

When the display apparatus 100 is a top emission type organic light emitting diode display, the cathode 173 may be formed of a transparent conductive oxide or a very thin metal thin layer to transmit light emitted from the organic layer 172. [ Therefore, the electrical resistance value of the cathode 173 can be high, a voltage drop phenomenon with respect to the low potential voltage at the cathode 173 can be generated, and the potential difference at the cathode 173 generated in the display region AA The quality of the image displayed by the display device may be degraded. Therefore, the low-potential supply wiring 130 can be arranged so as to surround the display area AA as shown in Fig. 1 to prevent a drop in the low potential voltage supplied to the plurality of pixels PX. However, the present invention is not limited thereto, and the low-potential supply wiring 130 may be disposed adjacent to at least one side of the display area AA.

The gate driver 120 is a circuit for supplying a gate signal to the pixel PX. The gate driver 120 may be disposed adjacent to both sides of the display area AA as shown in FIG. 1, but may be disposed adjacent to one side of the display area AA. The gate driver 120 can supply a gate signal to each pixel PX of the display area AA through the gate line GL.

The gate driver 120 may include a first sub gate driver 121 and a second sub gate driver 122. The low potential supply wiring 130 may be disposed between the first sub gate driver 121 and the second sub gate driver 122. In this case, the first sub-gate driver 121 may be disposed on one side of the low-potential supply wiring 130, and the second sub-gate driver 122 may be disposed on the other side of the low-potential supply wiring 130. 1 and 2, the first sub-gate driver 121 is disposed outside the low-potential supply wiring 130, and the second sub-gate driver 122 is connected to the low-potential supply wiring 130. [ The first sub gate driver 121 and the second sub gate driver 121 may be disposed adjacent to the display area AA.

The blocking structure 140 is a structure that blocks moisture permeation from the non-display area NA to the display area AA. The blocking structure 140 may prevent the out-gas generated in the flattening layer 114 located in the non-display area NA from diffusing from the non-display area NA to the display area AA have.

The auxiliary blocking structure formed on the lower layer of the planarization layer 114 in the case where the planarization layer 114 is formed of a double layer is configured to perform the permeation from the non-display area NA to the display area AA together with the blocking structure 140 And it is possible to prevent the out-gas generated in the planarization layer 114 located in the non-display area NA from diffusing from the non-display area NA to the display area AA.

The blocking structure 140 may be disposed between the outermost portion of the gate driver 120 and the display region AA. For example, the blocking structure 140 may be formed between the outermost portion of the gate driving portion 120 that is the farthest away from the display region AA and the region closest to the display region AA out of the non-display region NA Can be placed anywhere. For example, in the embodiment shown in FIGS. 1 and 2, the blocking structure 140 may be disposed between the first sub-gate driver 121 and the second sub-gate driver 122. That is, the first sub-gate driver 121 may be disposed on one side of the blocking structure 140, and the second sub-gate driver 122 may be disposed on the other side of the blocking structure 140. The blocking structure 140 may be disposed around the display area AA as shown in FIG. Accordingly, the display device 100 according to the embodiment of the present invention can effectively suppress the moisture permeation into the display area AA by the lower moisture permeation of the substrate 110 in the non-display area NA.

Referring to FIG. 2, the blocking structure 140 may be the same material as the anode 171 and may be electrically connected to the cathode 173.

In addition, a low potential voltage, that is, a constant voltage, may be applied to the blocking structure 140. [ Specifically, the blocking structure 140 may be electrically connected to the low-potential supply wiring 130 disposed over the blocking structure 140 through a contact hole formed in the planarization layer 114. Accordingly, the blocking structure 140 may be applied with a low potential voltage. Accordingly, the blocking structure 140 can electrically connect the low-potential supply wiring 130 and the cathode 173. A low potential voltage is applied to the blocking structure 140 by the low potential supply wiring 130 and a low potential voltage may be applied to the cathode 173 through the blocking structure 140 at the same time.

The contact hole formed in the planarization layer 114 for electrically connecting the blocking structure 140 and the low potential supply wiring 130 may extend around the display area AA. For example, the blocking structure 140 and the low-potential supply wiring 130 may be connected to each other by a contact hole extending and formed around the display area AA in correspondence with an area where the blocking structure 140 is disposed . Thus, the planarization layer 114 of the non-display area NA can be separated by the blocking structure 140. Therefore, the portion of the planarization layer 114 overlapping the first sub-gate driver 121 and the portion of the planarization layer 114 disposed in the display region AA can be separated. The planarization layer 114 located on the inner side and the planarization layer 114 located on the outer side with respect to the blocking structure 140 may be separated.

In the case where the planarization layer 114 is a double layer, a contact hole formed in a lower layer of the planarization layer 114 and a contact hole formed in an upper layer of the planarization layer 114 may be formed to extend around the display area AA. For example, the contact hole formed in the lower layer of the planarization layer 114 and the contact hole formed in the upper layer of the planarization layer 114 may be formed so as to surround the display area AA. The blocking structure 140 formed on the upper layer of the planarization layer 114 and the auxiliary blocking structure formed on the lower layer of the planarization layer 114 are overlapped and connected to each other and the auxiliary blocking structure formed on the lower layer of the planarization layer 114 The structure is overlaid and connected to the low power supply wiring 130. Accordingly, the planarization layer 114 of the non-display area NA can be separated by the barrier structure 140 and the auxiliary barrier structure. Therefore, the portion of the planarization layer 114 overlapping the first sub-gate driver 121 and the portion of the planarization layer 114 disposed in the display region AA can be separated.

The display device 100 according to an embodiment of the present invention can prevent the moisture permeation from the non-display area NA to the display area AA by disposing the blocking structure 140. [ For example, one or more inorganic layers may be included between the substrate 110 and the planarization layer 114. 2, the gate insulating layer 111, the first interlayer insulating layer 112, and the second interlayer insulating layer 113, which are disposed between the substrate 110 and the planarization layer 114, Layer. At this time, a crack may be generated in the inorganic material layer disposed between the substrate 110 and the planarization layer 114 due to an external impact applied to the display device 100. [ In addition, foreign matter may be formed during the deposition of at least one inorganic layer between the substrate 110 and the planarization layer 114, and cracks may be generated in the inorganic layer due to such foreign matter. Moisture can be generated from the bottom of the substrate 110 of the non-display area NA by a crack generated in the inorganic layer. At this time, the moisture introduced from the lower part of the substrate 110 in the non-display area NA may flow into the display area AA through the planarization layer 114. [ For example, the planarization layer 114 may be a layer made of an organic material, and the moisture introduced into the inorganic layer disposed under the planarization layer 114 may be introduced into the display area AA through the planarization layer 114 . Therefore, in the display device 100 according to the embodiment of the present invention, the blocking structure 140 includes the planarization layer 114 disposed in the non-display area NA and the planarization layer 114 disposed in the display area AA, Can be separated. The blocking structure 140 may be formed to surround the display area AA so that the flattening layer 114 may be separated from the blocking structure 140. Therefore, the moisture flowing into the lower portion of the substrate 110 in the non-display area NA can be suppressed from flowing into the display area AA through the planarization layer 114. [ Thereby, the reliability of the display apparatus 100 can be improved.

In the display device 100 according to an embodiment of the present invention, since a constant voltage is applied to the blocking structure 140, the parasitic capacitance between the blocking structure 140 and other conductive components arranged in the non- Can be reduced. For example, the blocking structure 140 may be coupled to the low-potential supply wiring 130, and a low potential voltage may be applied thereto. In this case, a plurality of conductive components may exist in the non-display area NA. A parasitic capacitor may occur between the blocking structure 140 and the conductive elements disposed in the non-display area NA when the blocking structure 140 is floating due to the application of a constant voltage. As such, the parasitic capacitor between the blocking structure 140 and the conductive material can interfere with signal transmission of various wirings disposed in the non-display area NA. Accordingly, in the display device 100 according to the embodiment of the present invention, since the constant voltage is applied to the blocking structure 140, parasitic capacitors between the blocking structure 140 and the conductive material disposed in the non-display area NA are reduced Thus, it can be prevented that the signal transmission of the wiring arranged in the non-display area NA is disturbed by the parasitic capacitor.

The planarization layer 114 may be formed of a plurality of planarization layers. For example, although the planarization layer 114 is shown as one layer in FIG. 2, the planarization layer 114 may be a plurality of layers. Since the planarization layer 114 is composed of a plurality of layers, an additional space necessary for arranging wiring or elements of the display device 100 can be secured.

3 is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 300 of FIG. 3 differs from the display device 100 of FIG. 1 to FIG. 2 in the structure of the low-potential supply wiring 330, and a description of substantially the same contents will not be repeated.

3, the low-potential supply wiring 330 includes a first layer 331, a second layer 332, and a third layer 333. The first layer 331, the second layer 332 and the third layer 333 may all overlap with the blocking structure 140. For example, the first layer 331 has substantially the same configuration as the low potential supply wiring 330 shown in FIG. That is, the first layer 331 is disposed between the second interlayer insulating layer 113 and the planarization layer 114 and is the same material as the source electrode 153 and the drain electrode 154 of the transistor 150. The first layer 331 may be electrically connected to the second layer 332 through a contact hole formed in the second interlayer insulating layer 113. The second layer 332 is disposed between the first interlayer insulating layer 112 and the second interlayer insulating layer 113 and is the same material as the conductive layer 160. The second layer 332 may be electrically connected to the third layer 333 through a contact hole formed in the first interlayer insulating layer 112. The third layer 333 is disposed between the gate insulating layer 111 and the first interlayer insulating layer 112 and is the same material as the gate electrode 152 of the transistor 150. In this case, the contact hole connecting the first layer 331 and the second layer 332 may be formed so as to surround the display area AA by overlapping the entire first layer 331. The contact hole connecting the second layer 332 and the third layer 333 may be formed so as to surround the display area AA by overlapping the entire second layer 332.

A contact hole connecting the first layer 331 and the second layer 332 and a contact hole connecting the second layer 332 and the third layer 333 extend around the display area AA And may include a plurality of contact holes which are not formed to extend around the entire display area AA but which connect the respective layers 331, 332, and 333.

Although the low potential supply wiring 330 of the display device 300 of FIG. 3 is shown as including both the first layer 331, the second layer 332 and the third layer 333, But may include at least two or more layers of the first layer 331, the second layer 332 and the third layer 333.

The display device 300 according to another embodiment of the present invention is characterized in that the low potential supply wiring 330 includes the first layer 331, the second layer 332 and the third layer 333, The total resistance of the wiring 330 can be reduced. When the first layer 331, the second layer 332 and the third layer 333 are overlapped and electrically connected to each other, the resistance of the entire low-potential supply wiring 330 is lower than the resistance of the first layer 331, (332) and the third layer (333). Since the first layer 331, the second layer 332 and the third layer 333 are connected in parallel, the resistance of the entire low-potential supply wiring 330 is reduced by the parallel connection of the resistors. The amount of voltage drop of the low potential voltage transmitted to the plurality of pixels PX of the display device 300 in the low potential supply wiring 330 can be reduced when the resistance of the entire low potential supply wiring 330 is reduced. For example, when the resistance of the entire low-potential supply wiring 330 is reduced, the difference in magnitude of the low-potential voltage at the position of each of the low-potential supply wirings 330 can be reduced. The magnitude of the low potential voltage measured at the portion of the low potential supply wiring 330 adjacent to the pad region PA is the same as the magnitude of the low potential voltage measured at the portion of the low potential supply wiring 330 that is not adjacent to the pad region PA It can be different in size. This may be caused by a drop in the low potential voltage due to the resistance of the low potential supply wiring 330. The display device 300 according to another embodiment of the present invention includes at least one of the first layer 331, the second layer 332, and the third layer 333 The total resistance of the low potential supply wiring 330 can be reduced. Thus, an even low potential voltage can be applied to the entire low potential supply wiring 330. Therefore, the difference in the magnitude of the low potential voltage supplied to the plurality of pixels PX of the display area AA can be reduced.

In some embodiments, the first layer 331 of the low potential supply wiring 330 is formed as one layer surrounding the display area AA while the second layer 332 of the low potential supply wiring 330 is formed as a single layer, And the third layer 333 are not formed as a single layer surrounding the entire display area AA but may include a plurality of patterns. For example, the second layer 332 may include a plurality of patterns that are the same material as the conductive layer 160, and may overlap the blocking structure 140 and surround the display area AA. The third layer 333 includes a plurality of patterns which are the same material as the gate electrode 152 of the transistor 150 and may be arranged to surround the display area AA in a superimposition manner with the blocking structure 140 . In this case, the gate line GL connected to the first sub-gate driver 121 located outside the low-potential supply line 330 of the gate driver 120 may be the same material as the conductive layer 160, The gate electrode 152 may be made of the same material as the gate electrode 152 of FIG. When the gate wiring GL connected to the first sub gate driver 121 is the same material as the conductive layer 160, the gate wiring GL should not be formed at the same position as the second layer 332. Accordingly, the second layer 332 includes a plurality of patterns arranged in regions except for the region where the gate line GL is disposed, and may be formed so as to overlap with the first layer 331. When the gate line GL connected to the first sub-gate driver 121 is the same as the gate electrode 152 of the transistor 150, the gate line GL is positioned at the same position as the third layer 333 . Therefore, the third layer 333 includes a plurality of patterns arranged in regions except for the region where the gate line GL is disposed, and may be formed in contact with the first layer 331. [ When the second layer 332 includes a plurality of patterns, a contact hole for electrically connecting the first layer 331 and the second layer 332 and a contact hole for electrically connecting the second layer 332 and the third layer 333 The contact hole for electrically connecting can not be formed to surround the entire display area AA, and thus may include a plurality of contact holes. When the third layer 333 includes a plurality of patterns, a contact hole for electrically connecting the second layer 332 and the third layer 333 may be formed to surround the entire display area AA It can include a plurality of contact holes.

4 is a plan view of a display device according to another embodiment of the present invention. 5 is a cross-sectional view taken along line V-V 'of FIG. The display device 400 of FIGS. 4 to 5 differs from the display device 100 of FIGS. 1 and 2 in the blocking structure 440 and the low-potential supply wiring 430, Duplicate descriptions are omitted.

4 to 5, the blocking structure 440 is disposed between the gate driver 420 and the display area AA. For example, the blocking structure 440 surrounds the display area AA and is arranged adjacent to the display area AA rather than the gate driving part 420.

The low potential supply wiring 430 includes a first low potential supply wiring 431 and a second low potential supply wiring 432. The first low-potential supply wiring 431 is disposed between the gate driver 420 and the display area AA. The first low potential supply wiring 431 overlaps with the blocking structure 440 and is disposed so as to surround the display area AA. The first low potential supply wiring 431 can supply a low potential voltage to the plurality of pixels PX of the display area AA.

The first low potential supply wiring 431 may be electrically connected to the blocking structure 440. For example, the first low-potential supply wiring 431 overlaps the blocking structure 440. [ In this case, the blocking structure 440 is electrically connected to the first low potential supply wiring 431 through the contact hole formed in the planarization layer 114. The blocking structure 440 may be electrically connected to the first low potential supply wiring 431 so that a low potential voltage, that is, a constant voltage may be applied. The first low potential supply wiring 431 is connected to the cathode 173 of the organic light emitting element 170 through the blocking structure 440. A low potential voltage is applied to the cathode 173 through the first low potential supply wiring 431 so that the first low potential supply wiring 431 can supply a low potential voltage to the plurality of pixels PX have. The contact hole connecting the first low-potential supply line 431 and the blocking structure 440 may be formed to surround the display area AA. For example, the blocking structure 440 and the first low-potential supply wiring 431 may be connected to each other by a contact hole surrounding the display area AA corresponding to a region where the blocking structure 440 is disposed. Therefore, the planarization layer 114 of the non-display area NA can be separated by the contact hole connecting the blocking structure 440 and the first low potential supply wiring 431. Therefore, the portion of the planarization layer 114 overlapping the gate driver 420 and the portion of the planarization layer 114 disposed in the display region AA can be separated. That is, the planarization layer 114 located on the inner side and the planarization layer 114 located on the outer side with respect to the contact hole connecting the blocking structure 440 and the first low potential supply wiring 431 may be separated.

Although the planarization layer 114 is shown as a single layer in FIG. 5, the planarization layer 114 may be formed of a double layer. When the planarization layer 114 is formed as a double layer, an auxiliary barrier structure may be further formed on the lower layer of the planarization layer 114. The auxiliary barrier structure may be formed on the lower low potential supply wiring 431 through the lower- Lt; / RTI > A blocking structure 440 is disposed on the upper layer of the planarization layer 114 and the blocking structure 440 may be connected to the auxiliary blocking structure through the contact holes of the upper layer. Accordingly, the auxiliary blocking structure formed on the lower layer of the planarization layer 114 can electrically connect the first low-power supply wiring 431 and the blocking structure 440. The auxiliary blocking structure may be formed so as to overlap with the first low potential supply wiring 431 and the blocking structure 440.

For example, when the planarization layer 114 is a double layer, the contact holes formed in the lower layer of the planarization layer 114 and the contact holes formed in the upper layer of the planarization layer 114 are extended and formed to surround the display area AA . For example, the contact hole formed in the lower layer of the planarization layer 114 and the contact hole formed in the upper layer of the planarization layer 114 may be formed so as to surround the display area AA. The blocking structure 440 formed in the contact hole of the upper layer and the auxiliary blocking structure formed in the contact hole of the lower layer are overlapped with each other and the auxiliary blocking structure formed in the contact hole of the lower layer of the flattening layer 114 is connected to the first low- And is connected to the supply wiring 431 in superposition with each other. Thus, the blocking layer 440 and the planarization layer 114 of the non-display area NA can be separated by the auxiliary blocking structure. A planarization layer 114 located on the inner side of the contact hole of the upper layer connecting the blocking structure 440 and the auxiliary blocking structure and a contact hole of the lower layer connecting the auxiliary blocking structure and the first low- And the planarization layer 114 located on the outer side can be separated.

Referring to FIG. 5, the second low potential supply wiring 432 is disposed outside the gate driver 420. The second low potential supply wiring 432 may be formed of the same material as the source electrode 153 and the drain electrode 154 of the transistor 150. Further, the second low potential supply wiring 432 may be electrically connected to the cathode 173 through the cathode connection part 450. The cathode connection portion 450 is disposed on the second low potential supply wiring 432 and the planarization layer 114 and may be the same material as the anode 171. [ The cathode connection portion 450 is disposed on the second low-potential supply wiring 432 and is disposed under the cathode 173.

In this case, the first low-potential supply wiring 431 and the second low-potential supply wiring 432 are electrically connected. The first low potential supply wiring 431 and the second low potential supply wiring 432 are electrically connected at one side of the non-display area NA of the display device 400, as shown in Fig. Therefore, the same low potential voltage can be applied to the first low potential supply wiring 431 and the second low potential supply wiring 432. [ The second low potential supply wiring 432 can supply a low potential voltage to the plurality of pixels PX of the display area AA.

When the planarization layer 114 is formed of a double layer, an auxiliary supply line may be additionally formed on the lower layer of the planarization layer 114, and an auxiliary supply line may be connected to the second low-potential supply line 432. A cathode connection portion 650 is disposed on the upper layer of the planarization layer 114 and a cathode connection portion 650 can be connected to the auxiliary supply wiring on the lower layer. Thus, the second low power supply wiring 432 can be electrically connected to the cathode connection portion 650 through the auxiliary supply wiring formed on the lower layer of the planarization layer 114.

The display device 400 according to another embodiment of the present invention is configured such that the blocking structure 440 is disposed between the gate driver 420 and the display area AA to thereby shift the display area AA from the non- And the out-gas can be more effectively blocked. In the case of the display device 400 of Figs. 4 to 5, the blocking structure 440 is disposed in the non-display area NA closest to the display area AA. For example, the blocking structure 440 may be disposed adjacent to the display area AA rather than the gate driving part 420, and no other structure may be disposed between the blocking structure 440 and the display area AA. As described above, cracks may be generated in the inorganic layer due to external impact applied to the display device 400 or foreign matter existing in the inorganic layer disposed between the substrate 110 and the planarization layer 114. Moisture can be generated from the lower part of the substrate 110 of the non-display area NA by the cracks generated in the inorganic layer and the introduced moisture flows into the display area AA through the planarization layer 114 made of organic material . In this case, the planarizing layer 114 may be a path of moisture inflow into the display area AA. Therefore, in the display device 400 according to another embodiment of the present invention, the blocking structure 440 is disposed in the non-display area NA closest to the display area AA, Can be blocked more effectively. The blocking structure 140 may prevent the out-gas generated in the flattening layer 114 located in the non-display area NA from diffusing from the non-display area NA to the display area AA have. Therefore, the blocking structure 440 can block the moisture permeation and out-gas from the non-display area NA located outside the blocking structure 440, thereby effectively suppressing the permeation of moisture into the display area AA . Thus, the reliability of the display apparatus 400 can be improved.

The display device 400 according to another embodiment of the present invention is configured such that a constant voltage is applied to the blocking structure 440 so that the parasitic capacitance between the blocking structure 440 and other conductive components arranged in the non- The capacitor can be reduced. Specifically, the blocking structure 440 may be connected to the first low potential supply wiring 431, and a low potential voltage may be applied thereto. As described above, when the blocking structure 440 is floated due to a non-constant voltage applied thereto, the blocking component 440 and the conductive components disposed in the non-display area NA can be operated as a capacitor. Accordingly, the display device 400 according to another embodiment of the present invention can be realized by applying a constant voltage, specifically a low potential voltage, to the blocking structure 440, thereby reducing the number of wirings disposed in the non-display area NA by the parasitic capacitor It may be blocked that signal transmission is disturbed.

The display device 400 according to another embodiment of the present invention is characterized in that the low potential supply wiring 430 includes a first low potential supply wiring 431 and a second low potential supply wiring 432, The low potential supply wiring 431 and the second low potential supply wiring 432 are electrically connected to each other, thereby reducing the drop of the low potential voltage. The first low potential supply line 431 and the second low potential supply line 432 may be electrically connected to each other on one side of the display device 400 as shown in FIG. In this case, the resistance of the first low potential supply wiring 431 and the resistance of the second low potential supply wiring 432 are connected in parallel. Therefore, the resistance of the entire low potential supply wiring 430 is reduced. When the resistance across the low potential supply wiring 430 is reduced, the drop in the low potential voltage due to the resistance can be reduced.

In some embodiments, each of the first low potential supply wiring 431 and the second low potential supply wiring 432 may include a first layer, a second layer and a third layer. Specifically, the first low-potential supply wiring 431 and the second low-potential supply wiring 432 are the first layer which is the same material as the source electrode 153 and the drain electrode 154 of the transistor 150, A second layer that is the same material as the first layer 160 and a third layer that is the same material as the gate electrode 152 of the transistor 150. The first layer, the second layer and the third layer are substantially the same as the first layer 331, the second layer 332 and the third layer 333 described in FIG. 3, and redundant description is omitted. In this case, each of the first low-potential supply interconnection 431 and the second low-potential supply interconnection 432 may not include both the first layer, the second layer and the third layer, and may include only some layers.

In the display device 400 according to another embodiment of the present invention, the first low-potential supply wiring 431 and the second low-potential supply wiring 432 are formed on the first layer, the second layer, and the third layer The total resistance of the low potential supply wiring 430 can be reduced. The first layer, the second layer and the third layer are connected in parallel, and the total resistance of each of the first low-potential supply interconnection 431 and the second low-potential supply interconnection 432 is reduced by the parallel connection of the resistors. Thus, the resistance of the entire low potential supply wiring 430 can also be reduced. When the resistance of the entire low potential supply wiring 430 is reduced, the amount of drop of the low potential voltage transmitted to the plurality of pixels PX of the display device 400 in the low potential supply wiring 430 can be reduced. Therefore, the uniformity of the low potential voltage of the low potential supply wiring 430 can be improved, and hence the low potential voltage supplied to the plurality of pixels PX can be more uniform.

6 is a plan view of a display device according to another embodiment of the present invention. 7 is a sectional view taken along line VII-VII 'of FIG. The display device 600 of Figs. 6 to 7 differs from the display device 100 of Figs. 1 and 2 in the low-potential supply wiring 630, and a duplicate description of substantially the same contents is omitted.

6 to 7, the low-potential supply wiring 630 includes a first low-potential supply wiring 631 and a second low-potential supply wiring 632. The first low potential supply wiring 631 is disposed between the first sub gate driver 121 and the second sub gate driver 122. The first low-potential supply wiring 631 overlaps with the blocking structure 140 and is disposed so as to surround the display area AA. The first low potential supply wiring 631 can supply a low potential voltage to the plurality of pixels PX of the display area AA.

The first low potential supply wiring 631 may be electrically connected to the blocking structure 140. For example, the first low potential supply wiring 631 overlaps the blocking structure 140. [ In this case, the blocking structure 140 is electrically connected to the first low potential supply wiring 631 through the contact hole formed in the planarization layer 114. The blocking structure 140 may be electrically connected to the first low potential supply wiring 631 to apply a low potential voltage, for example, a constant voltage. The first low-potential supply line 631 is connected to the cathode 173 of the organic light-emitting device 170 through the blocking structure 140. A low potential voltage is applied to the cathode 173 through the first low potential supply wiring 631 and therefore the first low potential supply wiring 631 can supply a low potential voltage to the plurality of pixels PX have.

The contact hole connecting the first low-potential supply line 631 and the blocking structure 140 may be formed to surround the display area AA. Specifically, the blocking structure 140 and the first low-potential supply wiring 631 may be connected to each other by a contact hole surrounding the display area AA corresponding to a region where the blocking structure 140 is disposed. Thus, the planarization layer 114 of the non-display area NA can be separated by the blocking structure 140. Therefore, the portion of the planarization layer 114 overlapping the first sub-gate driver 121 and the portion of the planarization layer 114 disposed in the display region AA can be separated. The planarization layer 114 located on the inner side and the planarization layer 114 located on the outer side are separated from each other with respect to the blocking structure 140. The second low potential supply line 632 is connected to the gate driver 120, As shown in Fig. The second low potential supply line 632 may be formed of the same material as the source electrode 153 and the drain electrode 154 of the transistor 150. Further, the second low potential supply wiring 632 may be electrically connected to the cathode 173 through the cathode connection portion 650. The cathode connection portion 650 is disposed on the second low potential supply wiring 632 and the planarization layer 114 and may be the same material as the anode 171. [ The cathode connection portion 650 is disposed on the second low potential supply wiring 632 and disposed under the cathode 173.

In this case, the first low-potential supply wiring 631 and the second low-potential supply wiring 632 are electrically connected. The first low potential supply line 631 and the second low potential supply line 632 are electrically connected in the non-display area NA of the lower region of the display device 600, as shown in FIG. Therefore, the same low potential voltage can be applied to the first low-potential supply interconnection 631 and the second low-potential supply interconnection 632. [ The second low potential supply wiring 632 can supply a low potential voltage to the plurality of pixels PX of the display area AA.

The sum of the width W1 of the first low potential supply wiring 631 and the width W2 of the second low potential supply wiring 632 is the minimum wiring May be equal to the width of For example, when the sum of the width W1 of the first low potential supply wiring 631 and the width W2 of the second low potential supply wiring 632 is reduced, the total resistance of the low potential supply wiring 630 Can be increased. When the total resistance of the low potential supply wiring 630 is increased, the amount of drop of the low potential supply voltage applied to the low potential supply wiring 630 can be increased, so that a plurality of pixels PX are provided with a uniform- The potential voltage may not be supplied. Therefore, the function of the low potential supply wiring 630 can be maintained only if the total resistance of the low potential supply wiring 630 does not exceed the specified value. Therefore, there may be a minimum wiring width for maintaining the function of the low potential supply wiring 630. [

Therefore, in the display device 600 according to another embodiment of the present invention, the sum of the width W1 of the first low-potential supply wiring 631 and the width W2 of the second low-potential supply wiring 632 is Is formed to be equal to the minimum wiring width for maintaining the function of the low potential supply wiring 630. Thus, the size of the non-display area NA, that is, the size of the bezel can be maintained without being increased. Then, the resistance of the entire low potential supply wiring 630 may not exceed the specific value described above. Thus, the function of the low potential supply wiring 630 for supplying the low potential voltage can be maintained. For example, the sum of the width W1 of the first low potential supply wiring 631 and the width W2 of the second low potential supply wiring 632 may be about 320 nm.

The width W2 of the second low potential supply wiring 632 may be the same as the minimum wiring width for maintaining the function of the low potential supply wiring 630. [ For example, the width W2 of the second low potential supply wiring 632 is equal to the minimum wiring width for maintaining the function of the low potential supply wiring 630, The width of the wiring can be increased by the width W1 of the low potential supply wiring 631. [ The total resistance of the low potential supply wiring 630 is a resistance due to the parallel connection of the resistances of the first low potential supply wiring 631 and the second low potential supply wiring 632. Therefore, the total resistance of the low potential supply wiring 630 may be lower than the maximum resistance value for maintaining the function of the low potential supply wiring 630. [

In the display device 600 according to another embodiment of the present invention, the width W2 of the second low potential supply wiring 632 is smaller than the minimum wiring width for maintaining the function of the low potential supply wiring 630 Respectively. Therefore, the size of the bezel can be increased by including the low-potential supply wiring 630 further including the first low-potential supply wiring 631. [ However, the barrier structure 140 that is electrically connected to the first low-potential supply wiring 631 can prevent the moisture permeation from the non-display area NA to the display area AA. The low potential supply wiring 630 includes the first low potential supply wiring 631 and the second low potential supply wiring 632 so that the total resistance of the low potential supply wiring 630 is smaller than that of the low potential supply wiring 630 may be lower than the maximum value of the total resistance. Therefore, the amount of drop of the low potential voltage in the low potential supply wiring 630 can be reduced. Therefore, a more uniform low potential voltage can be supplied to the plurality of pixels PX.

8 is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 800 of Fig. 8 differs from the display device 400 of Figs. 4 to 5 in the structure of the wiring connected to the blocking structure 440 and the structure of the low-potential supplying wiring 830, Redundant description is omitted.

8, the blocking structure 440 may be electrically connected to the source electrode 153 of the transistor 150. Referring to FIG. For example, the transistor 150 may be a driving transistor 150, and the source electrode 153 may be an electrode to which a high potential voltage is applied. That is, the source electrode 153 can be connected to the power supply line VDDL, and the high potential voltage is applied to the plurality of pixels PX by applying the high potential voltage to the source electrode 153 by the power supply line VDDL . In this case, the source electrode 153 may include a portion that extends into the non-display area NA and overlaps with the blocking structure 440. The blocking structure 440 may be electrically connected to the source electrode 153 through a contact hole formed in the planarization layer 114. Thus, a high-potential voltage, for example, a constant voltage, may be applied to the blocking structure 440.

In this case, the pixel PX shown in Fig. 8 may be a dummy pixel. The dummy pixel is a pixel PX disposed at the outermost portion of the display area AA and means a pixel PX that does not display an image. By including the dummy pixel in the display device 800, the light leakage phenomenon at the outermost part of the display area AA can be prevented. The blocking structure 440 may be electrically connected to the source electrode 153 of the dummy pixel disposed at the outermost portion of the display area AA so that a high potential voltage may be applied. Although the dummy pixels are described as being arranged in the display area AA in FIG. 8, the dummy pixels may be defined as being arranged in the non-display area NA instead of the display area AA. In addition, the pixel PX shown in FIG. 8 may be a dummy pixel, but is not limited thereto, and may be a pixel PX in which an image is displayed.

8, the low potential supply wiring 830 is disposed outside the gate driver 120. [ The low potential supply wiring 830 is disposed outside the gate driver 120 and surrounds the display area AA. The low potential supply wiring 830 may be formed of the same material as the source electrode 153 and the drain electrode 154 of the transistor 150. [ And may be electrically connected to the cathode 173 through the cathode connection part 450. The low potential supply wiring 830 can supply a low potential voltage to the plurality of pixels PX of the display area AA.

The display device 800 according to another embodiment of the present invention can be applied to the blocking structure 440 by applying a high potential voltage, The parasitic capacitances between the components can be reduced. For example, the blocking structure 440 may be connected to the source electrode 153 included in the pixel PX disposed at the outermost portion of the display area AA, and the source electrode 153 may be connected to the power supply line VDDL A low potential voltage is applied. Thus, the blocking structure 440 can be applied with a low potential voltage. When the blocking structure 440 is floated due to a non-constant voltage applied thereto, the blocking component 440 and the conductive components disposed in the non-display area NA can be operated as a capacitor. Accordingly, the display device 800 according to another embodiment of the present invention can be applied to a display device 800 that is arranged in the non-display area NA by the parasitic capacitor by applying a high-potential voltage, for example, a constant voltage to the blocking structure 440 It is possible to prevent the signal transmission of the wiring from being disturbed.

9 is a sectional view taken along line VII-VII 'of FIG. The sectional view of the display device 900 of FIG. 9 is different from the sectional view of the display device 600 of FIG. 7 in that the planarization layer 114 and the blocking structure 140 are formed as a double layer, The wiring 633 is additionally formed, and a duplicate explanation will be omitted for substantially the same contents.

9, the blocking structure 140 includes a first blocking structure 141 formed on the first planarization layer 116 and a second blocking structure 142 formed on the second planarization layer 117 . The first blocking structure 141 may be electrically connected to the first low potential supply line 631 through the contact hole of the first planarization layer 116. The second blocking structure 142 may be electrically connected to the first blocking structure 141 through the contact hole of the second planarization layer 117. Accordingly, the first low-potential supply line 631 is electrically connected to the second blocking structure 142 formed on the second planarization layer 117 through the first blocking structure 141 formed on the first flattening layer 116, . The second blocking structure 142 may be connected to the cathode 173 of the organic light emitting device 170. Therefore, the first low potential supply line 631 may be connected to the cathode 173 of the organic light emitting diode 170 through the first blocking structure 141 and the second blocking structure 142.

For example, the blocking structure 140 including the first blocking structure 141 and the second blocking structure 142 is electrically connected to the first low-potential supplying wiring 631 so that a low-potential voltage, that is, . The first low potential supply line 631 may be connected to the cathode 173 of the organic light emitting diode 170 through the blocking structure 140. A low potential voltage is applied to the cathode 173 through the first low potential supply wiring 631 and therefore the first low potential supply wiring 631 can supply a low potential voltage to the plurality of pixels PX have.

A contact hole connecting the first low potential supply line 631 and the first blocking structure 141 and a contact hole connecting the first blocking structure 141 and the second blocking structure 142 form a display area AA As shown in FIG. Accordingly, the contact hole of the first planarization layer 116 and the contact hole of the second planarization layer 117 may extend around the display area AA.

For example, the contact holes formed in the first planarization layer 116 and the contact holes formed in the second planarization layer 117 are formed so as to surround the display area AA, and the contact holes of the second planarization layer 117 The second blocking structure 142 formed in the hole and the first blocking structure 141 formed in the contact hole of the first flattening layer 116 are overlapped and connected to each other and the first blocking structure 142 formed in the contact hole of the first flattening layer 116 1 blocking structure 141 is connected to the first low power supply wiring 631 in a superposed manner. The first planarization layer 116 of the non-display area NA can be separated by the first barrier structure 141 and the second planarization layer 116 of the non-display area NA can be separated by the second barrier structure 142. [ Layer 117 can be separated.

Thus, the first planarization layer 116 and the second planarization layer 117 of the non-display area NA can be separated by the blocking structure 140. [ The first planarization layer 116 and the second planarization layer 117 overlapping the first subgate driver 121 and the first planarization layer 116 and the second planarization layer 116 disposed in the display area AA, The portion of layer 117 may be separated. The first planarization layer 116 and the second planarization layer 117 located on the inner side with respect to the blocking structure 140 and the first planarization layer 116 and the second planarization layer 117 located on the outer side with respect to the blocking structure 140 are separated . For example, the first planarization layer 116 located on the inner side and the first planarization layer 116 located on the outer side with respect to the first blocking structure 141 may be separated, and the second blocking structure 142 may be separated from the reference The first planarization layer 116 located on the inner side and the first planarization layer 116 located on the outer side may be separated.

9, the second low-potential supply line 632 formed on the second planarization layer 117 is connected to the cathode connection portion 632 through the auxiliary supply line 633 formed on the first planarization layer 116. [ (Not shown). The auxiliary supply wiring 633 may be electrically connected to the cathode 173 through the cathode connection portion 650. [ Therefore, the second low potential supply wiring 632 can be electrically connected to the cathode 173 through the auxiliary supply wiring 633 and the cathode connection portion 650.

For example, the auxiliary supply wiring 633 may be formed on the first planarization layer 116 and the second low potential supply wiring 632. The cathode connection portion 650 may be formed on the second planarization layer 117 and the auxiliary supply wiring 633. The cathode connection portion 650 may be the same material as the anode 171 and the auxiliary supply wiring 633 may be the same material as the first blocking structure 141. [ The cathode connection portion 650 may be disposed on the second planarization layer 117 and may be disposed under the cathode 173. The auxiliary supply wiring 633 may be disposed between the cathode connection portion 650 and the second low potential supply wiring 632.

In this case, the first low potential supply wiring 631 and the second low potential supply wiring 632 may be electrically connected. 6, the first low potential supply wiring 631 and the second low potential supply wiring 632 are electrically connected to each other in the non-display area NA of the lower region of the display device 600. [ Can be connected. Therefore, the same low potential voltage can be applied to the first low-potential supply interconnection 631 and the second low-potential supply interconnection 632. [ The second low potential supply wiring 632 can supply a low potential voltage to the plurality of pixels PX of the display area AA. 9, the drain electrode 154 of the transistor 150 is connected to the anode 115 formed on the second planarization layer 117 through the connection electrode 155 formed on the first planarization layer 116, As shown in FIG.

The first planarization layer 116 and the second planarization layer 117 may be formed of an organic layer formed of an organic material. The first planarization layer 116 and the second planarization layer 117 may be formed of a first organic layer and a second organic layer, which are made of different organic materials. The first planarization layer 116 and the second planarization layer 117 may be formed of a first organic layer and a second organic layer that are made of the same organic material.

The display device according to the embodiments of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display region and a non-display region surrounding the display region, a plurality of pixels in a display region, each of the pixels including a transistor, And a first blocking structure disposed in the non-display area and disposed between the outermost edge of the gate driving part and the display area.

According to another aspect of the present invention, the first blocking structure may be configured to be applied with a constant voltage.

According to another aspect of the present invention, the first blocking structure is disposed between the gate driver and the display region, and the high blocking voltage or the low blocking voltage may be applied.

According to still another aspect of the present invention, there is provided a display device including a plurality of dummy pixels disposed outside a display area, and a first blocking structure configured to apply a high-potential voltage through a plurality of dummy pixels.

According to another aspect of the present invention, the gate driver may include a first sub gate driver on one side of the first blocking structure and a second sub gate driver on the other side of the first blocking structure.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which further comprises a low-potential supply wiring disposed in a non-display area and outside the gate driver, have.

According to another aspect of the present invention, the organic light emitting display further includes a plurality of organic light emitting elements, each of which is disposed in the plurality of pixels and includes an anode, an organic layer, and a cathode, and the first blocking structure may be the same material as the anode.

According to another aspect of the present invention, the first blocking structure may be connected to the cathode.

According to still another aspect of the present invention, there is provided a semiconductor device, further comprising a planarization layer disposed between the first low-potential supply line and the first low-potential supply line and the first barrier structure overlapping the first barrier structure, Layer can be electrically connected to the first low-potential supply wiring through the contact hole in the layer.

According to still another aspect of the present invention, the gate driver may be disposed on both sides of the first low potential supply wiring.

According to still another aspect of the present invention, the semiconductor device may further include a second low potential supply wiring which is located outside the gate driver and connected to the first low potential supply wiring.

According to still another aspect of the present invention, there is provided a semiconductor device, further comprising a conductive layer between the source electrode and the drain electrode of the transistor and the gate electrode of the transistor, wherein each of the first low- And at least one of a first layer which is the same material as the drain electrode, a second layer which is the same material as the conductive layer, and a third layer which is the same material as the gate electrode of the transistor.

According to another aspect of the present invention, a transistor includes a gate electrode, a source electrode, and a drain electrode, and includes a planarization layer on the transistor, and the first barrier structure may be connected to the source electrode through a contact hole of the planarization layer. have.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a first low-potential supply interconnection overlapping a first interconnection structure; a first planarization layer on a first low-potential supply line; a second planarization layer on a first interconnection structure; And a second blocking structure on the second planarization layer.

According to another aspect of the present invention, the first blocking structure is connected to the first low potential supply wiring through the contact hole of the first planarization layer, and the second blocking structure is connected to the first blocking structure through the contact hole of the second planarization layer. Can be connected to the structure.

A display device according to another embodiment of the present invention includes a substrate including a display region and a non-display region surrounding the display region, a planarization layer disposed in the display region and the non-display region, and a non- And a blocking structure disposed in the gate driver and the non-display area disposed on one side for isolating a portion of the flattening layer overlapping the gate driver and a portion disposed in the display area to block moisture permeation from the non-display area to the display area .

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming at least one inorganic layer between a substrate and a planarizing layer in a non-display area, To block penetration into the display area through the substrate.

According to another aspect of the present invention, the blocking structure may be configured to apply a constant voltage to reduce a parasitic capacitor between the blocking structure and another conductive material disposed in the non-display area.

According to still another aspect of the present invention, the blocking structure is disposed between the gate driver and the display region, and can be configured to apply a high or low potential voltage.

According to still another aspect of the present invention, there is provided a semiconductor device comprising: a low-potential supply interconnection disposed below a planarization layer and connected to an interrupting structure, the interconnection structure interrupting a moisture permeation path through the planarization layer together with a low-

A display device according to another embodiment of the present invention includes: a substrate including a display region and a non-display region located adjacent to the display region; An organic film layer disposed in a display region and a non-display region of the substrate; A first sub gate driver arranged on at least one side of the display area in the non-display area; A second sub-gate driver disposed between the display region and the first sub-gate driver; A first power supply line disposed between the first sub-gate driver and the second sub-gate driver; And a blocking structure disposed on the organic film layer and connected to the first power source wiring through the contact hole of the organic film layer.

According to another aspect of the present invention, the organic film layer may include a first organic film layer disposed on the substrate and a second organic film layer disposed on the first organic film layer.

According to another aspect of the present invention, the blocking structure may include a first blocking structure disposed on the first organic film layer and a second blocking structure disposed on the second organic film layer, The first barrier layer may be connected to the first power supply line through the contact hole of the organic layer and the second barrier layer may be connected to the first barrier layer through the contact hole of the second organic layer.

According to another aspect of the present invention, the contact hole of the first organic film layer may be formed in a region overlapping with the first power supply wiring.

According to still another aspect of the present invention, the contact hole of the second organic film layer may be formed in a region overlapping the contact hole of the first organic film layer.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100, 300, 400, 600, 800: Display device
110: substrate
111: gate insulating layer
112: first interlayer insulating layer
113: second interlayer insulating layer
114: planarization layer
115: Bank
120, 420: Gate driver
121: first sub gate driver
122: second sub gate driver
130, 330, 430, 630, 830: low potential supply wiring
140, 440: blocking structure
150: transistor
151: active layer
152: gate electrode
153: source electrode
154: drain electrode
160: conductive layer
170: Organic light emitting device
171: anode
172: organic layer
173: Cathode
331: First Floor
332: Second layer
333: Third floor
431, 631: the first low potential supply wiring
432, 632: a second low potential supply wiring
450, 650: cathode connection
PA: pad area
AA: display area
NA: non-display area
PX: Pixels
VDDL: Power Wiring
DL: Data wiring
GL: gate wiring
W1: Width of the first low potential supply wiring
W2: Width of the second low potential supply wiring

Claims (20)

A substrate including a display region and a non-display region surrounding the display region;
A plurality of pixels in the display region, each pixel including a transistor;
A gate driver arranged in the non-display area and arranged to be adjacent to at least one side of the display area; And
And a first blocking structure disposed in the non-display region and disposed between the outermost portion of the gate driver and the display region. The method according to claim 1,
Wherein the first blocking structure is configured to apply a constant voltage. The method according to claim 1,
Wherein the first blocking structure is disposed between the gate driver and the display region, and is configured to apply a high-potential voltage or a low-potential voltage. The method of claim 3,
Further comprising a plurality of dummy pixels arranged outside the display area,
Wherein the first blocking structure is configured to apply a high potential voltage through the plurality of dummy pixels. The method according to claim 1,
Wherein the gate driver includes a first sub gate driver on one side of the first isolation structure and a second sub gate driver on the other side of the first isolation structure. The method according to claim 1,
And a low potential supply wiring disposed in the non-display region and outside the gate driver,
And the first blocking structure is configured to apply a low potential voltage from the low potential supply wiring. The method according to claim 1,
Further comprising a plurality of organic light emitting elements, each organic light emitting element being disposed in each of the plurality of pixels, the organic light emitting element including an anode, an organic layer, and a cathode,
Wherein the first blocking structure is the same material as the anode. 8. The method of claim 7,
And the first blocking structure is electrically connected to the cathode. The method according to claim 1,
A first low potential supply wiring overlapping with the first shield structure; And
Further comprising a planarizing layer between the first low potential supply line and the first blocking structure,
Wherein the first blocking structure is connected to the first low-potential supply wiring via a contact hole in the planarization layer. 10. The method of claim 9,
And the gate driver is disposed on both sides of the first low potential supply wiring. 10. The method of claim 9,
And a second low potential supply wiring which is outside the gate driver and is connected to the first low potential supply wiring. 12. The method of claim 11,
Further comprising a conductive layer between a source electrode and a drain electrode of the transistor and a gate electrode of the transistor,
Wherein each of the first low-potential supply line and the second low-potential supply line includes a first layer which is the same material as the source electrode and the drain electrode of the transistor, a second layer which is the same material as the conductive layer, And at least one of a third layer which is the same material. The method according to claim 1,
Further comprising a planarization layer on the transistor,
The transistor includes a gate electrode, a source electrode, and a drain electrode,
Wherein the first blocking structure is connected to the source electrode through a contact hole of the planarization layer. The method according to claim 1,
A first low potential supply wiring overlapping with the first shield structure;
A first planarization layer on the first low-potential supply line;
A second planarization layer on the first blocking structure; And
And a second blocking structure on the second planarization layer. 15. The method of claim 14,
Wherein the first blocking structure is connected to the first low potential supply wiring through a contact hole of the first planarization layer,
And the second blocking structure is connected to the first blocking structure through the contact hole of the second planarization layer. A substrate including a display region and a non-display region surrounding the display region;
At least one planarization layer disposed in the display region and the non-display region;
A gate driver disposed in the non-display area and disposed on at least one side of the display area; And
At least one block in the non-display region, which separates a portion of the at least one planarization layer that overlaps the gate driver and a portion of the display region, and blocks the moisture from the non-display region to the display region, Wherein the display comprises a structure. 17. The method of claim 16,
Further comprising at least one inorganic layer disposed between the substrate and the at least one planarization layer in the non-display area,
Wherein the at least one blocking structure is configured to block penetration of moisture penetrating from the bottom of the substrate into the display area through the at least one planarization layer as the inorganic layer cracks. 17. The method of claim 16,
Wherein the at least one blocking structure is configured to apply a constant voltage to reduce a parasitic capacitor between the blocking structure and another conductive material disposed in the non-display area. 17. The method of claim 16,
Wherein the at least one blocking structure is disposed between the gate driver and the display region, and is configured to apply a high-potential voltage or a low-potential voltage. 17. The method of claim 16,
Further comprising a low potential supply wiring disposed below said at least one planarization layer and connected to said at least one barrier structure,
Wherein the at least one blocking structure blocks the moisture permeation path through the at least one planarization layer with the low potential supply wiring.

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