KR102415865B1 - Narrow bezel display device - Google Patents

Abstract

By forming a pair of upper dams and lower dams and trenches at specific positions in the non-display area, the bezel width is reduced below a certain level, while at the same time controlling the spread of the sealant and the orientation material to overlap the sealant and the orientation material. to minimize In addition, the contact area between the sealant and the lower substrate is increased by the trench formed under the seal-region. Accordingly, it is possible to provide a display device in which adhesion between the upper substrate and the lower substrate is improved.

Description

NARROW BEZEL DISPLAY DEVICE {NARROW BEZEL DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, a sealant for bonding an upper substrate and a lower substrate from the outside is overlapped with a signal wiring region or a gate driver region, thereby reducing a bezel width. It relates to a display device.

A liquid crystal display device includes an upper substrate, a lower substrate, and a liquid crystal layer formed between the upper substrate and the lower substrate. An image is displayed by light passing through a liquid crystal layer whose orientation is controlled by an electric field applied to the liquid crystal display device. That is, the liquid crystal display device is a device in which the transmittance of light is adjusted by the alignment of the liquid crystal layer to display an image. A sealant is applied to a non-display area (or a bezel area) corresponding to the outer periphery of the display area of the display device so that the liquid crystal layer can be provided between the upper substrate and the lower substrate, and the upper substrate from the outer portion and the lower substrate.

In terms of design, a display device with a reduced bezel width has recently been in the spotlight. Accordingly, in order to reduce the width of the bezel in the display device, the industry continues to make efforts to reduce the area of the sealant for bonding the upper and lower substrates of the display device, that is, the seal region. have. However, since the area of the seal-region is proportional to the adhesive force between the upper substrate and the lower substrate, there is a limit to reducing the area of the seal-region. Since the seal-region should be designed to avoid an area made of a material with poor adhesion to the sealant or an area prone to breakage by external force, reducing the bezel by overlapping the circuit area of the seal-region and the non-display area is difficult. There are limits.

In addition, since the sealant may spread or overflow as it is applied to the upper substrate or the lower substrate in a fluid state, there is a limit in reducing the area of the seal-region.

In addition, when the sealant is made of a photocurable material, high energy light such as UV must be irradiated from the outside of the lower substrate toward the seal-region in order to harden the sealant. At this time, if the sealant is applied or spread to a portion of the circuit area where the metal wires are arranged with a dense density, the light does not reach the sealant by the metal wires that reflect the light, so that the sealant may not be cured. .

In addition, the alignment material for alignment of the liquid crystal layer may also spread or overflow as it is applied to the upper substrate or the lower substrate in a fluid state. When the applied orientation material spreads and invades the seal-region, the sealant and the orientation material unintentionally overlap. Since the adhesive force between the sealant and the alignment material is not good, as the overlapping area of the sealant and the alignment material increases, the adhesion between the upper substrate and the lower substrate decreases. Accordingly, a predetermined distance (or margin) is required between the seal-region and the area to which the orientation material is applied in order to prevent the applied orientation material from spreading and encroaching on the seal-region. The predetermined distance between the seal-region and the area to which the orientation material is applied causes an increase in the bezel width.

The present invention has been devised to solve the above-described problems in the prior art, and the narrow bezel display device according to the embodiment of the present invention improves the adhesion between the upper substrate and the lower substrate by overlapping the seal-region and the circuit region. It is an object of the present invention to provide a display device capable of reducing the bezel width to a certain level or less while simultaneously reducing the bezel width.

In addition, the narrow bezel display device according to the embodiment of the present invention configures a bumper capable of minimizing damage to the circuit region that may occur in the portion where the seal-region and the circuit region overlap, thereby An object of the present invention is to provide a display device in which corrosion or corrosion of metal wiring is reduced.

In addition, the narrow bezel display device according to an embodiment of the present invention reduces the bezel width to a certain level or less and at the same time controls the spread of the sealant and the spread of the orientation material, thereby minimizing the overlap of the sealant and the orientation material. The purpose is to provide a device.

In addition, in the narrow bezel display device according to the embodiment of the present invention, the contact area between the sealant and the lower substrate is widened by a trench formed in the lower portion of the seal-region or in the vicinity of the seal-region. An object of the present invention is to provide a display device in which adhesion between a substrate and a lower substrate is improved.

In addition, in reducing the bezel width of the display device, the seal-region and the specific circuit area avoid design, and without a separate independent processing process or addition of a mask, it is possible to prevent the failure of bonding between the upper substrate and the lower substrate and damage to the circuit under the sealant. An object of the present invention is to provide a display device with a high degree of freedom in design/process by providing a structure capable of reducing the occurrence of metal corrosion/corrosion.

In order to achieve the above object, the present invention includes an upper substrate and a lower substrate facing each other to interpose a liquid crystal, the upper substrate is provided with a plurality of upper spacers, and the lower substrate is provided with a plurality of lower spacers. A gate link unit and a gate driver on which a plurality of external signal wirings are disposed are provided at an outer portion of the substrate. The plurality of external signal lines and the gate driver are electrically connected by a plurality of bridge regions. In order to reduce the bezel, it is formed in a seal-region where a sealant is applied so as to overlap a portion of the region where the gate link portion and the gate driver are disposed, so that the upper substrate and the lower substrate are bonded to each other. In each of the plurality of bridge regions, the first metal layer and the second contact hole are formed above the first contact hole through which the first metal layer is exposed and the second contact hole is exposed through the second contact hole. A bridge electrode connecting the two metal layers is provided. The plurality of lower spacers formed on the lower substrate may include a lower spacer disposed at a position corresponding to the upper spacer and a lower spacer disposed to overlap with at least one bridge area among the plurality of bridge areas.

In addition, by forming a pair of upper dams and lower dams and trenches at specific positions in the non-display area, the bezel width is reduced below a certain level and at the same time, the spread of the sealant and the orientation material are controlled to control the spread of the sealant and the orientation material. to minimize the overlap of In addition, the contact area between the sealant and the lower substrate is increased by the trench formed under the seal-region.

According to an embodiment of the present invention, there is provided a display device divided into a display area for displaying an image and a non-display area around the display area, comprising: a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween; a sealant disposed in a non-display area between the first substrate and the second substrate to bond the first substrate and the second substrate to each other; an upper alignment layer and a lower alignment layer facing each other in a display area between the first substrate and the second substrate, which is a position for determining an initial alignment direction of the liquid crystal of the liquid crystal layer; a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area; an overlap prevention region including a lower dam rising from the first substrate toward the second substrate and an upper dam running from the second substrate toward the first substrate; and a trench region including a plurality of trenches to allow the sealant to flow in. In this case, the overlap prevention region and the trench region are disposed adjacent to the boundary between the touch wiring region and the gate driver and overlap each other.

In another aspect, according to an embodiment of the present invention, there is provided a display device divided into a display area for displaying an image and a non-display area around the display area, comprising: a first substrate; UV curing thruant disposed around the periphery of the display device; an alignment layer surrounded by a UV curing sealant; and a first structure disposed at a position to prevent overlapping of the UV curing sealant and the alignment layer in the non-display area to minimize the bezel width of the display device.

According to an embodiment of the present invention, it is possible to provide a display device capable of reducing the bezel width to a predetermined level or less while improving adhesion between the upper substrate and the lower substrate by overlapping the seal region and the circuit region.

In addition, according to an embodiment of the present invention, by configuring a bumper that can minimize damage to the circuit area that may occur in the portion where the seal-region and the circuit area overlap, corrosion or corrosion of the metal wiring due to the breakage of the circuit area It is possible to provide a display device in which the occurrence of

In addition, according to an embodiment of the present invention, it is possible to provide a display device in which the overlap of the sealant and the alignment material is minimized by reducing the bezel width below a certain level and at the same time controlling the spread of the sealant and the alignment material. .

In addition, according to an embodiment of the present invention, by the trench formed in the lower portion of the seal-region or in the vicinity of the seal-region, the contact area between the sealant and the lower substrate is increased, so that the adhesion between the upper substrate and the lower substrate is improved. A display device may be provided.

The effect of the present invention is not limited to the above-mentioned effects, and another effect not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description.

Since the content of the invention described in the problem to be solved above, the means for solving the problem, and the effect do not specify the essential characteristics of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

1 is a schematic plan view of a display device according to an embodiment of the present invention.
2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
3A to 3D are schematic plan and cross-sectional views illustrating an upper spacer and a lower spacer of a display device according to an exemplary embodiment of the present invention.
4A is an enlarged plan view of a portion of a non-display area of a display device according to an exemplary embodiment of the present invention.
FIG. 4B is a cross-sectional view of a corresponding region along a line extending from A to A' shown in FIG. 4A.
4C is a cross-sectional view of an enlarged portion of a non-display area of a display device according to an exemplary embodiment of the present invention, corresponding to FIG. 4B, showing another exemplary embodiment.
5 is a diagram schematically illustrating a non-display area of a display panel according to an embodiment of the present invention.
6 is a diagram schematically illustrating a non-display area of a display panel according to an exemplary embodiment of the present invention.
7A to 7H are plan views corresponding to the overlap prevention area shown in FIG. 5 .
8A to 8D are plan views corresponding to the anti-overlap region and the trench region shown in FIG. 5 .

Advantages and features of the present invention, and methods of achieving them, will become apparent with reference to the various embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the various embodiments disclosed below, but will be implemented in various different forms, and only these various embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the various embodiments may be independently embodied with respect to each other or may be practiced together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically showing a display device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of a display area of a display panel according to an embodiment of the present invention.

1 and 2 , the display device 10 includes a display panel 100 provided with a plurality of pixels P for outputting light. A portion provided with the plurality of pixels P is divided into a display area DA, and an outer periphery of the display area DA is divided into a non-display area NDA. When the display panel 100 is implemented as a liquid crystal panel, in the display panel 100 , the first substrate 110 and the second substrate 115 face each other and are spaced apart from each other by a predetermined interval. A liquid crystal layer LC filled with liquid crystal is formed to correspond to the display area DA between the spaced apart first and second substrates 110 and 115 . In this case, the first substrate 110 may be a TFT array substrate on which a plurality of thin film transistors (TFTs) are formed, and the second substrate 115 is a color filter layer ( CF) may be formed on a color filter substrate. Alternatively, the second substrate 115 may be a TFT array substrate on which a plurality of thin film transistors (TFTs) are formed, and the first substrate 110 may be a color filter layer CF corresponding to the plurality of pixels P. ) may be a color filter substrate formed thereon. Alternatively, the color filter layer CF and the TFT array may be formed together on one of the first substrate 110 and the second substrate 115 . A common electrode 140 and a pixel electrode 150 are provided on at least one of the first substrate 110 and the second substrate 115 . The alignment of the liquid crystal between the first substrate 110 and the second substrate 115 is controlled by a vertical or horizontal electric field formed by a difference in voltages respectively applied to the common electrode 140 and the pixel electrode 150 . .

In addition, the display device 10 includes a backlight unit disposed under the liquid crystal panel as a light source of the liquid crystal panel. In addition, the display device 10 includes various driving circuits for driving the liquid crystal panel. The driving circuit unit may be implemented on a printed circuit board (PCB). The driving circuit unit is connected to the gate pad unit G_Pad and the data pad unit D_Pad formed on one side of the outer side of the liquid crystal panel. The driving circuit unit drives the gate driver and the data driver of the liquid crystal panel.

1 and 2 , the first substrate 110 is divided into a display area DA and a non-display area NDA around it. A plurality of gate lines GL and data lines DL are disposed to cross each other in the display area DA, and each pixel P area defined by crossing the gate lines GL and data line DL A thin film transistor 130 is provided. For example, in the display panel 100 , N gate lines GL and M data lines DL cross to provide M*N pixels P. In some embodiments of the display panel 100 , a gate line GL or a data line DL may be shared between pixels P adjacent to each other. Accordingly, the display panel 100 may include a greater number of pixels P than M×N. The thin film transistor 130 provided in each pixel P region is connected to the gate line GL and the data line DL, is switched according to a gate signal applied to the gate line GL, and the data line DL. A data signal applied from the is supplied to the pixel electrode 150 . The pixel electrode 150 is connected to the thin film transistor 130 to form an electric field according to a data signal supplied from the thin film transistor 130 , and the liquid crystal alignment of the liquid crystal layer LC is adjusted by the formed electric field.

In FIG. 2 , three pixels P are illustrated in the display area DA of the display panel 100 for convenience of explanation. The thin film transistor 130 formed in each pixel P includes a gate electrode 131 , an active layer 132 , a first electrode 133 , and a second electrode 134 formed on a first substrate 110 . do. More specifically, a gate electrode 131 electrically connected to the gate line GL is formed on the first substrate 110 , and a gate insulating layer 121 is formed on the gate electrode 131 . An active layer 132 in which a channel is formed is formed on the gate insulating layer 121 , and the first electrode 134 and the pixel electrode 150 are electrically connected to the data line DL on the active layer 132 . An electrically connected second electrode 133 is formed. The active layer 132 may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like.

A planarization layer 122 is formed to cover the thin film transistor 130 on the first substrate 110 . The planarization layer 122 forms a flat surface on the thin film transistor 130 . The planarization layer 122 may be formed of an organic insulating material such as photo-acryl (PAC). A separate passivation layer PAS may be formed between the thin film transistor 130 and the planarization layer 122 . For example, the passivation layer PAS provided between the thin film transistor 130 and the planarization layer 122 may be formed of a silicon-based inorganic insulating material.

A common electrode 140 is formed on the planarization layer 122 . The common electrode 140 drives the liquid crystal by forming an electric field between the pixel electrode 150 and the pixel electrode 150 . In FIG. 2 , since the pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through a contact hole, it is as if the common electrode 140 is provided for each pixel P. shown as separated. However, the common electrode 140 is a common electrode of each pixel P in a portion other than a portion where the pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through a contact hole. Reference numeral 140 may be electrically connected to each other along a common electrode line through a separate contact hole.

In addition, although a separate common electrode 140 may be provided for each pixel P, a plurality of pixels P adjacent to each other may share one common electrode block. Accordingly, it is possible to realize the display panel 100 in which a touch is sensed by time-dividing one frame period of the screen and applying a signal for sensing a touch input to the common electrode line in one period. An individual common electrode line may extend from each common electrode block, and each common electrode line may be disposed to at least partially overlap the gate line GL or the data line DL. The common electrode line may be disposed on the thin film transistor 130 between the thin film transistor 130 and the common electrode block. Alternatively, the common electrode line may be disposed under the thin film transistor 130 . or,

When the common electrode line is disposed under the thin film transistor 130 , a high heat resistance planarization layer different from the planarization layer 122 formed on the thin film transistor 130 is formed between the common electrode line and the thin film transistor 130 . can be provided. For example, a plurality of common electrode lines are formed on the first substrate 110 , a silicon-based, high heat-resistance planarization layer (SOG) is formed on the common electrode line, and the high heat-resistance planarization layer is formed on the first substrate 110 . The thin film transistor 130 may be formed there.

The common electrode line may extend along a boundary between the display area DA and the non-display area NDA in the non-display area NDA to be connected to the touch driver by a touch wiring to be described later.

An insulating layer 123 for insulating the two electrodes is formed between the common electrode 140 and the pixel electrode 150 . The insulating layer 123 protects the common electrode 140 and forms a flat surface on the common electrode 140 . The insulating layer 123 may be formed of the same material as the planarization layer 122 or may be formed of the same material as the passivation layer PAS. That is, the insulating layer 123 may be the planarization layer 122 or the passivation layer PAS. Alternatively, the insulating layer 123 may be formed of an insulating material different from that of the passivation layer and the planarization layer 122 .

The pixel electrode 150 is electrically connected to the first electrode 133 of the thin film transistor 130 through a contact hole formed in the planarization layer 122 and the insulating layer 123 . The pixel electrode 150 and the common electrode 140 may be formed of a transparent conductive material such as indium tin oxide (ITO), and a horizontal electric field is formed in the pixel electrode 150 with the common electrode 140 . A plurality of slits may be formed to do so. However, this is only an example, and the structure and arrangement relationship between the common electrode 140 and the pixel electrode 150 is not limited thereto. Accordingly, in some embodiments, the common electrode 140 may be disposed on the pixel electrode 150 , or the pixel electrode 150 and the common electrode 140 may be disposed on the same layer. Also, in some embodiments, the common electrode 140 may be formed to have a plurality of slits instead of the pixel electrode 150 .

Referring to FIG. 2 , the second substrate 115 disposed to face the first substrate 110 is a color filter substrate of the display panel 100 . The second substrate 115 includes a black matrix BM and a color filter layer CF for partitioning a light blocking area and an opening area in the plurality of pixels P, respectively. An area in which the black matrix BM is formed is defined as a light blocking area, and an area in which the black matrix BM is not formed is defined as an opening area. Various driving devices and wirings such as the thin film transistor 130 , the data line DL and the gate line GL are formed in the light blocking area by the black matrix BM. A pixel electrode 150 and a common electrode 140 are formed in the opening region. Since FIG. 2 shows a cross-section cut along the gate line GL of the display panel 100 , the black matrix BM is continuously extended. That is, FIG. 2 shows a cross-sectional view in the light-shielding area. However, the black matrix BM is not formed in the opening region. As the black matrix BM is disposed between two adjacent pixels P, the black matrix BM is disposed to cover structures capable of reflecting external light, such as the lower data line DL and the thin film transistor 130 .

A plurality of color filters CF1 , CF2 , and CF3 are formed on the second substrate 115 to correspond to each pixel P of the display panel 100 . That is, the color filter layer CF includes color filters CF1 , CF2 , and CF3 . Specifically, the color filters CF1 , CF2 , and CF3 are formed to correspond to the opening regions of the red pixel R, the green pixel G, and the blue pixel B, respectively. A partial region of each of the color filters CF1 , CF2 , and CF3 may overlap the black matrix BM. In the embodiment shown in FIG. 2 , the black matrix BM is disposed closer to the second substrate 115 than the color filter layer CF. However, in some other embodiments, in order to reduce light leakage between adjacent pixels P, the color filter layer CF is disposed closer to the second substrate 115 than to the black matrix BM, and the black matrix (BM) may be disposed on the surface of the first substrate 110 .

An overcoat layer OC is formed on the second substrate 115 to cover the black matrix BM and the color filter layer CF. The overcoat layer OC is a layer for providing a flat surface to the second substrate 115 by covering the black matrix BM and the color filter layer CF. In addition, the overcoat layer OC prevents liquid crystal contamination by various pigments of the color filter layer CF. For example, the overcoat layer OC may be formed of an acrylic-based resin or an epoxy-based resin. Alternatively, the overcoat layer OC may be made of the same material as the planarization layer 122 .

A pad part PAD, a data link part D_Link, a gate link part G_Link, and a gate driver GIP are provided in the non-display area NDA of the first substrate 110 . The pad part PAD includes a data pad part D_Pad and a gate pad part G_Pad. The gate pad part G_Pad is formed on one side of the data pad part D_Pad and is connected to an external driving circuit part. The data pad part D_Pad may be formed on one side of the non-display area NDA of the first substrate 110 and may be connected to an external driving circuit part. Also, in the data pad part D_Pad, a data driver having an integrated circuit (IC) structure may be directly connected to the first substrate 110 in a chip-on-glass (COG) method.

In addition to the above-described data pad unit D_Pad and gate pad unit G_Pad, the pad unit PAD includes input/output of signals necessary for driving the pixel P of the display panel 100 or implementing various additional functions. Pads for this may be provided. For example, a common voltage pad connected to the common voltage generator of the driving circuit unit may be configured in the pad unit PAD. Alternatively, a touch sensor pad connected to a touch driver for performing a touch recognition function of the display panel may be configured in the pad unit PAD. The position of each pad part PAD is not limited to one side of the non-display area NDA, and may be configured on at least one side of an upper side, a lower side, a left side, and a right side of the non-display area NDA.

The data link part D_Link may include a data link line D_LL disposed between the data line DL disposed in the display area DA and the data pad part D_Pad to electrically connect each other. An external signal line to which various external signals for driving the gate driver GIP are supplied may be configured in the gate link unit G_Link. For example, as shown in FIG. 1 , the gate start signal line VST, the plurality of clock signal lines CLK1-4, the reset signal line RESET, the voltage lines VSS, VDD, VDD1, etc. are gated. It may be configured in the link unit (G_Link). Each external signal line of the gate link unit G_Link electrically connected to the gate pad unit G_Pad is connected to the gate driver through the connection line CL.

The gate driver may be configured by the thin film transistor 130 formed in the non-display area NDA of the first substrate 110 during the process of forming the thin film transistor 130 in the display area DA. The gate driver disposed on one substrate of the ZUG display panel may be configured in a gate-in-panel (GIP) method. The gate driver generates a gate signal and sequentially supplies it to the gate line GL disposed in the display area DA. To this end, the gate driver includes a plurality of stages ST connected to each of the gate lines GL. Accordingly, each external signal line of the gate link unit G_Link is selectively connected to each stage ST of the gate driver GIP through the connection line CL.

Each of the plurality of stages ST receives a clock supplied from any one of the plurality of clock signal lines CLK1 , CLK2 , CLK3 and CLK4 in response to the gate start signal line VST or a gate start signal supplied from the previous stage. The signal is applied as a gate signal. In addition, each of the plurality of stages ST supplies the applied gate signal to the gate line GL. Each of the plurality of stages ST sequentially operates the gate signal from the first gate line GL to the last gate line GL by sequentially operating according to the gate start signal line VST or the gate start signal supplied from the previous stage. or sequentially from the last gate line GL to the first gate line GL.

A sealant is applied to the edge of the first substrate 100 or the edge of the second substrate 115 along the non-display area NDA. The first substrate 110 and the second substrate 115 are bonded to each other to face each other in the display area DA with the liquid crystal layer LC interposed therebetween. Since the seal-region to which the sealant is applied and the non-display area NDA of the first substrate 110 are not areas in which an image is displayed, they are covered by the black matrix BM or the housing of the display device. do. In this case, the non-display area NDA covered by the black matrix BM or the housing is also referred to as a bezel. In order to reduce the width of the bezel, the seal-region to which the sealant is applied may overlap the circuit area in the non-display area NDA. That is, the seal-region may overlap a portion of the gate link portion G_Link, overlap a region in which the extension wiring CL is disposed, or may overlap a region in which a gate driver is formed.

In order to maintain a constant distance between the first substrate 110 and the second substrate 115 bonded by the sealant provided in the seal-region, there is a gap between the first substrate 110 and the second substrate 115 . A spacer is provided. The spacer may be configured on one surface of the first substrate 110 or on one surface of the second substrate 115 . When the display panel is subjected to an external force, the alignment of the first substrate 110 and the second substrate 115 is misaligned. In this case, when the spacer is formed on one surface of the first substrate 110 , the spacer may damage the alignment layer provided on the one surface of the second substrate 115 . Accordingly, an unintentional shift in the alignment of the liquid crystal occurs, and light leakage due to the shift in the alignment of the liquid crystal occurs. When the display panel displays a black image to the user, the leaking light is recognized as reddish, greenish, or blueish light corresponding to the position of the spacer. That is, the light leakage defect in the black image is caused by damage to the alignment layer by the spacer. In order to reduce a light leakage defect due to damage to the alignment layer due to the aforementioned spacer, the area of the black matrix BM that covers the spacer may be further enlarged and designed. However, in consideration of the high resolution and high aperture ratio in the display panel, it should be avoided to solve the light leakage problem by using the method of expanding the area of the black matrix BM. Accordingly, in the display panel 100 according to an embodiment of the present invention, a spacer is formed on one surface of the first substrate, and a spacer is formed on one surface of the second substrate to face the spacer corresponding thereto.

Referring to FIG. 2 , a plurality of upper spacers U_SP are disposed on the overcoat layer OC of the second substrate 115 between the first substrate 110 and the second substrate 115 . The upper spacer U_SP is disposed in the light blocking area where the black matrix BM is disposed. A plurality of lower spacers L_SP are disposed on the planarization layer 122 and the insulating layer 123 of the first substrate 110 between the first substrate 110 and the second substrate 115 . The lower spacer L_SP is disposed to face and face the upper spacer U_SP.

The heights of some of the plurality of spacers U_SP and L_SP respectively provided on the first substrate 110 and the second substrate 115 may be longer or shorter than those of other spacers U_SP and L_SP. That is, the length of each of the plurality of upper spacers U_SP may not be uniform. Also, the lengths of the plurality of lower spacers L_SP may not be uniform. For example, some of the upper spacers U_SP may be formed to have a longer height than others. In addition, the distance (or spacing) between the upper spacer U_SP and the corresponding lower spacer L_SP may also not be uniform.

A cell gap of the display panel 100 is fixed by some upper spacers U_SP having a longer height than the rest and a corresponding lower spacer L_SP. For example, the sum of the heights of the lower spacer L_SP and the corresponding upper spacer U_SP for maintaining the cell gap between the first substrate 110 and the second substrate 115 is the cell gap and can be the same. Accordingly, the upper surface of the lower spacer L_SP and the lower surface of the upper spacer U_SP corresponding thereto may contact each other.

Even if the cell gap of the display panel 100 is momentarily reduced when an external pressure is applied to the display panel 100 by the remaining upper spacer U_SP having a short height and the corresponding lower spacer L_SP, the cell gap is A decrease below a certain value is prevented.

3A to 3D are schematic cross-sectional views and plan views for explaining an upper spacer U_SP and a lower spacer L_SP provided in the display panel 100 according to various embodiments of the present disclosure. 3A to 3D , planarization is performed in a region where the gate line GL and the data line DL intersect on the first substrate 110 among the components of the display panel 100 described above for convenience of explanation. Only the layer 122 , the contact hole formed in the planarization layer 122 , the pixel electrode 150 , the upper spacer U_SP and the lower spacer L_SP are illustrated.

Referring to FIG. 3A , the upper spacer U_SP and the lower spacer L_SP are implemented in a bar shape. The bar-shaped upper spacer U_SP and the lower spacer L_SP may be formed in a light blocking area by the black matrix BM disposed along the gate line GL. The upper spacer U_SP overlaps the gate line GL and is formed to extend in the same direction as the extension direction of the gate line GL. The lower spacer L_SP disposed at a position corresponding to the upper spacer U_SP overlaps the data line DL on the first substrate 110 and extends in the same direction as the extension direction of the data line DL. In FIG. 3A , the upper spacer U_SP is formed to extend along the gate line GL in a range that does not go beyond (or does not pass through) the contact holes of two pixel P regions adjacent to each other. However, the upper spacer U_SP is not limited thereto, and may be formed to extend beyond (or exceed) the contact holes of the plurality of pixels along the gate line GL.

Referring to FIG. 3B , the upper spacer U_SP and the lower spacer L_SP are formed to correspond to the light blocking area by the black matrix BM disposed along the gate line GL. 3B , the upper spacer U_SP extends in the same direction as the extension direction of the data line DL and overlaps the data line DL. The lower spacer L_SP disposed at a position corresponding to the upper spacer U_SP extends in the same direction as the extending direction of the gate line GL on the first substrate 110 to overlap the gate line GL. When the first substrate 110 and the second substrate 115 are slightly shifted by the external pressure applied to the display panel 100 in the upper spacer U_SP, as the position of the upper spacer U_SP is changed, the upper spacer (U_SP) may be located on the contact hole. In this case, even after the external pressure applied to the display panel 100 is removed, the upper spacer U_SP may not be restored to its original position. Accordingly, a horizontal length or a vertical length of the upper spacer U_SP is formed so that the upper spacer U_SP is not caught in the contact hole. Accordingly, the upper spacer U_SP is not caught in the contact hole. That is, the upper spacer U_SP may be formed such that the horizontal length of the upper spacer U_SP is longer than the horizontal length of the contact hole or the vertical length of the upper spacer U_SP is longer than the vertical length of the contact hole.

Alternatively, as shown in FIG. 3B , the lower spacer L_SP may extend in the same direction as the extending direction of the gate line GL to cover the plurality of contact holes. The lower spacer L_SP may be formed in a line shape along the gate line GL and on the gate line GL. When the lower spacer L_SP is formed in a line shape on the gate line GL, it may be difficult to optimize the amount of liquid crystal between the first substrate 110 and the second substrate 115 . Accordingly, the lower spacer L_SP may be formed to cover only a predetermined number of contact holes adjacent to the lower spacer L_SP. That is, the lower spacer L_SP may not have a line shape. For example, the lower spacer L_SP may have a length that covers only two contact holes adjacent to the lower spacer L_SP.

The upper spacer U_SP and the lower spacer L_SP may be formed in a circular shape, different from the shape shown in FIGS. 3A to 3B . Referring to FIG. 3C , the upper spacer U_SP and the lower spacer L_SP are formed in a light blocking area by the black matrix BM disposed along the gate line GL. The upper spacer U_SP may be formed in a cone shape. At this time, the cone-shaped sharp portion faces the first substrate 110 from the second substrate 115 . The lower spacer L_SP opposite the upper spacer U_SP extends in the same direction as the extension direction of the gate line GL on the first substrate 110 and overlaps the gate line GL. In this case, the diameter of the lower spacer L_SP may be longer than that of the upper spacer U_SP corresponding to the lower spacer L_SP. That is, the circle area of the lower spacer may be wider than the circle area of the upper spacer U_SP corresponding to the lower spacer _SP. Additionally, as in the embodiment of FIG. 3B , the lower spacer L_SP may cover the contact holes of the plurality of pixels along the gate line GL or only two contact holes adjacent to the lower spacer L_SP.

3D is a cross-sectional view illustrating an example of a spacer (hereinafter, referred to as a push spacer) formed to have a shorter height than other spacers among a plurality of spacers. The push spacer serves to prevent the cell gap from being reduced below a certain level even if the cell gap is momentarily slightly reduced when an external force is applied to the display panel. 3D illustrates an upper spacer U_SP and a lower spacer L_SP serving as a push spacer. Meanwhile, FIGS. 3A to 3C illustrate an example of a spacer (hereinafter, a gap spacer) formed to have a longer height than other spacers among a plurality of spacers provided on the substrate. The gap spacer serves to fix the cell gap of the display panel. 3A to 3C illustrate an upper spacer U_SP and a lower spacer L_SP serving as a gap spacer. The distance between the upper spacer U_SP and the lower spacer L_SP serving as the push spacer is greater than the distance between the upper spacer U_SP and the lower spacer L_SP serving as the gap spacer. For example, the distance between the upper spacer U_SP serving as the gap spacer and the lower spacer L_SP may be 0 (zero). The upper spacer U_SP and the lower spacer L_SP serving as a push spacer are the same as the upper spacer U_SP and lower spacer L_SP serving as the gap spacer, the black matrix BM disposed along the gate line GL. ) is formed in the light-shielded area.

In FIG. 3D , the upper spacer U_SP and the lower spacer L_SP serving as a push spacer are disposed between contact holes of pixels adjacent to each other along the axis of the gate line GL. The upper spacer U_SP and the lower spacer L_SP serving as the push spacer are formed to have a smaller area than the upper spacer U_SP and the lower spacer L_SP serving as the gap spacer, respectively. One of the upper spacer U_SP and the lower spacer L_SP extends along the gate line GL axis and the other of the upper spacer U_SP and lower spacer L_SP serves as a push spacer along the data line DL axis. may be extended to In addition, the upper spacer U_SP and the lower spacer L_SP serving as the push spacer may be configured in such a way that the lower spacer L_SP extends along the gate line GL to cover two or more contact holes.

The upper spacer U_SP and the lower spacer L_SP may be formed of the same material or may be formed of different materials. When the lower spacer (L_SP) and the upper spacer (U_SP) are formed of the same material, the friction coefficient, elasticity, and restoring force before and after external pressure are the same between the lower spacer (L_SP) and the upper spacer (U_SP). In designing the upper spacer U_SP and the lower spacer L_SP, an optimal height, width, and arrangement relationship can be easily set. However, the equipment for producing the upper spacer (U_SP) configured in the production line of the second substrate 115 is also provided in the production line of the first substrate 110, or the first substrate 110 is moved to various production lines. There may be difficulties in manufacturing.

The upper spacer U_SP and the lower spacer L_SP may be formed of an organic material or an inorganic material. In terms of adjusting the height and shape of the spacer, it may be relatively easier to form the upper spacer U_SP and the lower spacer L_SP using an organic material. For example, the upper spacer U_SP and the lower spacer L_SP may be formed of an organic material such as photo acryl (PAC) or polyimide (PI). In order to secure a separation distance between the upper spacer U_SP and the alignment layer on the second substrate 115 , the height of the lower spacer L_SP may be 4000 Å or more.

According to the structure and arrangement relationship of the above-described upper spacer U_SP and lower spacer L_SP, the upper spacer U_SP and the lower spacer L_SP do not contact the alignment layer even when an external force is applied to the display panel 100 . . Accordingly, it is possible to prevent light leakage due to liquid crystal distortion due to damage to the alignment layer. Accordingly, it is possible to prevent light leakage defects without widening the width of the black matrix BM, so that the display panel 100 having a high aperture ratio and high resolution can be realized.

4A to 4B are diagrams schematically illustrating a non-display area NDA of the display panel 200 according to an embodiment of the present invention. 4A is an enlarged plan view of a portion of the gate link part G_Link and the gate driver GIP included in the non-display area NDA on the first substrate 110 . FIG. 4B is a cross-sectional view schematically illustrating a non-display area NDA of the display panel 200 along a line extending from point “A” to point “A’” illustrated in FIG. 4A .

Referring to FIG. 4A , a gate link part G_Link in which a plurality of external signal wirings are formed is formed on the outer side of the first substrate 110 , and a gate is formed on the display area DA side with respect to the gate link part G_Link as a reference. The driver (GIP) is located. As in various embodiments of the present disclosure, when the gate driver GIP is implemented with the thin film transistor 130 formed on the first substrate 110 , the gate link unit G_Link and the gate are formed on the first substrate 110 . Simultaneously with the formation of the driver GIP, a connection line CL for transmitting an external signal applied from an external signal line formed on the gate link part G_Link to the gate driver GIP is formed. The connection line CL may be positioned between the gate link part G_Link and the gate driver GIP or may be formed across the gate link part G_Link and the gate driver GIP.

As shown in FIG. 4A , the connection line CL extends toward the gate driver GIP across the plurality of external signal lines. Accordingly, the external signal wiring and the connection wiring CL of the gate link part G_Link are composed of different conductive layers, and an insulating layer is formed between the conductive layer in which the external signal wiring is formed and the conductive layer in which the connection wiring CL is formed. This may be interposed. Accordingly, the connection line CL may be connected to the selective external signal line and may extend to the gate driver GIP side across the other external signal lines. A plurality of bridge areas BRA are provided in the display panel 100 for electrical connection between two different conductive layers.

4B exemplarily shows a connection structure of one of the above-described various external signal wirings for convenience of explanation. Referring to FIG. 4B , the external signal wiring is formed of a first metal layer M1 and the connection wiring CL is formed of a second metal layer M2, and one or more insulating layers are formed between the external signal wiring and the connection wiring CL. This is interposed.

For example, the external signal wiring may be formed of a metal layer forming the gate electrode 131 of the thin film transistor 130 formed on the first substrate 110 . In addition, the connection wiring CL may be formed of a metal layer (S/D Metal) forming the source/drain electrodes 133 and 134 of the thin film transistor 130 . In this case, the first metal layer M1 may be a metal layer forming the gate electrode 131 of the thin film transistor 130 formed on the first substrate 110 , and the second metal layer M2 may be It may be a metal layer (S/D Metal) forming the source/drain electrodes 133 and 134 of the thin film transistor 130 .

Alternatively, the external signal wiring may be formed of a metal layer (S/D Metal) forming the source/drain electrodes 133 and 134 of the thin film transistor 130 formed on the first substrate 110 . In addition, the connection wiring CL may be formed of a metal layer forming the gate electrode 131 of the thin film transistor 130 . In this case, the gate insulating layer 121 may be interposed between the external signal wiring and the connection wiring CL. In this case, the first metal layer M1 may be a metal layer (S/D Metal) forming the source/drain electrodes 133 and 134 of the thin film transistor 130 formed on the first substrate 110 , The second metal layer M2 may be a metal layer forming the gate electrode 131 of the thin film transistor 130 .

Alternatively, the external signal wiring may be formed of the same conductive layer as the gate line GL, and the connection wiring CL may be formed of the same conductive layer as the data line DL. In addition, one or more insulating layers may be interposed between the external signal wiring and the connection wiring CL. In this case, the first metal layer M1 may be the same conductive layer as the gate line GL, and the second metal layer M2 may be the same conductive layer as the data line DL.

Alternatively, the external signal wiring may be formed of the same conductive layer as the data line DL, and the connection wiring CL may be formed of the same conductive layer as the gate line GL. In addition, the same insulating layer as the insulating layer interposed between the gate line GL and the data line DL in the display area DA may be interposed between the external signal wiring and the connection wiring. In this case, the first metal layer M1 may be the same conductive layer as the data line DL, and the second metal layer M2 may be the same conductive layer as the gate line GL.

At least one insulating layer may also be provided on the external signal wiring and the connection wiring CL. For example, as shown in FIG. 4B , a passivation layer PAS and a planarization layer 122 as insulating layers may be formed on the external signal wiring and the connection wiring CL. In order to electrically connect the external signal wiring and the connection wiring CL formed of different conductive layers, a contact area of each of the external signal wiring and the connection wiring CL is formed in the insulating layer on the external signal wiring and the connection wiring CL. A contact hole to be exposed is formed. A bridge electrode BRL is formed on the contact area of the external signal line and the contact area of the connection line CL to simultaneously contact the contact area of the external signal line and the contact area of the connection line CL. The bridge electrode BRL electrically connects the external signal line and the connection line CL.

On the contact hole exposing the contact region of the first metal layer M1 and the second metal layer M2, the bridge electrode BRL extends to contact the contact region of each conductive layer at the same time, so that the first metal layer M1 and the second metal layer M1 and the second metal layer M2 are simultaneously contacted. A region electrically connecting the two metal layers M2 is referred to as a bridge region BRA.

Similarly, the signal input terminal of each stage ST of the gate driver GIP may also be formed of a conductive layer different from that of the connection wiring CL. For example, as shown in FIG. 4B , the signal input terminal S_In of the gate driver GIP may be formed of the same conductive layer as the conductive layer forming the external signal wiring. In this case, in the insulating layer covering the connection wiring CL and the signal input terminal S_In of the gate driver GIP, a contact hole exposing a part of the gate driver GIP side of the connection wiring CL and the gate driver GIP ), a contact hole exposing a part of the signal input terminal S_In is formed. The contact area of the connection wiring CL located on the side of the gate driver GIP and the contact area of the signal input terminal S_In of the gate driver GIP also have a bridge area BRA connecting the connection wiring CL and the external signal wiring. are connected to each other in the same structure as Accordingly, the external signal applied from the external signal wiring is transmitted to the gate driver GIP. That is, through the contact hole of the insulating layer covering the external signal wiring and the connection wiring CL, the first metal layer M1 forming the external signal wiring located below the insulating layer and the second forming the connection wiring CL are formed. A plurality of bridge electrode BRL patterns in contact with the metal layer M2 are formed on the gate link portion G_Link.

Also, as shown in FIG. 1 , a signal applied from the driving circuit unit is transferred to the data driver or a data signal output from the data driver provided in the data pad unit D_Pad in a COG method is transferred to a data line arranged in the display area DA. The data link wiring D_LL for transferring to the DL also connects the bridge electrode BRL formed on the respective corresponding contact hole like the connection wiring CL formed between the external signal wiring and the gate driver GIP. can be electrically connected through. Accordingly, not only the plurality of bridge regions BRA may be provided around the gate link part G_Link and the gate driver GIP, but also the non-display regions other than the regions around the gate link part G_Link and the gate driver region A plurality of bridge areas BRA may also be formed in the NDA). For example, the bridge area BRA may also be applied to the pad portion PAD illustrated in FIG. 1 .

As described above, in order to realize a narrower bezel width and to reinforce the adhesion between the first substrate 110 and the second substrate 115 at the same time, the seal-region is formed in the non-display area NDA. The gate link part G_Link or the gate link part G_Link and the gate driver GIP may overlap. In addition, the sealant may be applied on the bridge area BRA to cover the partial bridge area BRA. However, the bridge electrode BRL formed in the bridge area BRA may be formed of a material having poor adhesion to the sealant. For example, a bridge electrode (BRL) formed of indium tin oxide (ITO) may not only have poor adhesion to the sealant, but may also be easily cracked by an external force transmitted through the cured sealant. In other words, even if the sealant is provided to extend to a portion of the gate driver GIP, adhesion failure between the first substrate 110 and the second substrate 115 may occur due to weakening of the adhesive force between the sealant and the bridge electrode BRL. can occur In addition, when a crack occurs in the bridge electrode BRL overlapping the sealant, foreign substances penetrate through the crack to cause corrosion/corrosion of metal wires under the bridge electrode BRL.

Accordingly, in the display panel 200 according to the embodiment of the present invention, some of the plurality of lower spacers L_SP formed on the first substrate 110 correspond to the bridge area BRA of the first substrate 110 . and a lower spacer L_SP formed at the position. In other words, some of the lower spacers L_SP provided on the first substrate 110 are formed to cover the bridge electrode BRL located in the non-display area NDA. As shown in FIGS. 4A and 4B , the lower spacer L_SP disposed on the bridge area BRA may be provided such that one individual lower spacer L_SP covers one bridge area BRA. . In FIG. 4B , the lower spacer L_SP covering the bridge electrode BRL electrically connecting the external signal line and the connection line CL is formed to fill the contact hole formed so that the bridge electrode BRL comes into contact with the contact area. is formed Similarly, in the lower spacer L_SP covering the bridge electrode BRL that electrically connects the connection line CL and the signal input terminal S_In of the gate driver GIP, the bridge electrode BRL is in contact with the contact region. It is formed to fill the formed contact hole.

The lower spacer L_SP disposed in the non-display area NDA and covering the bridge area BRA is made of the same material as the lower spacer L_SP disposed in the display area DA and disposed to correspond to the upper spacer U_SP. formed in the same process. Accordingly, the lower spacer L_SP disposed in the non-display area NDA and covering the bridge area BRA and the lower spacer L_SP disposed in the display area DA may be formed to have the same height. However, since structures formed between the first substrate 110 and the second substrate 115 may be different in the display area DA and the non-display area NDA, respectively, they are disposed in the non-display area NDA. and the lower spacer L_SP covering the bridge area BRA and the lower spacer L_SP disposed in the display area DA may be formed to have different heights if necessary. For example, the lower spacer L_SP formed in the non-display area NDA to cover the bridge area BRA may also affect the cell-gap between the first substrate 110 and the second substrate 115 . have. Accordingly, the lower spacer L_SP covering the bridge area BRA may be formed to have a lower height than the lower spacer L_SP formed in the display area DA. As another example, in terms of protection of the bridge area BRA, it is preferable to form the lower spacer L_SP covering the bridge area BRA to be higher than the lower spacer L_SP formed in the display area DA. It may be more preferable. In order to have the lower spacer L_SP covering the bridge area BRA and the lower spacer L_SP disposed in the display area DA have different heights, a half-tone mask may be used.

In FIG. 4B , the lower spacer L_SP covering the bridge electrode BRL of the bridge area BRA is illustrated as being covered with a sealant. However, as described above, the seal-region Seal may overlap a portion of the gate link portion G_Link, and the remaining portion of the gate link portion G_Link may not overlap the seal-region Seal. Also, even if the seal area overlaps the entire area of the gate link part G_Link, some bridge areas BRA provided in the gate driver GIP may be located outside the seal area. can That is, the bridge area BRA may be provided even where the seal area does not overlap the seal, and the lower spacer L_SP is also provided on the bridge area BRA which does not overlap the seal area. may be available.

As shown in FIG. 4B , when the lower spacers L_SP are locally formed in each bridge area BRA located under the sealant, due to the step difference by the lower spacer L_SP, the Staining may occur. In order to reduce a step difference caused by the lower spacers L_SP in the seal area, one lower spacer L_SP may be disposed to cover the plurality of bridge areas BRA.

FIG. 4C is a cross-sectional view schematically illustrating a display panel 300 including lower spacers L_SP disposed to extend on a plurality of bridge areas BRA, according to an exemplary embodiment of the present invention. Referring to FIG. 4C , a bridge region BRA connects the external signal wiring and the connection wiring CL to each other, and a bridge region BRA connects the connection wiring CL to the signal input terminal S_In of the gate driver GIP. It is covered by this single lower spacer L_SP. As described above, as one lower spacer L_SP is formed to correspond to the plurality of bridge areas BRA, a step difference due to the lower spacer L_SP disposed under the sealant may be reduced.

The lower spacer L_SP disposed in the non-display area NDA extends not only to the two bridge areas BRA located at both ends of the connection line CL, but also to other bridge areas BRA in the vicinity of the two or more bridge areas. (BRA) may be formed to cover. In consideration of adhesiveness between the material forming the lower spacer L_SP and the sealant, the lower spacer L_SP of the non-display area NDA may cover a portion or the entire surface of the gate link part G_Link in a single pattern or It may be formed to cover a part or the entire surface of the driver GIP. For example, the lower spacer (L_SP) is formed of a material such as photo acryl (PAC) or polyimide (PI), and the bridge electrode (BRL) is formed of indium tin oxide (ITO). When formed, the lower spacer L_SP has better adhesion to the sealant than the bridge electrode BRL. Accordingly, the lower spacer L_SP of a single pattern having a constant area in proportion to the area of the seal-region, rather than the lower spacer L_SP that locally covers each bridge area BRA in a 1:1 ratio, is used in the gate link part. Disposing over G_Link and the gate driver GIP may be more advantageous in bonding the first substrate 110 and the second substrate 115 and protecting the bridge region BRA.

5 is a diagram schematically illustrating a non-display area NDA of the display panel 400 according to an embodiment of the present invention.

Since the same description as that described above is applied to the same components as the above-described components, a separate description is not repeated, and only the parts that need to be added to the above description are added.

5 shows a gate insulating layer 121 on the first substrate 110 , a first metal layer M1 on the gate insulating layer 121 , an interlayer 120 on the first metal layer M1 , and an intermediate layer The second metal layer M2 on the 120 and the first passivation layer PAS1 covering the second metal layer M2, the planarization layer 122 on the first passivation layer PAS1, and the planarization layer 122 are disposed A second passivation layer covering the trench T and the contact hole, the third metal layer M3 and the third metal layer M3 disposed on the planarization layer 122 and connected to the second metal layer M2 by the contact hole (PAS2). In addition, a sealant for bonding the first substrate 110 and the second substrate 115 to each other is disposed outside the display panel 400 . The sealant is disposed between the overcoat layer OC disposed under the second substrate 115 and the second passivation layer PAS2 disposed above the first substrate 110 . The upper alignment layer U_AL is disposed under the overcoat layer OC disposed under the second substrate 115 so as not to overlap the sealant. In addition, the lower alignment layer L_AL is disposed on the second passivation layer PAS2 disposed on the first substrate 110 so as not to overlap the sealant. The black matrix BM is disposed in part or all of the non-display area NDA to cover various metal lines disposed in the non-display area NDA.

An upper dam U_DM and a lower dam L_DM are disposed at a point where the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL may overlap. The upper dam U_DM is disposed under the overcoat layer OC disposed under the second substrate 115 , and the lower dam L_DM is a second passivation layer disposed over the first substrate 110 . It is placed on PAS2). A trench T formed in the planarization layer 122 is formed at a point where the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL may overlap.

In the non-display area NDA, a touch wiring area RVcomA including a plurality of touch wirings RVcom_1 and RVcom_2 densely arranged in an outer direction of the display panel 400 from the end of the display area DA, and a gate driver (GIP) and the gate link unit (G_Link) are sequentially arranged. That is, among the touch wiring area RVcomA, the gate driver GIP, and the gate link part G_Link included in the non-display area NDA, the touch wiring area RVcomA is disposed closest to the display area DA.

By lowering the resistance of the touch wirings RVcom_1 and RVcom_2, the touch sensing performance can be improved. However, when the widths of the touch wirings RVcom_1 and RVcom_2 are widened to lower the resistance of the touch wirings RVcom_1 and RVcom_2, there is a disadvantage in that the bezel width increases. In order to lower the resistance of the touch wirings RVcom_1 and RVcom_2 without increasing the bezel width, the touch wirings RVcom_1 and RVcom_2 are arranged as densely as possible while overlapping the touch wirings RVcom_1 and RVcom_2 in a plurality of layers. In addition, the touch wiring RVcom_2 of the upper layer and the touch wiring RVcom_1 of the lower layer are electrically connected through the contact hole of the planarization layer 122 . More specifically, in the touch wiring area RVcomA, a plurality of first touch wirings RVcom_1 is formed by the second metal layer M2 . In addition, in the touch wiring area RVcomA, a planarization layer 122 is disposed on the first touch wiring RVcom_1 , and has a shape overlapping with the first touch wiring RVcom_1 on the planarization layer 122 , and a third metal layer M3 ) to form a plurality of second touch wirings RVcom_2 . In addition, the first touch wiring RVcom_1 and the corresponding second touch wiring RVcom_2 are connected to each other by a contact hole formed in the planarization layer 122 . Accordingly, the width of the bezel can be formed narrow while obtaining the effect of reducing the resistance of each of the touch wirings RVcom_1 and RVcom_2.

The touch wirings RVcom_1 and RVcom_2 may connect the aforementioned common electrode line and the touch driver. Accordingly, it is possible to implement the display panel 400 capable of sensing a touch by applying a signal for sensing a touch input to the common electrode line connected to the touch wirings RVcom_1 and RVcom_2 .

A sealant may be disposed on the second passivation layer PAS2 to overlap the entire area of the gate link part G_Link and a partial area of the gate driver GIP. That is, the seal-region to which the sealant is applied may overlap the gate link part G_Link and the gate driver GIP among the non-display area NDA. In any case, the seal-area Seal does not overlap the touch wiring area RVcomA.

The seal-region (Seal) formed by disposing the sealant on the periphery of the display panel 400 secures a space for the liquid crystal layer LC between the first substrate 110 and the second substrate 115 . do. That is, the first substrate 110 and the second substrate 115 are bonded to each other while securing a cell gap by the sealant of the seal region, and the liquid crystal layer LC defined corresponding to the cell gap The liquid crystal does not leak out of the display panel 400 . The sealant may be formed of a material that is applied in a fluid state and cured by photocuring. When the sealant is made of a photocurable material, high energy light such as UV must be irradiated toward the seal-region to cure the sealant. At this time, when high-energy light is irradiated from the second substrate 115 to the seal-region, the light does not reach the seal-region Seal by the black matrix BM having a property of absorbing the light. It is not effective because it is not Accordingly, it is possible to irradiate high energy light from the first substrate 110 to the seal region. If the sealant is applied to the touch wiring area RVcomA or the sealant is not applied to the touch wiring area RVcomA but spreads in the display area DA direction D1, the sealant is applied to the touch wiring area RVcomA ) may also be present. In this case, in order to cure the sealant, when light is irradiated from the first substrate 110 to the seal region, not only the gate link part G_Link and the gate driver GIP but also the touch wiring region RVcomA. It may be necessary to irradiate the light. However, in the touch wiring area RVcomA, since most of the light is reflected by the plurality of densely arranged touch wirings RVcom_1 and RVcom_2, a sufficient amount of light does not reach the sealant.

More specifically, the degree to which the metal wiring is dense in a certain area of the circuit area may be expressed as an open ratio in the corresponding area. The aperture ratio in the corresponding region means the ratio of the region not covered by the metal wiring in the total area of the corresponding region. Among the circuit areas, the touch wiring area RVcomA has an aperture ratio of 20% or less due to a plurality of densely arranged touch wirings. However, when light is irradiated in a region having an aperture ratio of at least 50% or more, light sufficient to cause photocuring in the sealant can reach the sealant. That is, through the touch wiring area RVcomA, light sufficient to photocur the sealant does not reach the sealant.

Therefore, the sealant should not be applied on the circuit area where the metal wirings are densely arranged. In addition, the sealant should not spread over the circuit area where the metal wirings are densely arranged. When the sealant is applied or spread to a region in which the metal wiring is arranged in a densely dense circuit area, the amount of light sufficient to photocur the sealant in the corresponding region does not reach the sealant by the metal wiring reflecting the light. As a result, since the sealant in the corresponding area is not cured, it becomes a cause of poor bonding between the first substrate 110 and the second substrate 115 . In this case, among the circuit regions, the region in which the metal wirings are arranged with a high density means a region in which the aperture ratio of the region is less than 50%. Therefore, the sealant should not spread over the circuit area where the opening ratio is less than 50%. In other words, the sealant should be disposed over the area where the opening ratio is 50% or more in the circuit area. For example, the sealant is not applied on the touch wiring area RVcomA. Also, the sealant does not spread over the touch wiring area RVcomA.

An upper dam U_DM and a lower dam L_DM corresponding to the upper dam U_DM are formed between the seal and the touch wiring area RVcomA so that the sealant does not spread over the touch wiring area RVcomA. are placed The upper dam U_DM faces the first substrate 110 and rests on the overcoat layer OC. In other words, the upper dam U_DM is disposed to protrude from the overcoat layer OC toward the first substrate 110 . The lower dam L_DM rises from the second passivation layer PAS2 toward the second substrate 115 in correspondence with the upper dam U_DM. In other words, the lower dam L_DM is disposed to protrude from the second passivation layer PAS2 toward the second substrate 115 to correspond to the upper dam U_DM. For example, the upper dam U_DM and the lower dam L_DM may be disposed across the boundary between the touch wiring area RVcomA and the gate driver GIP. Alternatively, the upper dam U_DM and the lower dam L_DM may be disposed to be biased toward the gate driver GIP based on the boundary between the touch wiring area RVcomA and the gate driver GIP.

The upper dam U_DM may be formed of the same material as the above-described upper spacer U_SP in the same process. Also, the lower dam L_DM may be formed of the same material as the above-described lower spacer L_SP in the same process. For example, the upper dam U_DM and the lower dam L_DM may be formed of polyimide (PI) or photo acryl (PAC).

The upper alignment layer U_AL is formed of an alignment material and determines an initial alignment direction of the liquid crystal included in the liquid crystal layer LC. For example, the alignment material constituting the upper alignment layer U_AL may be polyimide (PI). The upper alignment layer U_AL is disposed in the display area DA under the overcoat layer OC. Accordingly, the upper alignment layer U_AL is surrounded by the sealant disposed in the non-display area NDA. An alignment material for forming the upper alignment layer U_AL is applied to one surface of the overcoat layer OC corresponding to the display area DA in a fluid state. Depending on the spreading property of the alignment material, the alignment material may not only be formed in the display area DA but also spread in the non-display area NDA direction D2 . Accordingly, the upper alignment layer U_AL may be formed to extend to the non-display area NDA.

Like the upper alignment layer U_AL, the lower alignment layer L_AL is also formed of an alignment material, and determines the initial alignment direction of the liquid crystal included in the liquid crystal layer LC. For example, the alignment material constituting the lower alignment layer L_AL may be polyimide (PI). The lower alignment layer L_AL is disposed on the second passivation layer PAS2 in the display area DA. Accordingly, the lower alignment layer L_AL is surrounded by the sealant disposed in the non-display area NDA. An alignment material for forming the lower alignment layer L_AL is applied to one surface of the overcoat layer OC corresponding to the display area DA in a fluid state. Depending on the spreading property of the alignment material, the alignment material may not only be formed in the display area DA but also spread in the non-display area NDA direction D2 . Accordingly, the lower alignment layer L_AL may be formed to extend to the non-display area NDA.

The sealant of the seal-region is also applied and spread in a fluid state before curing. As the sealant spreads in the display area DA direction D1 , it may partially cover the upper alignment layer U_AL or the lower alignment layer L_AL. That is, there is a possibility that the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL overlap. However, when the second passivation layer PAS2 is made of a silicon-based inorganic material and the upper alignment layer U_AL or the lower alignment layer L_AL is made of polyimide, the gap between the sealant and the second passivation layer PAS2 is The adhesive force is much stronger than the adhesive force between the sealant and the upper alignment layer U_AL or the lower alignment layer L_AL. That is, in a region where the sealant and the upper alignment layer U_AL or the lower alignment layer L_AL overlap each other, the bonding strength between the first substrate 110 and the second substrate 115 by the sealant is lowered. This is a cause of poor bonding between the first substrate 110 and the second substrate 115 .

Accordingly, the upper dam U_DM and the lower dam L_DM are disposed so that the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL do not overlap. Alternatively, the upper dam U_DM and the lower dam L_DM are disposed so that the sealant does not spread in the display area DA direction D1 . An area in which the upper dam U_DM and the lower dam L_DM are disposed is referred to as an overlap prevention area OA. The overlap prevention area OA may be disposed across a boundary between the touch wiring area RVcomA and the gate driver GIP. Alternatively, the overlap prevention area OA may be disposed to be biased toward the gate driver GIP based on the boundary between the touch wiring area RVcomA and the gate driver GIP. Accordingly, it is possible to prevent a decrease in bonding strength between the first substrate 110 and the second substrate 115 due to the sealant.

A plurality of trenches T are formed in the planarization layer 122 to increase the adhesive force of the sealant. At a position corresponding to the edge of the sealant, the planarization layer 122 is recessed to form a trench (T). An area in which the plurality of trenches T are disposed is referred to as a trench area TA. When the applied sealant spreads in the display area DA direction D1 , the sealant flows into the trench T. As the sealant fills the curvature of the trench T, the adhesive area of the sealant increases. As the adhesive area of the sealant increases, the adhesive force by the sealant is improved. Also, even if the sealant spreads in the display area DA direction D1 , the degree of spread, that is, the spread width, decreases as the trench T is filled. As the spread width of the sealant is reduced, the overlapping phenomenon of the sealant and the lower alignment layer L_AL may be minimized. In addition, the overlapping phenomenon of the sealant and the lower alignment layer L_AL by the trench T is minimized, thereby preventing a decrease in bonding strength between the first substrate 110 and the second substrate 115 due to the sealant. can do.

The overlap prevention area OA and the trench area TA are disposed adjacent to the boundary between the touch wiring area RVcomA and the gate driver GIP and overlap each other.

In this case, the overlap prevention area OA and the trench area TA may be disposed to be biased toward the gate driver GIP based on the boundary between the touch wiring area RVcomA and the gate driver GIP.

Alternatively, the overlap prevention area OA is disposed across the boundary between the touch wiring area RVcomA and the gate driver GIP, and the trench area TA is based on the boundary between the touch wiring area RVcomA and the gate driver GIP. As a result, it may be disposed to be biased toward the gate driver GIP. In other words, a portion of the overlap prevention area OA and a portion of the trench area TA may overlap, and the overlap prevention area OA may be disposed closer to the touch wiring area RVcomA than the trench area TA. That is, the upper dam U_DM and the lower dam L_DM are disposed across the boundary between the touch wiring region RVcomA and the gate driver GIP, and the trench T is formed between the touch wiring region RVcomA and the gate driver GIP. Based on the boundary of , it may be disposed to be biased toward the gate driver GIP. Since the trench T is formed by forming a groove in the planarization layer 122, it is to be disposed in the touch wiring area RVcomA where the touch wiring of the upper layer and the touch wiring of the lower layer are connected by the contact hole of the planarization layer 122. On the other hand, since the upper dam U_DM and the lower dam L_DM are located on the touch wiring, they may be disposed in the touch wiring area RVcomA. Accordingly, when the sealant is spread in the display area DA direction D1, the trench T primarily serves as a puddle to receive the sealant, and secondarily, the upper dam U_DM and the lower dam L_DM ) can act as a barrier to prevent the sealant from flowing into the touch wiring area (RVcomA).

6 is a diagram schematically illustrating a non-display area (NDA) of the display panel 500 according to an embodiment of the present invention.

Since the same description as that described above is applied to the same components as the above-described components, a separate description is not repeated, and only the parts that need to be added to the above description are added.

6 shows a gate insulating layer 121 on the first substrate 110 , a first metal layer M1 on the gate insulating layer 121 , an interlayer 120 on the first metal layer M1 , and an intermediate layer The second metal layer M2 and the second metal layer 122 covering the second metal layer M2 are formed on 120 , and the second sub metal layer M2_s and the second sub metal layer M2_s are formed on the planarization layer 122 . The sub-planarization layer 122_s covering the sub-planarization layer 122_s, the trench T and the contact hole disposed in the sub-planarization layer 122_s, the third layer disposed on the sub-planarization layer 122_s and connected to the second metal layer M2 by the contact hole A second passivation layer PAS2 covering the metal layer M3 and the third metal layer M3 may be included. In this case, the sub-planarization layer 122_s may be made of the same material as the planarization layer 122 .

An upper dam U_DM and a lower dam L_DM are disposed at a point where the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL may overlap. The upper dam U_DM is disposed under the overcoat layer OC disposed under the second substrate 115 , and the lower dam L_DM is a second passivation layer disposed over the first substrate 110 . It is placed on PAS2). A trench T formed in the sub-planarization layer is formed at a point where the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL may overlap.

By lowering the resistance of the touch wirings RVcom_1, RVcom_2, and RVcom_3, the touch sensing performance can be improved. However, when the widths of the touch wirings RVcom_1, RVcom_2, and RVcom_3 are widened in order to lower the resistance of the touch wirings RVcom_1, RVcom_2, and RVcom_3, the bezel width increases. In order to lower the resistance of the touch wirings (RVcom_1, RVcom_2, RVcom_3) without increasing the bezel width, the touch wirings (RVcom_1, RVcom_2, RVcom_3) are arranged as densely as possible and the touch wirings (RVcom_1, RVcom_2, RVcom_3) are arranged in multiple layers. overlap to form Then, the upper layer touch wirings (RVcom_2, RVcom_3) and the lower layer touch wirings (RVcom_1, RVcom_3) are electrically connected. More specifically, in the touch wiring area RVcomA, a plurality of first touch wirings RVcom_1 is formed by the second metal layer M2 . In addition, in the touch wiring area RVcomA, a planarization layer 122 is disposed on the first touch wiring RVcom_1 , and a second sub-metal layer ( A plurality of third touch wirings RVcom_3 may be formed by M2_s). In addition, in the touch wiring area RVcomA, a sub-planarization layer 122_s is disposed on the third touch wiring RVcom_3 , and a third metal layer has a shape overlapping with the third touch wiring RVcom_3 on the sub-planarization layer 122_s. A plurality of second touch wirings RVcom_2 may be formed by (M3). In addition, the first touch wiring RVcom_1 and the third touch wiring RVcom_3 corresponding thereto are connected to each other by a contact hole formed in the planarization layer 122 . In addition, the third touch wiring RVcom_3 and the corresponding second touch wiring RVcom_2 are connected to each other by a contact hole formed in the sub-planarization layer 122_s. As described above, by using the three-layer touch wirings RVcom_1, RVcom_2, and RVcom_3, the resistance of each of the touch wirings RVcom_1, RVcom_2, and RVcom_3 can be reduced while obtaining a narrow bezel width.

7A to 7H are plan views corresponding to the anti-overlap area OA shown in FIG. 5 .

Referring to FIG. 7A , the upper dam U_DM and the lower dam L_DM overlap each other and are disposed in a solid line between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM overlap each other to form a pair, the upper dam U_DM and the lower dam L_DM may have two or three pairs. When the upper dam U_DM and the lower dam L_DM have a plurality of pairs, the separation distance between the upper dam U_DM and the lower dam L_DM may be different for each pair. For example, as the pair is closer to the seal-region Seal, the separation distance between the upper dam U_DM and the lower dam L_DM may be greater. In addition, in the pair furthest from the seal-region Seal, the separation distance between the upper dam U_DM and the lower dam L_DM may be substantially zero. Accordingly, when the sealant is spread in the direction D1 of the display area DA, a predetermined amount of the sealant is allowed to leak by a pair close to the sealant, thereby preventing the sealant from bursting during bonding. In addition, by completely blocking the sealant by a pair far from the sealant, it is possible to prevent the sealant from finally passing the overlap preventing area OA.

Referring to FIG. 7B , the upper dam U_DM and the lower dam L_DM overlap each other, but the upper dam U_DM is disposed in a dotted line between the seal-region Seal and the alignment layer AL, and the lower The dam L_DM is disposed in a solid line between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM overlap each other to form a pair, the upper dam U_DM and the lower dam L_DM may have two or three pairs. In particular, in the case where the sealant flows along the second passivation layer PAS2 as the first substrate 110 is bonded to the bottom and the second substrate 115 is disposed thereon and curing proceeds, the lower dam ( L_DM) is advantageously arranged in a solid line. The lower dam L_DM is linearly arranged and the upper dam U_DM is arranged in a dotted line, so that a gap is generated in an area where the upper dam U_DM corresponding to the lower dam L_DM does not exist. As a result, when the sealant spreads in the display area DA direction D1, a certain amount of the sealant can leak through a gap generated in the area where the upper dam U_DM corresponding to the lower dam L_DM is not present. It can prevent the sealant from bursting during bonding. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7C , the upper dam U_DM and the lower dam L_DM overlap each other and are disposed in a dotted line shape between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM overlap each other to form a pair, the upper dam U_DM and the lower dam L_DM may have two or three pairs. Since the lower dam L_DM and the upper dam U_DM are arranged in a dotted line, a gap is generated in an area where the lower dam and the upper dam U_DM do not exist. Accordingly, when the sealant spreads in the display area DA direction D1, a certain amount of the sealant is allowed to leak through the gap that occurred in the area where the lower dam and the upper dam U_DM are not, so that the sealant does not burst during bonding. can do. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7D , the upper dam U_DM and the lower dam L_DM are alternately disposed and disposed in a solid line between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM are alternately arranged to form a pair, the pair formed by the upper dam U_DM and the lower dam L_DM may be two or three. Accordingly, when the sealant spreads in the direction D1 of the display area DA, the upper dam U_DM and the lower dam L_DM are alternately arranged and a certain amount of the sealant is allowed to leak through the gap, thereby allowing the sealant to leak out. It can prevent the sealant from bursting. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7E , the upper dam U_DM and the lower dam L_DM are alternately disposed and the upper dam U_DM is disposed in a dotted line between the seal-region Seal and the alignment layer AL, and the lower dam U_DM is disposed in a dotted line. The dam L_DM is disposed in a solid line between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM are alternately arranged to form a pair, the pair formed by the upper dam U_DM and the lower dam L_DM may be two or three. In particular, in the case where the sealant flows along the second passivation layer PAS2 as the first substrate 110 is bonded to the bottom and the second substrate 115 is disposed thereon and curing proceeds, the lower dam ( L_DM) is advantageously arranged in a solid line. Accordingly, when the sealant spreads in the direction D1 of the display area DA, the upper dam U_DM and the lower dam L_DM are alternately arranged and a certain amount of the sealant is allowed to leak through the gap, thereby allowing the sealant to leak out. It can prevent the sealant from bursting. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7F , the upper dam U_DM and the lower dam L_DM are alternately disposed and the upper dam U_DM is disposed in a solid line between the seal-region Seal and the alignment layer AL, and the lower The dam L_DM is disposed in a dotted line shape between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM are alternately arranged to form a pair, the pair formed by the upper dam U_DM and the lower dam L_DM may be two or three. In particular, in the case where the sealant flows along the overcoat layer OC as the first substrate 110 is placed on top and the second substrate 115 is bonded to the bottom, and curing proceeds, the upper dam (U_DM) It is advantageous to be arranged in this solid line. As a result, when the sealant spreads in the display area DA direction D1, the upper dam U_DM and the lower dam L_DM are alternately arranged to allow a certain amount of sealant to leak through the gap, thereby It can prevent the sealant from bursting. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7G , the upper dam U_DM and the lower dam L_DM are alternately disposed and disposed in a dotted line between the seal-region Seal and the alignment layer AL. When the upper dam U_DM and the lower dam L_DM are alternately arranged to form a pair, the pair formed by the upper dam U_DM and the lower dam L_DM may be two or three. The lower dam (L_DM) and the upper dam (U_DM) are arranged in a dotted line, and are alternately arranged, and the area without the lower dam (L_DM) and the upper dam (U_DM), the upper dam (U_DM) corresponding to the lower dam (L_DM) ) and a region without the lower dam L_DM corresponding to the upper dam U_DM. As a result, when the sealant spreads in the display area DA direction D1, the upper dam U_DM and the lower dam L_DM are alternately arranged to allow a certain amount of sealant to leak through the gap, thereby It can prevent the sealant from bursting. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

Referring to FIG. 7H , the upper dam U_DM and the lower dam L_DM are alternately arranged in a dotted line shape along between the seal-region Seal and the alignment layer AL while forming a checkered shape at the same time. are placed When the upper dam U_DM and the lower dam L_DM are alternately arranged to form a pair, the pair formed by the upper dam U_DM and the lower dam L_DM may be two or three. As the lower dam (L_DM) and the upper dam (U_DM) are arranged in a dotted line and are alternately arranged and form a checkered shape at the same time, the area without the upper dam (U_DM) corresponding to the lower dam (L_DM) and the upper dam A gap is generated in a region where there is no lower dam L_DM corresponding to (U_DM). Accordingly, when the sealant is spread in the display area DA direction D1, the upper dam U_DM and the lower dam L_DM are arranged to form a checkered pattern so that a certain amount of the sealant can leak through the gap, It can prevent the sealant from bursting during bonding. In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

The anti-overlap area OA shown in FIGS. 7A to 7H may be applied in combination to various embodiments of the present invention as well as the display panel shown in FIG. 5 .

8A to 8D are plan views corresponding to the anti-overlap area OA and the trench area TA shown in FIG. 5 .

As the anti-overlapping area OA shown in FIG. 5, a plan view of the anti-overlapping area OA shown in FIG. 7A is shown, but this is only exemplary and not limited thereto. That is, any one of FIGS. 7B to 7H may be applied to FIG. 8A as the overlap prevention area OA shown in FIG. 5 . In addition, although not shown, any type of overlap prevention area OA that falls within the scope described as the present invention through the detailed description of the present invention may be applied to FIG. 8A .

Referring to FIG. 8A , the upper dam U_DM and the lower dam L_DM overlap each other and are disposed in a solid line between the seal-region Seal and the alignment layer AL. On the other hand, the plurality of trenches T are arranged in a solid line shape that intersects the upper dam U_DM and the lower dam L_DM in the solid line shape. When the sealant spreads in the display area DA direction D1 , the pair formed by the upper dam U_DM and the lower dam L_DM sequentially contacts the sealant, whereas the plurality of trenches T are all in no order. It comes into contact with the sealant under equal conditions. In addition, the sealant fills the plurality of trenches T before leaking beyond the upper dam U_DM and the lower dam L_DM. Therefore, as the area in contact with the sealant by the trench (T) increases, the adhesive force of the sealant increases, and the trench (T) provides a space for the sealant to stay without going over the overlap prevention area (OA). It is possible to control the spread width of the sealant. The plurality of trenches T are not perpendicular to the upper dam U_DM and the lower dam L_DM of the solid or dotted line, but intersect at an angle, thereby making the path of the trench T long. By making the path of the trench T long, the space in which the sealant can stay without going over the overlap prevention area OA as the trench T can be increased.

Referring to FIG. 8B , the upper dam and the lower dam L_DM overlap each other and are disposed in a solid line between the seal-region Seal and the alignment layer AL. In contrast, the plurality of trenches T are disposed in a plurality of solid lines orthogonal to the upper dam U_DM and the lower dam L_DM of a solid or dotted line. When the sealant spreads in the display area DA direction D1 , the pair formed by the upper dam U_DM and the lower dam L_DM sequentially contacts the sealant, whereas the plurality of trenches T are all in no order. It comes into contact with the sealant under equal conditions. In addition, the sealant fills the plurality of trenches T before leaking beyond the upper dam U_DM and the lower dam L_DM. Therefore, as the area in contact with the sealant by the trench (T) increases, the adhesive force of the sealant increases, and the trench (T) provides a space for the sealant to stay without going over the overlap prevention area (OA). It is possible to control the spread width of the sealant.

Referring to FIG. 8C , the upper dam U_DM and the lower dam L_DM overlap each other and are disposed in a solid line between the seal-region Seal and the alignment layer AL. In contrast, the plurality of trenches T are arranged in a plurality of solid lines adjacent to the solid upper dam U_DM and the lower dam L_DM. When the sealant spreads in the display area DA direction D1 , the pair formed by the upper dam U_DM and the lower dam L_DM sequentially comes into contact with the sealant, and the plurality of trenches T also sequentially contact the sealant. come into contact with In addition, the sealant fills the trench T before leaking beyond the upper dam U_DM and the lower dam L_DM. Therefore, as the area in contact with the sealant by the trench (T) increases, the adhesive force of the sealant increases, and the trench (T) provides a space for the sealant to stay without going over the overlap prevention area (OA). It is possible to control the spread width of the sealant.

Referring to FIG. 8D , the upper dam U_DM and the lower dam L_DM overlap each other and are disposed in a solid line between the seal-region Seal and the alignment layer AL. In contrast, the plurality of trenches T are arranged in a plurality of V-shapes that intersect with the solid upper dam U_DM and the lower dam L_DM. When the sealant spreads in the display area DA direction D1 , the pair formed by the upper dam U_DM and the lower dam L_DM sequentially contacts the sealant, whereas the plurality of trenches T are all in no order. It comes into contact with the sealant under equal conditions. In addition, the sealant fills the plurality of trenches T before leaking beyond the upper dam U_DM and the lower dam L_DM. Therefore, as the area in contact with the sealant by the trench (T) increases, the adhesive force of the sealant increases, and the trench (T) provides a space for the sealant to stay without going over the overlap prevention area (OA). It is possible to control the spread width of the sealant. The plurality of trenches T are not perpendicular to the upper dam U_DM and the lower dam L_DM of the solid or dotted line, but intersect at an angle, thereby making the path of the trench T long. By making the path of the trench T long, the space in which the sealant can stay without going over the overlap prevention area OA as the trench T can be increased. In addition, since the plurality of trenches T are formed in a V shape, the spreading direction of the sealant flowing into the trench T is bent once, thereby reducing the flow rate of the sealant.

The trench area TA shown in FIGS. 8A to 8D may be applied in combination to various embodiments of the present invention as well as the display panel shown in FIG. 5 .

In various embodiments of the present invention described with reference to the drawings, in the area where the seal-region and the gate link part G_Link and the gate driver GIP disposed in the non-display area NDA overlap, the sealant has improved adhesion. By having the , it is possible to reduce the occurrence of a bonding defect between the first substrate 110 and the second substrate 115 and at the same time reduce the bezel width of the display device to a certain level or less.

In addition, in the area where the seal-region and the non-display area NDA overlap, the occurrence of corrosion/corrosion of the first metal layer M1 and the second metal layer M2 due to the breakage of the bridge electrode BRL under the sealant is minimized. Accordingly, a more robust display panel can be provided.

In addition, in reducing the bezel width of the display device, the first substrate 110 and the second substrate 115 are bonded together without designing to avoid the seal-region and the bridge region BRA, and without a separate process or addition of a new mask. It is possible to provide a display panel capable of reducing the occurrence of defects and corrosion/corrosion of wirings.

In addition, in order to lower the resistance of the touch wirings RVcom_1, RVcom_2, and RVcom_3, the touch wirings RVcom_1, RVcom_2, and RVcom_3 are arranged as densely as possible, and the touch wirings RVcom_1, RVcom_2, and RVcom_3 are overlapped in a plurality of layers. Then, the upper layer touch wirings (RVcom_2, RVcom_3) and the lower layer touch wirings (RVcom_1, RVcom_3) are electrically connected. Accordingly, the width of the bezel can be narrowed while obtaining the effect of reducing the resistance of each of the touch wirings RVcom_1, RVcom_2, and RVcom_3.

In addition, the upper dam U_DM and the lower dam L_DM are disposed so that the sealant does not spread in the display area DA direction D1, so that the sealant and the upper alignment layer U_AL, or the sealant and the lower alignment layer L_AL ) can provide a non-overlapping display panel.

In addition, the overlap prevention area OA is disposed over the boundary between the touch wiring area RVcomA and the gate driver GIP, or the gate driver GIP based on the boundary between the touch wiring area RVcomA and the gate driver GIP. By designing to be biased toward the side, a display panel in which the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL do not overlap may be provided.

In addition, since the sealant and the upper alignment layer U_AL or the sealant and the lower alignment layer L_AL do not overlap, a decrease in bonding strength between the first substrate 110 and the second substrate 115 can be prevented. have.

In addition, as the adhesive area of the sealant increases by filling the curvature of the trench T while the sealant is spread, the adhesive force by the sealant is improved, so that the first substrate 110 and the second substrate 115 The bonding strength may be increased.

Also, even if the sealant spreads in the display area DA direction D1, as the spread sealant fills the trench T, the spread width of the sealant decreases, so that the sealant and the lower alignment layer L_AL overlap. can be minimized.

In addition, the overlapping phenomenon of the sealant and the lower alignment layer L_AL by the trench T is minimized, thereby preventing a decrease in bonding strength between the first substrate 110 and the second substrate 115 due to the sealant. can do.

In addition, when the sealant is spread in the display area DA direction D1, the trench T primarily serves as a puddle to receive the sealant, and secondarily, the upper dam U_DM and the lower dam L_DM ) can serve as a barrier preventing the sealant from flowing into the touch wiring area (RVcomA).

In addition, by allowing a certain amount of sealant to leak through the gap formed by the upper dam U_DM and the lower dam L_DM, the sealant may not burst during bonding.

In addition, as the flow velocity decreases while the sealant flows to find a gap avoiding the upper dam U_DM and the lower dam L_DM, it is possible to prevent the sealant from finally crossing the overlap prevention area OA.

In addition, as the area in contact with the sealant by the trench (T) increases, the adhesive force of the sealant increases, and the trench (T) provides a space for the sealant to stay without going over the overlap prevention area (OA). It is possible to control the spread width of the sealant.

In addition, the plurality of trenches (T) do not orthogonal to the upper dam (U_DM) and the lower dam (L_DM) of the solid or dotted line type, but intersect obliquely, it is possible to make the path of the trench (T) long. By making the path of the trench T long, the space in which the sealant can stay without going over the overlap prevention area OA as the trench T can be increased.

A display apparatus according to various exemplary embodiments of the present invention may be described as follows.

According to an embodiment of the present invention, there is provided a display device divided into a display area for displaying an image and a non-display area around the display area, comprising: a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween; a sealant disposed in a non-display area between the first substrate and the second substrate to bond the first substrate and the second substrate to each other; an upper alignment layer and a lower alignment layer facing each other in a display area between the first substrate and the second substrate, which is a position for determining an initial alignment direction of the liquid crystal of the liquid crystal layer; a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area; an overlap prevention region including a lower dam rising from the first substrate toward the second substrate and an upper dam running from the second substrate toward the first substrate; and a trench region including a plurality of trenches to allow the sealant to flow in. In this case, the overlap prevention region and the trench region are disposed adjacent to a boundary between the touch wiring region and the gate driver and overlap each other.

In addition, in the display device according to an embodiment of the present invention, a touch wiring region, a gate driver, and a gate link part are sequentially disposed from the end of the display region to an outer direction of the display device, and the trench region is a portion of the touch wiring region and the gate driver. It is characterized in that the arrangement is biased toward the gate driver based on the boundary.

Further, in the display device according to the embodiment of the present invention, the touch wiring region, the gate driver and the gate link part are sequentially disposed from the end of the display region to the outer direction of the display device, and the overlap prevention region includes the touch wiring region and the gate driver. It is characterized in that it is disposed over the boundary of

In addition, in the display device according to an embodiment of the present invention, in the touch wiring region, a plurality of first touch wirings composed of a second metal layer, an insulating planarization layer disposed on the first touch wiring, and a first touch on the planarization layer A plurality of second touch wirings formed of a third metal layer are further disposed in a shape overlapping the wirings, and the first touch wirings and the second touch wirings corresponding to the first touch wirings are formed by a contact hole disposed in the planarization layer. Connected to each other, the trench includes a groove configured in the planarization layer separately from the contact hole disposed in the planarization layer, so that it does not overlap the touch wiring area, and the upper dam and the lower dam are located on the touch wiring, thereby preventing overlapping area and the touch wiring area partially overlap.

In addition, in the display device according to the embodiment of the present invention, the trench is primarily arranged at a position to receive the spread of the sealant, and the upper dam and the lower dam prevent the spread of the sealant from flowing into the touch wiring area. It is characterized in that it is secondarily arranged in a position.

In addition, the display device according to an embodiment of the present invention is characterized in that the aperture ratio of the touch wiring area is 20% or less.

In addition, the display device according to the embodiment of the present invention, the lower dam is characterized in that it is formed of either polyimide (Polyimide) or photo acryl (Photo Acryl).

In addition, the display device according to the embodiment of the present invention is characterized in that the sealant is disposed in an area having an aperture ratio of 50% or more among the non-display areas.

In addition, in the display device according to the embodiment of the present invention, the touch wiring area is characterized in that it belongs to an area having an aperture ratio of less than 50% among the non-display areas.

In addition, in the display device according to an embodiment of the present invention, the second substrate includes a black matrix and a color filter layer for partitioning a light blocking area and an opening area in a plurality of pixels, respectively, and an overcoat layer for flattening the black matrix and the color filter layer by covering it, , wherein the first substrate includes a thin film transistor and a planarization layer disposed to cover the thin film transistor, and in a display area between the first substrate and the second substrate, a plurality of upper spacers disposed on the overcoat layer of the second substrate; and a plurality of lower spacers disposed on the planarization layer of the first substrate in the display area between the first substrate and the second substrate. At this time, the upper spacer is disposed in the light blocking area where the black matrix is disposed, and the lower spacer maintains the cell gap or minimizes the reduction of the cell gap to a specific value or less even if the cell gap is momentarily reduced. It is disposed to face each other, and the lower dam is made of the same material as the lower spacer, and the upper dam is made of the same material as the upper spacer.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam overlap each other and are disposed in a solid line or a dotted line between the area to which the sealant is applied and the lower alignment layer, and the path of the trench is long. , the trench is not perpendicular to the upper dam and the lower dam, but is characterized in that it is arranged to cross at an angle.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam overlap each other and are disposed in a solid or dotted shape along a region where the sealant is applied and the lower alignment layer, and the sealant flowing into the trench It is characterized in that the trench is arranged in a V shape so that the spreading direction of the is bent.

In addition, in the display device according to the embodiment of the present invention, the upper dam and the lower dam are arranged in a solid or dotted line shape along the area to which the sealant is applied and the lower alignment layer while being alternately arranged, so that a certain amount of the sealant is It is characterized in that a gap that can leak out is configured.

In addition, in the display device according to an embodiment of the present invention, the upper dam and the lower dam overlap each other and are disposed in a solid line or a dotted line along a space between the seal-region and the alignment layer, and the upper dam and the lower dam overlap each other. When there are a plurality of pairs formed by the upper dam and the lower dam, the closer the pair is to the area to which the sealant is applied, the greater the separation distance between the upper dam and the lower dam is.

In addition, in the display device according to an embodiment of the present invention, the sealant is a photocurable sealant.

In another aspect, according to an embodiment of the present invention, there is provided a display device divided into a display area for displaying an image and a non-display area around the display area, comprising: a first substrate; UV curing thruant disposed around the periphery of the display device; an alignment layer surrounded by a UV curing sealant; and a first structure disposed at a position to prevent overlapping of the UV curing sealant and the alignment layer in the non-display area to minimize the bezel width of the display device.

In addition, the display device according to an embodiment of the present invention further includes a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area. At this time, the first structure is characterized in that the lower dam.

In addition, the display device according to an embodiment of the present invention is characterized in that the lower dam is disposed across the boundary between the touch wiring area and the gate driver.

In addition, the display device according to an embodiment of the present invention further includes a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area. At this time, the first structure is characterized in that the trench.

In addition, the display device according to an embodiment of the present invention is characterized in that the trench is disposed to be biased toward the gate driver based on the boundary between the touch wiring region and the gate driver.

Although various embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. have. Accordingly, the various embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the various embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display device 100, 200, 300, 400: display panel
110: first substrate 115: second substrate
120: intermediate layer 121: gate insulating layer
122: planarization layer 122_s: sub-planarization layer
123: insulating layer 130: thin film transistor
131: gate electrode 132: active layer
133: first electrode 134: second electrode
140: common electrode 150: pixel electrode
BM: black matrix OC: overcoat layer
U_SP: upper spacer L_SP: lower spacer
G_Link: gate link part GIP: gate driver
D_LL: Data link wiring CL: Connection wiring
GL: gate line DL: data line
ST: stage LC: liquid crystal layer
DA: display area NDA: non-display area
BRA: bridge area BRL: bridge electrode
PAD: Pad part D_Link: Data link part
CLK1, CLK2, CLK3, CLK4: Clock signal Seal: Seal-area
G_Pad: Gate pad part D_Pad: Data pad part
S_In: signal input terminal CF1, CF2, CF3: color filter
CF: color filter layer PAS, PAS1, PAS2: passivation layer
M1: first metal layer M2: second metal layer
M2_s: second sub-metal layer M3: third metal layer
OA: Anti-overlap area TA: Trench area
T: trench P: pixel
D1: Display area direction D2: Non-display area direction
U_DM: upper dam L_DM: lower dam
U_AL: upper alignment layer L_AL: lower alignment layer
RVcomA: touch wiring area RVcom_1: first touch wiring (RVcom_1)
RVcom_2: 2nd touch wiring (RVcom_2) RVcom_3: 3rd touch wiring (RVcom_3)

Claims (20)

In the display device divided into a display area for displaying an image and a non-display area around the display area,
a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween;
a sealant disposed in the non-display area between the first substrate and the second substrate so that the first substrate and the second substrate are bonded to each other;
an upper alignment layer and a lower alignment layer that determine an initial alignment direction of the liquid crystal of the liquid crystal layer and are positioned between the first substrate and the second substrate;
a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area;
an overlap prevention region including a lower dam disposed from the first substrate toward the second substrate and an upper dam disposed from the second substrate toward the first substrate; and
a trench region including a plurality of trenches to allow the sealant to flow in;
The overlap prevention region and the trench region are disposed adjacent to a boundary between the touch wiring region and the gate driver and overlap each other. According to claim 1,
the touch wiring region, the gate driver, and the gate link part are sequentially disposed in an outer direction of the display device from the end of the display region;
The trench region is disposed to be biased toward the gate driver based on a boundary between the touch wiring region and the gate driver. 3. The method of claim 2,
The display apparatus of claim 1, wherein the anti-overlapping area is disposed across a boundary between the touch wiring area and the gate driver. According to claim 1,
In the touch wiring region, a plurality of first touch wirings composed of a second metal layer, an insulating planarization layer disposed on the first touch wiring, and a third metal layer on the planarization layer in a shape overlapping with the first touch wiring, A plurality of second touch wirings composed of
The first touch wiring and the second touch wiring corresponding to the first touch wiring are connected to each other by a contact hole disposed in the planarization layer,
The trench includes a groove formed in the planarization layer separately from the contact hole disposed in the planarization layer, and does not overlap the touch wiring area;
The upper dam and the lower dam are positioned on the touch wiring so that the overlap prevention area and the touch wiring area partially overlap. 5. The method of claim 4,
The trench is primarily disposed at a position to receive the spread of the sealant,
The display device, wherein the upper dam and the lower dam are secondarily disposed at positions preventing the spread of the sealant from flowing into the touch wiring region. 5. The method of claim 4,
An aperture ratio of the touch wiring area is 20% or less. According to claim 1,
The lower dam is composed of any one of polyimide (Polyimde) or photo acryl (Photo Acryl), the display device. According to claim 1,
and the sealant is disposed in an area having an opening ratio of 50% or more among the non-display areas. 9. The method of claim 8,
and the touch wiring area belongs to an area having an aperture ratio of less than 50% among the non-display areas. According to claim 1,
The second substrate further includes a black matrix and a color filter layer for partitioning a light blocking area and an opening area in a plurality of pixels, and an overcoat layer on the black matrix and the color filter layer,
The first substrate further includes a thin film transistor and a planarization layer on the thin film transistor,
a plurality of upper spacers disposed on the overcoat layer of the second substrate in a display area between the first substrate and the second substrate; and
a plurality of lower spacers disposed on the planarization layer of the first substrate in a display area between the first substrate and the second substrate;
the upper spacer is disposed in a light blocking area in which the black matrix is disposed;
The lower spacer is disposed to face each other and face the upper spacer so as to maintain the cell gap or minimize the reduction in the cell gap to a specific value or less even if the cell gap is momentarily reduced
The lower dam is made of the same material as the lower spacer,
and the upper dam is made of the same material as the upper spacer. According to claim 1,
The upper dam and the lower dam overlap each other and are disposed in a solid line or a dotted line along a region where the sealant is applied and the lower alignment layer,
The display apparatus of claim 1, wherein the trench is disposed to cross the upper dam and the lower dam at an angle rather than orthogonally to the upper dam and the lower dam so that the path of the trench becomes longer. According to claim 1,
The upper dam and the lower dam overlap each other and are disposed in a solid line or a dotted line along a region where the sealant is applied and the lower alignment layer,
The display device, wherein the trench is disposed in a V-shape such that a spreading direction of the sealant flowing into the trench is bent. According to claim 1,
The upper dam and the lower dam are arranged in a solid line or a dotted line along a region to which the sealant is applied and the lower alignment layer while being alternately arranged, thereby forming a gap through which a predetermined amount of the sealant can leak. , display device. According to claim 1,
The upper dam and the lower dam overlap each other and are disposed in a solid line or a dotted line shape along a space between the seal-region and the alignment layer,
When the upper dam and the lower dam overlapping each other form a pair, and the upper dam and the lower dam form a plurality of pairs,
The closer the pair to the area to which the sealant is applied, the greater the separation distance between the upper dam and the lower dam. According to claim 1,
The sealant is a photocurable sealant, the display device. In the display device divided into a display area for displaying an image and a non-display area around the display area,
a first substrate;
UV curing sealant disposed around the periphery of the display device;
an alignment layer surrounded by the UV curing sealant;
a lower dam and a plurality of trenches provided on the first substrate and disposed at positions to prevent overlapping of the UV-curable sealant and the alignment layer in the non-display area to minimize a bezel width of the display device; and
a gate link unit, a gate driver, and a touch wiring area disposed in the non-display area;
the lower dam overlaps the plurality of trenches;
The lower dam is disposed across a boundary between the touch wiring region and the gate driver. delete delete delete 17. The method of claim 16,
The plurality of trenches are disposed to be biased toward the gate driver based on a boundary between the touch wiring region and the gate driver.

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