KR20230093937A - Method of manufacturing a non emitting iii-nitride semiconductor stacked structure - Google Patents

Abstract

The present disclosure provides a method for manufacturing a non-emissive group III nitride semiconductor laminate, comprising: forming a seed layer made of AlN at a first temperature on a growth substrate made of silicon (Si); Forming a layer of AlN on the seed layer at a second temperature higher than the first temperature; forming a channel layer, a 2DEG and a barrier layer on the AlN layer; And, prior to forming the channel layer, forming at least one of air voids and protrusions; relates to a method for manufacturing a non-light emitting group III nitride semiconductor laminate including.

Description

Method for manufacturing a non-emission group III nitride semiconductor laminate

The present disclosure relates to a method of manufacturing a non-emissive group 3 nitride semiconductor laminate or a group 3 nitride semiconductor device as a whole, and in particular, a non-light emitting device such as a power device (eg, diode, transistor, HEMT, JFET) emitting) to a method for manufacturing a group 3 nitride semiconductor laminate or a group 3 nitride semiconductor device.

Here, background art related to the present disclosure is provided, and they do not necessarily mean prior art (This section provides background information related to the present disclosure which is not necessarily prior art).

1 is a view showing an example of a group III nitride semiconductor device presented in US Patent Registration No. 7,230,284, and the group III nitride semiconductor device (eg AlGaN / GaN based HEMT) is a growth substrate 11; example: sapphire substrate , SiC substrate), buffer layer (12; ex: Al _x Ga _1-x N (0≤x≤1) buffer layer), channel layer (20; ex: GaN channel layer), 2DEG (22; two-dimensional electron gas) 22, a barrier layer 18 (eg, an AlGaN barrier layer), an insulating layer 24 (SiN insulating layer), a drain electrode 14, a gate electrode 16, and a source electrode 17.

Although it is preferable to utilize a sapphire substrate as the growth substrate 11 from the viewpoint of material cost and crystallinity, it is not suitable from the viewpoint of heat dissipation. SiC substrates can be considered from the viewpoints of crystallinity and heat dissipation, but the material cost is high and may become a bigger problem as the device becomes larger. From the viewpoint of material cost, it can be considered to use a low-cost Si substrate, but a method of improving the crystallinity of the group III nitride semiconductor layer grown thereon must be accompanied. Hereinafter, a method of improving the crystallinity of a group III nitride semiconductor layer in the process of growth is first looked at.

2 is a view showing an example of a group 3 nitride semiconductor laminate proposed in US Patent Publication No. 2005-0156175, the group 3 nitride semiconductor laminate includes a c-plane sapphire substrate 100, a c-plane sapphire substrate 100 A growth prevention film 150 made of SiO ₂ formed thereon, and a Group III nitride semiconductor layer 310 selectively grown thereon. Through this growth method, crystal defects in a group III nitride semiconductor laminate can be reduced.

3 is a view showing another example of a group 3 nitride semiconductor laminate proposed in US Patent Publication No. 2005-0156175, a group 3 nitride semiconductor laminate comprising a c-plane sapphire substrate 100, a c-plane sapphire substrate ( 100), a group 3 nitride semiconductor template 210 formed in advance, a growth prevention film 150 made of SiO ₂ formed on the group 3 nitride semiconductor template 210, and a group 3 nitride semiconductor layer selectively grown thereon. (310). The group III nitride semiconductor template 210 is conventionally formed by a method of growing a group III nitride semiconductor on a c-plane sapphire substrate 100 . That is, a seed layer is formed at a growth temperature around 550 ° C and a hydrogen atmosphere, and then it is formed to a thickness of 1 to 3 μm by a method of growing GaN at a growth temperature of 1050 ° C. Reference numeral 180 denotes defects (Threading Dislocations), and development of defects under the growth prevention layer 150 is blocked, resulting in overall improvement in crystallinity. That is, the growth prevention layer 150 enables ELOG (Epitaxially Lateral Overgrowth) as in the group III nitride semiconductor stack shown in FIG.

4 is a view showing an example of a group III nitride semiconductor light emitting device presented in US Patent Publication No. 2003-0057444, wherein the group III nitride semiconductor light emitting device is grown on a sapphire substrate 100 and a sapphire substrate 100 n It includes a group III nitride semiconductor layer 300 , an active layer 400 grown on the n-type group III nitride semiconductor layer 300 , and a p-type group III nitride semiconductor layer 500 grown on the active layer 400 . Protrusions 110 are formed on the sapphire substrate 100, and the protrusions 110 improve the growth quality of the group III nitride semiconductor layers 300, 400, and 500 grown on the sapphire substrate 100, while the active layer 400 ) functions as a scattering surface that improves the efficiency of emitting light generated from the light emitting device to the outside. The sapphire substrate 100 on which the protrusion 110 is formed as described above is referred to as a patterned sapphire substrate (PSS).

5 is a view showing an example of a group 3 nitride semiconductor light emitting device presented in US Patent Publication No. 2005-082546, the group 3 nitride semiconductor light emitting device includes a sapphire substrate 101 having protrusions 111 and a group 3 nitride A semiconductor layer 301 is included. Unlike the example shown in FIG. 4, a protrusion 111 having a round cross section is presented, which is when using the protrusion 110 as in FIG. 4, the bottom surface of the protrusion 110 (protrusion 110 is formed Epi growth occurs on both the upper surface of the projection 110 and the upper surface of the projection 110, and thus threading dislocation, which is a crystal defect, occurs on both the bottom and top surfaces. ) has an advantage of suppressing the occurrence of threading dislocations by suppressing epitaxial growth on the upper surface of the protrusion 111 .

6 is a view showing an example of a Group 3 nitride semiconductor light emitting device proposed in US Patent Publication No. 2011-0042711, and the Group 3 nitride semiconductor light emitting device 10 is on a sapphire substrate 11 and a sapphire substrate 11. An n-type group III nitride semiconductor region 12a grown, an active region 12b grown over the n-type group III nitride semiconductor region 12a, and a p-type group III nitride semiconductor region 12c grown over the active region 12b. includes Similarly, protrusions 13 are provided on the sapphire substrate 110 . However, the protrusion 13 has a pointed cross section. By having a pointed protrusion 13, the upper part of the protrusion 13 is in the form of a dot or line (when the protrusion 13 is conical, it becomes a point, and when the protrusion 13 is a sharp stripe, it becomes a line). .) to suppress the formation of threading dislocation on the upper side, while suppressing the epi growth on the side connecting the top and bottom surfaces of the protrusion 13, so that the occurrence of threading dislocation on the side of the protrusion 13 can also be suppressed. do.

7 is a view showing an example of a group 3 nitride semiconductor laminate proposed in US Patent Registration No. 10,361,339. The group 3 nitride semiconductor laminate includes a sapphire substrate 10, a buffer region 20 and a group 3 nitride semiconductor region. 35, showing that threading dislocations 35 are still formed at the top of the protrusion even if the protrusion is provided in the form shown in FIG. 6 .

26 and 27 are diagrams showing an example of a group III nitride semiconductor laminate or device proposed in US Patent Registration No. 9,324,844, a junction-type field effect transistor having a vertical structure as a non-emitting group III nitride semiconductor laminate or device. (1000; Vertical Junction Field Effect Transistor; JFET) is presented. The non-emitting group III nitride semiconductor device 1000 includes a drain region 102, a drift region 103, a gate region 104, a source region 105, a drain electrode 106, a gate electrode 107, and a source electrode ( 108). 26 shows the off state, which is the default mode, and the depletion region 109 overlaps the position 120 in the channel 121 (see FIG. 27) to prevent current from flowing. 27 shows an on state, and when voltages (V _D , V _S ) are applied to the gate electrode 107 and the source electrode 108, the gate voltage (V _D ) reduces the size of the depletion region 109 A channel 108 through which current can flow is provided to turn on the JFET 1000 in a vertical structure, and the depletion region 109 is separated so that current flows from the drain region 102 to the drift region 103 and the channel region 121 ) to the source region 106 in the vertical direction 122 .

41 is a view showing an example of a non-emission Group III nitride semiconductor laminate or device proposed in US Patent Registration No. 7,388,236, and a Group III nitride semiconductor device (eg, AlGaN / GaN based HEMT) is shown in FIG. Similarly to the device, a growth substrate (11; ex: sapphire substrate, SiC substrate), a buffer layer (12; ex: Al _x Ga _1-x N (0≤x≤1) buffer layer), a channel layer (20; ex: GaN channel layer) ), 2DEG (22; two-dimensional electron gas) 22, barrier layer (18; example: AlGaN barrier layer), insulating layer (24; example: SiN insulation layer), drain electrode 14, gate electrode 16 ) and a source electrode 17, and a gate field plate 25 is additionally provided on the gate electrode 16. On the other hand, by providing a group III nitride layer 26 (eg: p-type GaN) of different conductivity between the gate electrode 16 and the barrier layer 17, D-mode (Depletion-mode) AlGaN / GaN HEMT (gate voltage E-mode (Enhancement-mode) HEMT (turn-off state when gate voltage is not applied, that is, normally-off device) can be implemented. When high electric energy (high voltage, high frequency) is applied (or injected) through the gate electrode 16 to the gate field plate 25, a large electric field is concentrated around the gate electrode 16, and a part of the group III nitride semiconductor element An electric shock is given to adversely affect the lifespan and reliability of the device. In order to prevent this, an electrode plate shape extended from the gate electrode 16 is designed to disperse the concentrated electric field to protect the device.

57 is a diagram illustrating an example of a display device disclosed in US Patent Publication No. 2021-0183301, and the display device 4100 includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel. (SP3). In addition, the display device 4100 includes a support substrate 4110 (eg, a backplane substrate), a driving layer 4130 provided on the substrate 4110, and light emitting units 4141, 4142, 4143, and 4145 provided on the driving layer 4130. ,4146,4147,4149,4150). The driving layer 4130 drives the light emitting unit and may include a driving element 4135 and an insulating layer 4132, and the driving element 4135 may include a transistor, a thin film transistor, or a high electron mobility transistor (HEMT). can 4141 is a first electrode, 4142 is a first semiconductor layer, 4143 is an active layer, 4145 is a second semiconductor layer, 4146 is a second electrode, 4147 is an isolation structure, 4149 is a window region, and 4150 is a reflective layer. Of course, the light emitting unit may be composed of OLED in addition to being composed of LED and micro LED.

58 and 59 are diagrams illustrating an example of a display device presented in Korean Patent Publication No. 10-2021-0023392, and the display device 5150 includes light emitting units 151, 153, and 155, a pad electrode (PAD), and a buffer layer 5120. ), passivation layers 162 and 164, a switching transistor SMT, a driving transistor DRT, a storage capacitor Cst, and an encapsulation layer 180b. Reference numeral 151 denotes a first semiconductor layer, 153 an active layer, and 155 a second semiconductor layer. The switching transistor SMT includes a first heterojunction layer 165a, a first gate electrode 167a, a first source electrode 168a, and a first drain electrode 169a. The first heterojunction layer 165a includes a first channel formation layer 161a and a first channel supply layer 163a. The driving transistor DRT includes a second heterojunction layer 165b, a second gate electrode 167b, a second source electrode 168b, and a second drain electrode 169b. The second heterojunction layer 165b includes a second channel formation layer 161b and a second channel supply layer 163b. The storage capacitor Cst includes a first storage electrode 171 , a dielectric layer 173 and a second storage electrode 175 . The first storage electrode 171 is connected to the first drain electrode 169a of the switching transistor SWT, and the second storage electrode 175 is connected to the second source electrode 168b of the driving transistor DRT. there is. The pad electrode PAD is connected to a voltage line (Vdd; see FIG. 59) to which a voltage or signal for driving a subpixel is applied, and the S-PAD connects the first source electrode 168a to the data line DL. It is a source pad electrode for connection. In FIG. 59 , GL is a gate line to which the first gate electrode 167a of the switch transistor SWT is connected, and Vcom is a common line to which the second source electrode 168b of the driving transistor DRT is connected. In summary, the first gate electrode 167a of the switching transistor SWT is connected to the gate line GL, the first source electrode 168a is connected to the data line DL, and the first drain electrode 169a is connected to the second gate electrode 167b of the driving transistor DRT, the second source electrode 168b is connected to the common wire Vcom, and the second drain electrode 169b is connected to the first semiconductor layer 151 , the pad electrode PAD is connected to the power supply line Vdd, and the storage capacitor Cst is connected to the first drain electrode 169a and the second source electrode 168b, and the light emitting unit is connected through these lines. Control the light emission of (151,153,155; μLED). Although various types of transistors such as BJT, MOSFET, and TFT may be used as the switching transistor (SWT) and driving transistor (DRT), HEMT is used in the example presented.

This will be described at the end of 'Specific Contents for Carrying Out the Invention'.

This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to one aspect according to the present disclosure (According to one aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, preparing a growth substrate containing silicon (Si); Forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; Forming a plurality of growth prevention films on the first buffer layer; growing a second buffer layer from the first buffer layer exposed through the growth prevention layer; And, forming a non-emission group III nitride semiconductor laminate on the second buffer layer; there is provided a method for manufacturing a non-emission group III nitride semiconductor laminate including.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, preparing a growth substrate; Forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth inhibiting films on the first buffer layer; growing a second buffer layer from the first buffer layer exposed from the plurality of growth suppression films; And, forming a non-emission group III nitride semiconductor laminate on the second buffer layer; there is provided a method for manufacturing a non-emission group III nitride semiconductor laminate including.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, preparing a growth substrate; growing a first buffer layer on the growth substrate; Forming a plurality of protrusions made of the first buffer layer on the first buffer layer; growing a second buffer layer over the first buffer layer; Forming a non-emission Group III nitride semiconductor laminate on the second buffer layer; And, prior to the step of growing the second buffer layer, forming a material layer on the plurality of protrusions to slow down or prevent the growth of the second buffer layer; Provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a non-emitting group III nitride semiconductor laminate, a sequentially stacked drain region; drift area; and a gate area; a support substrate electrically connected to the drain region; a gate electrode electrically connected to the gate region; a source electrode electrically connected to a channel formed by the drift region exposed through the gate region; a passivation layer covering the entire stack where the gate electrode and the source electrode are positioned and having a plurality of openings; a gate electrode for bonding electrically connected to the gate electrode through one of the plurality of openings; And, a source electrode for bonding electrically connected to the source electrode through the other one of the plurality of openings; including, a non-emitting group III nitride semiconductor laminate is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emissive group III nitride semiconductor laminate, forming a non-emissive group III nitride semiconductor laminate on a growth substrate; attaching a temporary substrate to the side of the stack facing the growth substrate; removing the growth substrate; forming a multi-layered thin film including an electrically insulating ceramic layer and a metal layer on a side of the stack from which the growth substrate is removed, in that order; attaching a support substrate to the multilayer thin film; In addition, there is provided a method for manufacturing a non-emission Group III nitride semiconductor laminate including the step of removing the temporary substrate.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a laminate for a non-emission Group III nitride semiconductor device, sequentially laminated, a support substrate; a multilayer thin film composed of an electrically insulating ceramic layer and a metal layer; a non-emitting group III nitride semiconductor region composed of a buffer layer, a channel layer, and a barrier layer; a gate electrode, a source electrode, and a drain electrode electrically connected to the non-emitting group III nitride semiconductor region; a passivation layer covering a non-emitting group III nitride semiconductor region where the source electrode, the drain electrode, and the gate electrode are positioned, and opening the source electrode, the drain electrode, and the gate electrode to enable electrical connection with the outside; And, a field plate provided on top of the passivation layer to be electrically connected to one of the source electrode and the gate electrode; including, a non-emitting group III nitride semiconductor laminate is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emissive group III nitride semiconductor laminate, forming a non-emissive group III nitride laminate on a non-conductive growth substrate step; attaching a temporary substrate to the side of the stack facing the growth substrate; reducing the thickness of the growth substrate; attaching a support substrate to a growth substrate having a reduced thickness; In addition, there is provided a method for manufacturing a non-emission Group III nitride semiconductor laminate including the step of removing the temporary substrate.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, sequentially growing a drain region and a drift region; forming a channel by removing a part of the drift region; and re-growing the gate region in the partially removed drift region, and prior to the regrowth, forming an intervening layer positioned between the gate region and the drift region; further comprising a non-emission group 3. A method for manufacturing a nitride semiconductor laminate is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, preparing a growth substrate having a plurality of protrusions; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth-preventing films on the first buffer layer that are not aligned with respect to the plurality of protrusions; And, growing a second buffer layer from the first buffer layer exposed through the plurality of growth prevention films; there is provided a method of manufacturing a non-light emitting group III nitride semiconductor laminate including.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emission Group III nitride semiconductor laminate, a channel layer, a 2DEG, a barrier layer, and a gate electrode are formed on a growth substrate forming; attaching a temporary substrate using a bonding layer; removing the growth substrate; And, forming a source electrode and a drain electrode on the channel layer from which the growth substrate is removed; a method for manufacturing a non-light emitting group III nitride semiconductor laminate is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing a non-emissive group III nitride semiconductor laminate, a growth substrate made of silicon (Si) is made of AlN at a first temperature. Forming a seed layer; Forming a layer of AlN on the seed layer at a second temperature higher than the first temperature; forming a channel layer, a 2DEG and a barrier layer on the AlN layer; And, prior to forming the channel layer, forming at least one of air voids and protrusions; a method for manufacturing a non-light emitting group III nitride semiconductor laminate including the step is provided.

This will be described at the end of 'Specific Contents for Carrying Out the Invention'.

1 is a view showing an example of a group III nitride semiconductor device presented in US Patent Registration No. 7,230,284;
2 is a view showing an example of a group III nitride semiconductor laminate presented in US Patent Publication No. 2005-0156175;
3 is a view showing another example of a group III nitride semiconductor laminate presented in US Patent Publication No. 2005-0156175;
4 is a view showing an example of a group III nitride semiconductor light emitting device presented in US Patent Publication No. 2003-0057444;
5 is a view showing an example of a group III nitride semiconductor light emitting device presented in US Patent Publication No. 2005-082546;
6 is a view showing an example of a group III nitride semiconductor light emitting device presented in US Patent Publication No. 2011-0042711;
7 is a view showing an example of a group III nitride semiconductor laminate presented in US Patent Registration No. 10,361,339;
8 is a view showing an example of a group III nitride semiconductor laminate or device according to the present disclosure;
9 is a view showing an example of the arrangement relationship between protrusions and growth prevention films according to the present disclosure;
10 is a view showing an example of a method of forming protrusions on a growth substrate according to the present disclosure;
11 is a view showing another example of a method of forming protrusions on a growth substrate according to the present disclosure;
12 is a view showing another example of a method of forming protrusions on a growth substrate according to the present disclosure;
13 is a view showing another example of a method of forming protrusions on a growth substrate according to the present disclosure;
14 is a view showing a specific example of a method of forming a protrusion shown in FIG. 12;
15 to 17 are views showing another example of a method of forming a growth prevention film according to the present disclosure;
18 is a view showing another example of a method of forming a growth prevention film according to the present disclosure;
19 is a view showing another example of a method of forming a growth prevention film according to the present disclosure;
20 is a view showing another example of a method of forming a growth prevention film according to the present disclosure;
21 to 23 are views showing another example of a method of forming a growth prevention film according to the present disclosure;
24 and 25 are diagrams showing another example of a group III nitride semiconductor laminate or device according to the present disclosure;
26 and 27 are diagrams showing an example of a group III nitride semiconductor laminate or device presented in US Patent Registration No. 9,324,844;
28 to 37 are views showing another example of a method for manufacturing a group III nitride semiconductor laminate or device according to the present disclosure;
38 to 40 are views for explaining an example of a support substrate used in the laminate shown in FIG. 37;
41 is a view showing an example of a non-emission Group III nitride semiconductor laminate or device presented in US Patent Registration No. 7,388,236;
42 to 46 are views showing an example of a method of manufacturing the non-emission group III nitride semiconductor laminate or device shown in FIG. 41;
47 is a view showing another example of a method for manufacturing a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
48 is a view showing another example of a method for manufacturing a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
49 is a view showing another example of a method for manufacturing a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
50 is a view showing another example of a method for manufacturing a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
51 is a view showing another example of a method of manufacturing a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
52 and 53 are views showing another example of a method for manufacturing a group III nitride semiconductor laminate or device according to the present disclosure;
54 and 55 are diagrams showing another example of the arrangement relationship between protrusions and growth prevention films according to the present disclosure;
56 is an example of an image (Monochromatic CL image) showing crystal defects formed in the first buffer layer;
57 is a view showing an example of a display device presented in US Patent Publication No. 2021-0183301;
58 and 59 are views showing an example of a display device presented in Korean Patent Publication No. 10-2021-0023392;
60 is a view showing another example of a method for manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure;
61 and 62 are views illustrating various types of non-emission Group III nitride semiconductor laminates or devices manufactured according to the method shown in FIG. 60;
63 is a view showing an example of a method of transferring a non-emission group III nitride semiconductor stack or device manufactured according to the method shown in FIG. 60;
64 is a view showing another example of a method of transferring a non-emission Group III nitride semiconductor laminate or device manufactured according to the method shown in FIG. 60;
65 is a view showing another example of a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
66 is a view explaining the bowing of a wafer during the growth process of the non-emission Group III nitride semiconductor stack or device shown in FIG. 65;
67 is a view showing another example of a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
68 is a view explaining the bowing of a wafer during the growth process of the non-emission Group III nitride semiconductor stack or device shown in FIG. 67;
69 is a view showing another example of a non-emission Group III nitride semiconductor laminate or device according to the present disclosure;
70 is a view explaining the bowing of a wafer during the growth process of the non-emission Group III nitride semiconductor laminate or device shown in FIG. 69;
71 is a view showing another example of a non-emissive group III nitride semiconductor laminate or device according to the present disclosure;
FIG. 72 is a view explaining the bowing of a wafer during the growth process of the non-emission group III nitride semiconductor laminate or device shown in FIG. 70;

Hereinafter, the present disclosure will now be described in detail with reference to the accompanying drawing(s).

8 is a diagram showing an example of a group III nitride semiconductor laminate or device according to the present disclosure, in which HEMT is presented as an example. The group III nitride semiconductor device includes a growth substrate 42 (6-inch or 8-inch Si substrate) having protrusions 41, a first buffer layer 43, a growth prevention film 44; for example, a dielectric material such as SiO ₂ or SiN _x ), second buffer layer 45, channel layer 46 (eg: GaN channel layer with a thickness of 3 μm), 2DEG 47, interlayer 48 (eg: thin AlN layer with a thickness of 10 nm, can be omitted), barrier layer (49; Example: Al _x Ga _1-x N (0.2≤x≤0.3~0.6) barrier layer or AlGaInN barrier layer or AlScN barrier layer with a thickness of 10 to 50 nm), cap layer (50; Example: GaN with a thickness of 5 to 20 nm) It includes a cap layer, an n layer or a p layer, which can be doped or omitted), a source electrode 51, a gate electrode 52, and a drain electrode 53.

In the case of the growth substrate 42 made of silicon (Si) (hereinafter referred to as the Si growth substrate 42), since it is an opaque substrate, the projections used in the sapphire substrate (see FIGS. 4 to 7, these projections are primarily light emitting elements). In (LED), it functions as a scatter (light scattering) to solve the total internal reflection caused by the difference between the refractive index of the group III nitride semiconductor layer and the refractive index of the sapphire substrate, and secondarily the protrusion is a growth prevention film in ELOG (FIG. 2 and see FIG. 3) to improve film quality.) is not required, but in the non-emitting group III nitride semiconductor device or laminate according to the present disclosure, even though the Si growth substrate 42 is a protrusion ( 41) is employed. In addition, as pointed out above, even if the protrusion 41 is employed, the first buffer layer ( 43), threading dislocations (54, 55; threading dislocations) occur, and it is not easy to reach this when high-quality, that is, TDD (Threading Dislocation Density) of 10 ⁷ /cm2 or less is required. In order to solve this problem, the present disclosure adopts the protrusion 41 on the Si growth substrate 42, while forming the growth prevention film 44 on the first buffer layer 43 to By blocking some of the threading dislocations 54 and 55 and forming a group III nitride semiconductor laminate including the second buffer layer 45, channel layer 46, and barrier layer 48 thereon, the film quality of these is improved. It should have TDD (Threading Dislocation Density) of 10 ⁷ /cm 2 or less. In the case where high heat dissipation specifications are required for the device, the growth substrate 42 can be changed from a Si growth substrate to a SiC growth substrate, and therefore a growth substrate containing Si as the growth substrate 42 (Si growth substrate, SiC growth substrate) substrate) may be used. The protrusion 41 may have various shapes shown in FIGS. 4 to 7, and in order to minimize the threading dislocation 54 on the top or upper surface 41a of the protrusion 41, it is preferable to have a sharp longitudinal section. do. Depending on the structure and shape of the protrusion 41, the material constituting the protrusion 41 is the same material as the growth substrate 42 (eg Si, SiC) or a material different from the growth substrate 42 (eg AlN, AlNO) , AlGaN, or GaN).

9 is a view showing an example of the arrangement relationship between the protrusions and the growth preventing film according to the present disclosure, and is a view from above of the growth substrate 42 or the protrusions 41 provided on the bottom surface 42a of the growth substrate 42 . , Conical projections 41 having a circular cross section are arranged at regular intervals in the diagonal direction, and the growth prevention film 44 located on the projections 41 is indicated by 44a, and is located on the bottom surface 42a An anti-growth film 44 is indicated by 44b. The threading dislocation 54 is blocked by the growth prevention layer 44a, and a portion of the threading dislocation 55 is blocked by the growth prevention layer 44b. The size of the growth prevention layer 44a is preferably smaller than the size of the cross section of the protrusion 41 on the bottom surface 42a. If it is too large, the area where the second buffer layer 45 will grow is excessively reduced.

The protrusion 41 may have a height of 0.1 to 2 μm, a width of 0.2 to 3.0 μm, and an interval of 0.1 to 1.0 μm, and the longitudinal section is a cone, square pyramid, dome, or trun. It may have a shape such as a truncated cone/pyramid.

Prior to growing the first buffer layer 43, depending on the type (Si, SiC) of the growth substrate 42, whether or not there are protrusions 41 (in the examples shown in FIGS. 10 and 11, the protrusions 41 are first formed, and in the example shown in FIGS. 12 and 13, the protrusion 41 is formed later) GaN, AlN, AlNO, or AlGaN seed layer (not shown; seed layer) having a thickness of about 20 nm is CVD (MOCVD, ALD, MBE) or PVD (Sputter, PLD) method. In particular, when the AlN seed layer is formed on the Si growth substrate 42 using the CVD method, TMAl gas, which is an aluminum (Al) source, is supplied alone without ammonia (NH ₃ ) gas, which is a nitrogen (N) source. Free It is also desirable to introduce a seeding (Pre-seeding) process. In order to grow the first buffer layer 43 made of a group III nitride semiconductor on the Si growth substrate 42, since the minimum actual growth temperature is a high temperature of 800 ° C. or more, Si atoms are debonded from the surface of the Si growth substrate 42 (Atomic Debonding & Desorption), and in a high-temperature nitrogen atmosphere, fine amorphous material particles due to Si-N bonds are generated on the Si surface, making it difficult to obtain a high-quality group III nitride semiconductor thin film. In order to effectively suppress this, introducing an aluminum (Al) pre-seeding process on the surface of the Si growth substrate 42 from several seconds to several tens of seconds is advantageous for growing a group III nitride semiconductor thin film. After forming a seed layer (not shown) on the Si growth substrate 42, in a subsequent process, the first buffer layer 43 is a GaN single layer, an AlN single layer, or a multilayer thin film using TMGa, TMAl and NH ₃ as a source gas, Using hydrogen (H ₂ ) as a carrier gas, GaN or Ga-rich AlGaN is grown at a relatively high pressure (eg, 250 mbar) at an actual growth temperature of 800 to 1100 ° C, respectively, and on the other hand, at a relatively low pressure (eg, 50 mbar) can grow from AlN to Al-rich AlGaN. In some cases, an AlGaN layer obtained by alloying GaN and AlN materials may be introduced as a part of the first buffer layer 43 . That is, the first buffer layer 43 may be formed of GaN, GaN/AlGaN, AlN, AlN/AlGaN, AlN/AlGaN/GaN, or GaN/AlGaN/AlN on the growth substrate 42.

The thickness of the first buffer layer 43 must be higher than the height of the protrusion 41, and is at least equal to the height of the protrusion 41 in order to primarily shield and reduce the threading dislocation generated from the difference in lattice constant with the growth substrate 42. Alternatively, after thick growth, it is very important to make the growth rate in the lateral direction (horizontal direction) higher than the growth rate in the vertical direction to bend threading dislocations moving in the vertical direction parallel to the growth. As for the conditions for growing up to the height of the protrusion 41, it is preferable to increase the growth rate in the vertical direction rather than the growth rate in the side. Bowing may occur in a wafer state in which the first buffer layer 43 is grown on the growth substrate 42 , which may interfere with accurate positioning of the growth prevention layer 44 . In the case of considering such warping, the thickness of the first buffer layer 43 may be limited to less than 3 μm, and thus the height of the protrusion 41 may be limited to less than the thickness of the first buffer layer 43 .

The growth prevention layer 44 may be formed to a thickness of 1 nm to 1 μm, and the thickness is not particularly limited as long as the growth of the second buffer layer 45 can be suppressed. The shape and position of the growth prevention film 44 is a strip mask shape using a dielectric material such as SiO ₂ or SiN _x in a conventional ELOG or similar group 3 nitride growth process (eg, Pendeo Epitaxy). These positions are a region aligned with the center of the protrusion 41 where the growth prevention layer 44a is located and a region aligned with the bottom surface of the growth substrate 42 between the protrusions 41 where the growth prevention layer 44b is located. For example, the protrusion 41 has an isolation or island shape of various dimensions of a polygon such as a circular shape, a triangular shape, a quadrangular shape, or a hexagonal shape. The width and width of the growth prevention film 44a aligned with the protrusion 41 are first determined according to the shape and dimension of the protrusion 41, but finally, the position of the threading dislocation formed during the growth of the first buffer layer 43 and It is desirable to set considering the distribution.

Like the first buffer layer 42, the second buffer layer 45 is a single layer of GaN, single layer of AlN, or a multilayer thin film using TMGa, TMAl, and NH ₃ as a source gas and hydrogen (H ₂ ) as a carrier gas at an actual growth temperature of 800°C. GaN to Ga-rich AlGaN can be grown at a relatively high pressure (250 mbar) in the range of ~1100 ° C, while AlN to Al-rich AlGaN can be grown at a relatively low pressure (50 mbar). In some cases, an AlGaN layer obtained by alloying GaN and AlN materials may be introduced as a part of the second buffer layer 45 . That is, the second buffer layer 45 is composed of GaN, GaN/AlGaN, AlN, AlN/AlGaN, AlN/AlGaN/GaN, or GaN/AlGaN/AlN on top of the first buffer layer 43 and the growth prevention film 44. It can be. The thickness of the second buffer layer 45 is basically thicker than the thickness of the growth prevention layer 44 . In general, the second buffer layer 45 may grow to have a thickness of 1-5 μm. Threading dislocations generated in the growth substrate 420 by the growth prevention layer 44 are secondarily shielded and extinguished, and the threading potential in the region of the first buffer layer 43 where the growth prevention layer 44 is not formed is considerably less in a group III nitride semiconductor. is re-grown to form the second buffer layer 45 through ELOG or a similar growth process. A foundation for fabricating a group III nitride semiconductor laminate or group III nitride semiconductor device having a threading dislocation density (TDD) of 10 ⁷ /cm 2 or less, which is the goal of the present disclosure, can be made.

10 is a diagram showing an example of a method of forming protrusions on a growth substrate according to the present disclosure. First, a growth substrate 42 is prepared, an etching mask 60 is formed, and the growth substrate 42 itself is dried. The protrusion 41 is formed through etching or wet etching. For example, when an etching mask 60 is formed of SiO ₂ , SiN _x , etc. on the (100), (110), or (111) surface of the Si growth substrate, and then combined with a KOH wet solution and dry etching, various shapes and The protrusion 41 may be formed in a dimension.

FIG. 11 is a diagram showing another example of a method of forming protrusions on a growth substrate according to the present disclosure. In addition to the method shown in FIG. A layer to a seed layer (70; Seed Layer, AlN, AlNO, Al ₂ O ₃ , or Ga ₂ O ₃ ) is formed. The seed layer 70 may be formed by a PVD method and serves to help the growth of the first buffer layer 43 grown by a CVD method (eg, MOCVD method).

FIG. 12 is a diagram showing another example of a method of forming protrusions on a growth substrate according to the present disclosure. Unlike the method shown in FIG. 11, a growth substrate 42 is prepared and then a protrusion base layer 71 is formed. Next, after forming an etching mask 60 thereon, a portion of the protrusion base layer 71 is etched to form the protrusion 41 . Accordingly, the protrusion 41 is made of a material constituting the protrusion base layer 71 formed on the growth substrate 42 , rather than a material constituting the growth substrate 42 . At this time, since the growth substrate 42 is etched so as not to be exposed, the first buffer layer 43 is entirely formed on the projection base layer 71, and thus has an advantage of realizing a high-quality film quality. The protrusion base layer 71 may be formed of a seed layer 70 (see FIG. 11) and a Group III nitride semiconductor layer (eg, AlGaN and GaN) provided thereon, and the seed layer 70, as described above, It may be made of AlN, AlNO, Al ₂ O ₃ , or Ga ₂ O ₃ having a thickness of 200 nm or less by PVD or CVD method, and the group III nitride semiconductor layer is AlGaN and GaN having a thickness of 3 μm or less by CVD method It can be composed of sequential and multi-layered films such as, etc., and functions as a strain control layer. Etching of the protrusion base layer 71 to form the protrusion 41 may be performed until the seed layer 70 is exposed. For example, a 150 nm thick AlN (a pre-seeding process using TMAl gas may be introduced in some cases) is formed as a seed layer 70 on the growth substrate 42 by a CVD (MOCVD) method, followed by a group III nitride semiconductor layer may be configured as a multi-layered film formed of two regions (first and second). The first layer may be composed of 500 nm thick Al _x Ga _1-x N, and is formed while sequentially reducing the aluminum (Al) composition (x) from 80% to 20% to primarily reduce tensile stress. play a mitigating role. The second layer may be composed of GaN with a thickness of 2 μm. Next, after forming an etching mask 60 made of a material such as SiO ₂ or SiN _x , the protrusion 41 is formed through dry etching.

13 is a diagram showing another example of a method of forming protrusions on a growth substrate according to the present disclosure. Unlike the methods shown in FIGS. 11 and 12, a seed layer 70 (see FIG. 11) is formed, but etching is not performed. A method of forming through a lift-off method without using it has been proposed. After preparing the growth substrate 42, a patterned photoresist film 80 (PR) is formed, and a protrusion base layer 71 through a PVD method (eg: an AlN layer, an AlNO layer, Al ₂ having a thickness of 2 μm or less) When a part of the O ₃ layer or the Ga ₂ O ₃ layer (indicated by 71a) is formed and the photoresist film 80 is removed, the protrusion base layer 71a formed on the photoresist film 80 is also removed, leaving the remaining The projection base layer 71a is left on the growth substrate 42 in the form of projections 41, and the projection base layer 71 functions as a seed layer 70 (see FIG. 11) through the PVD method again; Example: An AlN layer, an AlNO layer, an Al ₂ O ₃ layer, or a Ga ₂ O ₃ layer, indicated as 71 b) having a thickness of 1 μm or less, so that the protrusion base layer 71 b covers the entire growth substrate 42, , helps the growth of the first buffer layer 43. It is preferable to set the thickness of the layers 71a and 71b constituting the protrusion base layer 71 in consideration of design to minimize wafer warpage due to stress of the growth substrate 42 . For example, the thickness of the projection base layer 71a formed on the photoresist layer 80 may be 500 nm, and the thickness of the projection base layer 71a may be 20 nm.

FIG. 14 is a diagram showing a specific example of the method of forming the protrusions shown in FIG. 12, wherein a seed layer 70 (eg: AlN having a thickness of 200 nm or less), a first layer 71c (eg: 500 nm thick) is formed on a growth substrate 42 Al _x Ga _1-x N) and a second layer (71d; for example: 2 μm thick GaN) are sequentially formed, and then the protrusion 41 made of the protrusion base layer 71 ) is presented. Here, the protrusion 41 consists of only the second layer 71d (Case I), the first layer 71c - the second layer 71d (Case II), or the seed layer 70 - the first layer. (71c) - may be formed of a second layer (71d) (Case III).

15 to 17 are diagrams for explaining another example of a method of forming a growth prevention film according to the present disclosure, and FIG. 15 shows a growth substrate 42 and a first buffer layer 43 grown thereon. . No protrusions 41 (see FIG. 8) are formed on the growth substrate 42, and threading dislocations 55 penetrate the first buffer layer 43 over the entire sea surface 42a of the growth substrate 41. is formed with 16 shows a growth substrate 42 on which protrusions 41 are formed and a first buffer layer 43 grown thereon. In the area A of the bottom surface 42a of the growth substrate 42 where the protrusion 41 is not formed, threading dislocations 55 are formed to penetrate the first buffer layer 43, as shown in FIG. 15. Threading dislocations 54 are also formed in the region B of the top or upper surface 41a of the protrusion 41 to penetrate the first buffer layer 43 . The threading dislocation 54 is directly generated from the top to top surface 41a, or the first buffer layer 43 grown from the bottom surface 42a is coalesced at the top to top surface 41a of the protrusion 41, that is, region B. Coalescence may occur, and threading dislocations 54 directly generated from the upper or upper surface 41a of the protrusion 41 may be minimized by forming the upper or upper surface 41a of the protrusion 41 in a pointed shape. A bent threading dislocation 56 is formed in the region C between regions A and B, and the threading dislocation 56 is a first buffer layer grown from the bottom surface 42a of the growth substrate 42. (43) is formed in a curved form in the process of filling the space (concave part) between the projections 41 and the projections 41, and if the growth conditions are properly adjusted, most of them do not lead to the upper part of the first buffer layer 43. , is not considered as a crystal defect in the second buffer layer 45 (see FIG. 8) formed thereon. Meanwhile, a threading dislocation may occur on the side surface of the protrusion 41 (that is, in the area of the protrusion 41 between the bottom surface 42a and the top or top surface 41a), which is shown in FIGS. 5 to 7 . , can be minimized by preventing the side surface of the protrusion 41 from being a crystal plane (eg, in the case of the growth substrate 41 made of sapphire, the c-plane is mainly used as the bottom surface 42a). That is, from the side of the projection 41 in such a way that the side surface of the projection 41 has a circular cross section, the longitudinal section is a straight line or upwardly convex curve, or the side surface of the projection 41 is roughened. The growth of the first buffer layer 43 can be hindered. Therefore, when the first buffer layer 43 is grown on the growth substrate 42 provided with the protrusions 41, the area C is grown as an area with fewer crystal defects than the areas A and B. know that it can. Therefore, the example shown in FIG. 17 is characterized in that the growth prevention film 44 is provided in the region A and the region B, and the material constituting the growth substrate 42 is sapphire (Al) in addition to Si and SiC. ₂ O ₃ ), and can be further expanded to Sapphire, AlN, AlGaN, GaN, etc. having an HCP crystal structure, and the C plane can be used as the surface on which growth is made, that is, the bottom surface 42a. The growth preventing film 44 positioned on region A (see FIG. 16) blocks the threading dislocation 55, and the growth preventing film 44 positioned on the region B (see FIG. 16) blocks the threading dislocation 54. Since most of the threading dislocations 56 generated in the region C (see FIG. 16) are bent and do not penetrate the first buffer layer 43, the threading dislocations on the upper surface of the first buffer layer 43 are minimized and thus grow. Threading dislocations 57 and 58 in the first buffer layer 43 exposed through the prevention film 44, that is, the second buffer layer 45 grown from the corresponding first buffer layer 43 in the region C, are 10 ⁷ It can be minimized to have a Threading Dislocation Density (TDD) of / cm 2 or less. The threading dislocation 57 is a threading dislocation generated from the exposed first buffer layer 43, and since the exposed first buffer layer 43 already has a film quality in which crystal defects are minimized and is grown therefrom, the number of crystal defects is greatly reduced. do. The threading dislocation 58 is a crystal defect formed when the second buffer layer 45 grown from the exposed first buffer layer 43 coalesces on the anti-growth film 44, and is blocked by the anti-growth film 44. It has a significantly reduced number compared to threading dislocations 55. The protrusion 41 may have a micro-scale width and height of 1 μm or more (eg, width-2.5 μm, height-1.6 μm, interval between protrusions-0.4 μm), and a nano-scale width and height of less than 1 μm (eg, : width-500nm, height-500nm, spacing between protrusions-50nm). The arrangement of the protrusions 41 may be in a stripe shape or a dot shape, and in the case of a dot shape, six protrusions 41 centered on one protrusion 41 may have a disposition in which the vertexes of a hexagon are located. (Viewed from the point of view of an array of dots of the projections 41, the projections 41 belonging to adjacent rows are not aligned with each other and are arranged in a zigzag form), and the first buffer layer 43 can be grown. It is preferable that the bottom surface 42a on which growth is made is minimized on the premise that there is.

As described above, the growth prevention film 44 is formed of a dielectric (thickness: 1 to 1000 nm) such as SiO ₂ or SiN _x to suppress the second buffer layer 45 on the growth prevention film 44, or the second buffer layer 45 ), but made of a material (eg, AlN, AlNO, AlO) whose growth rate of the second buffer layer 45 is slower than that of the material (eg, GaN) constituting the upper portion of the first buffer layer 43 (eg, AlN, AlNO, AlO). (This is formed by depositing AlN, AlNO, or AlO with a PVD (Sputter, ALD, PLD) device to a predetermined thickness (eg, 1 to 100 nm) and then patterning), so that the second layer on the growth prevention film 44 The growth of the buffer layer 45 may be delayed. In the case of using the growth prevention film 44 made of a material having a slow growth rate of the second buffer layer 45 (eg, AlN, AlNO, AlO), as in the case of using the growth prevention film 44 made of a dielectric material, the exposed second buffer layer 45 1 The second buffer layer 45 grown from the buffer layer 44 is spread over the growth prevention film 44, but the growth of the second buffer layer 45 is also made on the growth prevention film 44 (the growth prevention film 44 is the second buffer layer 45). Functions as a seed layer of the buffer layer 45) and dielectric (SiO ₂ , SiN _x ) growth prevention film 44, the mechanism of generation of threading potential generated in the process of coalescence of the second buffer layer 45 exhibits a different behavior.

18 is a diagram showing another example of a method of forming a growth prevention film according to the present disclosure. Unlike the previous examples, the growth prevention film 44 is formed by the first buffer layer 43 itself. The growth prevention layer 44 is formed in the form of a protrusion 44c with the same concept as the protrusion 41 formed on the growth substrate 42, and may be formed through a photolithography process and an etching process (plasma). The principle of reducing crystal defects in the second buffer layer 45 is the same as in the previous examples. The threading dislocation 57 is a threading dislocation existing in the second buffer layer 45 above the first buffer layer 43 where the protrusion 44c is not formed, and in this region (region C; see FIG. 16), the first buffer layer ( Since the threading dislocation 54 of 43) is bent and most of it does not reach the top of the first buffer layer 43, the second buffer layer 45 is grown from the first buffer layer 43 having a good film quality in this region to reduce penetration. It has a dislocation 57. The threading dislocation 58 is a threading dislocation generated on the top or upper surface 44d of the protrusion 44c located at a position corresponding to the protrusion 41, and the threading dislocation 59 is the bottom surface. This is a threading dislocation generated on the top or upper surface 44d of the protrusion 44c located at a position corresponding to (42a), and the threading dislocation 55 existing in the first buffer layer 43 extends to the protrusion 44c. , Since the top or upper surface 44d of the protrusion 44c is a narrow plane or sharp, it is difficult for threading dislocations 55 to exist even in the second buffer layer 45. Threading dislocations 58 and 59 are partially threaded The second buffer layer 45, which is generated by the dislocation 54 and the threading dislocation 55 and is partially grown on the first buffer layer 43 on which the protrusion 44c is not formed, is formed on the top or upper surface of the protrusion 44c ( Compared to the example shown in Fig. 17, the protrusion 44c is a relatively easy process (photolithography and etching (plasma)) on a GaN or AlGaN single crystal (Epitaxy) having an HCP crystal structure. ), and since it is a homo-epitaxy film formation process in which the second buffer layer is grown with the same material (GaN or AlGaN), threading dislocation and other crystal defects can be minimized. ) may have the same or similar dimensions as the protrusion 44a provided on the growth substrate 42, and may have a nanoscale width and height of less than 1 μm (eg, width-500 nm height) rather than a micro scale width and height of 1 μm or more. -500 nm, spacing between protrusions -50 nm) is preferred.

FIG. 19 is a view showing another example of a method of forming a growth prevention film according to the present disclosure. Unlike the example shown in FIG. It is formed on the first buffer layer 43 at a position corresponding to the surface 42a, that is, a position corresponding to the region A. The threading dislocation 55 existing in the region A is connected to the protrusion 44c, but since the top or upper surface 44d of the protrusion 44c is narrow or sharp, it is eliminated or only partially covered by the second buffer layer 45. This leads to the formation of threading dislocations 59. Some of the threading dislocations 54 present in the region B are connected to the second buffer layer 45 to form threading dislocations 58a or the second buffer layer 45 fills the space between the protrusions 44c. It becomes a bent threading dislocation 58b and disappears in the second buffer layer 45 . Since there are not many threading dislocations in the region C, occurrence of crystal defects in the second buffer layer 45 growing from the region C is also minimized.

FIG. 20 is a view showing another example of a method of forming a growth preventing film according to the present disclosure. Unlike the example shown in FIG. It is formed on the first buffer layer 43 at a position corresponding to the upper surface 41a, that is, a position corresponding to the region B. Some of the threading dislocations 55 existing in the region A lead to the second buffer layer 45 and exist as threading dislocations 59b, but some of the threading dislocations 55 in the second buffer layer 45 cover the space between the protrusions 44c. During the filling process, the threading dislocation 59b is bent and disappears in the second buffer layer 45 . The threading dislocation 54 existing in the region B is connected to the protrusion 44c, but since the top or upper surface 44d of the protrusion 44c is narrow or sharp, it is eliminated or only partially covered by the second buffer layer 45. This leads to the formation of threading dislocations 58a. Since there are not many threading dislocations in region C, generation of crystal defects is minimized even in the second buffer layer 45 growing from region C.

21 to 23 are diagrams showing another example of a method of forming a growth prevention film according to the present disclosure, and in FIG. 21, in addition to the configuration shown in FIG. 18, AlN on the first buffer layer 43 on which protrusions 44c are formed. , AlNO , or AlO material layer 45a is formed. The material layer 45a is the same material as the growth prevention film 44 shown in FIG. 17 and may be formed to a thickness of 1 to 100 nm by the same method (deposited using a PVD (Sputter, ALD, PLD) device). In FIG. 22, the material layer 45a is formed only in the region A, and in FIG. 23, the material layer 45a is formed to cover at least a part of the protrusion 44c. The material layer 45a shown in FIGS. 21 to 23 may be similarly applied to the structure shown in FIG. 19 and the structure shown in FIG. 20 . By introducing the material layer 45a, the threading potential generated in the growth substrate 42 and exposed to the surface of the first buffer layer 43 is blocked and reduced, while the first grown in the two regions A and B; see FIG. 16 . The lattice constant of the second buffer layer 45 with the material layer 45a made of AlN, AlNO, or AlO is small, so that the number of threading dislocations can be minimized overall by suppressing generation of threading dislocations. Of course, the material layer 45a may be introduced in the example shown in FIG. 17 . The material layer 45a may also perform a function of restoring damage that may occur to the first buffer layer 43 exposed in the process of forming the growth prevention layer 44 and the protrusion 44c.

Considering all the examples shown in FIGS. 17 to 23 , the growth prevention layer 44 may be referred to as a growth inhibition layer 44 in that it prevents or slows down the growth of the second buffer layer 45 .

24 and 25 are views showing another example of a group III nitride semiconductor laminate or device according to the present disclosure, in which the protrusion 41 of the form shown in FIG. 14 and the material layer 45a shown in FIG. 21 are combined. Examples of shapes are given. In view of the example shown in FIG. 14, projections 41 (see FIGS. 16 to 23) made of a material (Al ₂ O ₃ ) constituting the growth substrate 42 are formed on the growth substrate 42 (eg, a sapphire substrate). Rather, the protrusion bay layer 71 is formed through film formation, then the protrusion 41 is formed by patterning, and then the material layer 45a shown in FIG. 21 is formed thereon. At this time, the growth prevention film or growth The suppression layer 44 may be omitted, and in this case, the protrusion base layer 71 corresponds to the first buffer layer 43 . In view of the example shown in FIG. 21 , the protrusions 41 provided on the growth substrate 42 are omitted, the first buffer layer 43 is formed, and then the protrusions are formed on the first buffer layer 43 as the growth inhibition layer 44. 44c is formed, and a material layer 45a is formed thereon. A second buffer layer 45 and a non-emission Group III nitride semiconductor stack or element A are stacked thereon. Of course, the material layer 45a may be partially formed in the form shown in FIGS. 22 and 23, and when the material layer 45a is formed in the form shown in FIG. 23, the material layer ( 45a) is not an Al-containing material such as AlN, AlNO, or AlO that slows down the growth of the second buffer layer 45, but a material that prevents the growth of the second buffer layer 45 on the protrusion 41, SiO ₂ , SiN _x Of course, it can be composed of a dielectric material such as. By using this structure, as described with reference to FIGS. 21 to 23, threading dislocation can be reduced, while as shown in FIG. 25, it is supported on the side of the non-emitting group III nitride semiconductor laminate or element A. After the substrate S is provided, when the growth substrate 42 is removed through a process such as LLO (Laser Lift-Off), in the case of having protrusions 41 made of the same material as the growth substrate 42 It has the advantage of being able to easily separate the growth substrate 42 from the non-emission Group III nitride semiconductor laminate or device A side. When fabricating a non-light emitting device having a vertical current flow using a group III nitride semiconductor, a short wavelength high-density laser beam (Shorter Wavelength & Higher Optical Flux Laser Beam) is irradiated to the sapphire growth substrate 42 to cause optical, thermal, and mechanical damage. Improving the performance (especially breakdown voltage) and reliability of non-light emitting devices (e.g., transistors or diodes) having a vertical current flow through a process of separation and removal without damage (LLO process) and subsequent wafer bonding process It is required, in the case where the sapphire growth substrate 42 has protrusions 41 made of the material (Al ₂ O ₃ ) constituting the growth substrate 42, after forming the non-luminescent group III nitride semiconductor laminate (A) into a film In the LLO process, when irradiating and separating a short-wavelength high-density laser beam to the backplane of the sapphire growth substrate 42, a large amount of scattering of the laser beam occurs at the interface where the protrusion 41 is formed, so that the sapphire growth substrate 42 does not Difficulty occurs due to lack of light energy in separating the light-emitting group III nitride semiconductor laminate (A), and at the same time, the scattered laser beam reaches the non-emitting group III nitride semiconductor laminate (A), resulting in an unexpected effect (Side Effect). ) goes crazy. Therefore, in order to manufacture a high-quality group III nitride semiconductor non-light emitting device having a vertical current flow after separating the non-emission group III nitride semiconductor laminate A from the sapphire growth substrate 42, the protrusion 41 is first formed. By forming on the buffer layer 43, it is possible to suppress crystal defects including threading dislocation and at the same time minimize damage in a subsequent device manufacturing process. The protrusion base layer 71 to the first buffer layer 43 may be formed with the same composition and growth conditions as in the previous examples, and after forming the seed layer, suppression of crystal defect including threading dislocation and stress strain A material layer (GaN, AlN, AlGaN, SiNx) or a multi-layer structure (Superlattice) made of these may be introduced to control the .

28 to 37 are diagrams showing another example of a method of manufacturing a group III nitride semiconductor laminate or device according to the present disclosure, as shown in FIGS. 26 and 27 as a group III nitride semiconductor laminate or device. A junction type field effect transistor of the structure is exemplified.

First, as shown in FIG. 28 , a buffer layer 82 is formed on the growth substrate 81 . Of course, the method described above in FIGS. 8 to 25 may be applied to the formation of the buffer layer 82 . Compared with the devices shown in FIGS. 26 and 27 , it is different in that a heterogeneous substrate (eg, a Si substrate or an Al ₂ O ₃ substrate) is used instead of a GaN growth substrate. The buffer layer 82 is preferably made of undoped GaN (uGaN) having a TDD of low 10 ⁷ /cm 2 or less. Since the purpose of the thickness of the buffer layer 82 is to minimize crystal defects (threading dislocation, vacancy, interstitial, and substitutional), there is no limitation as long as it is necessary to achieve this. The method and thickness described over FIGS. 8 to 25 are preferentially applied.

Next, as shown in FIG. 29, a drain region 83 and a drift region 84 are formed. The drain region 83 is a region in contact with the drain electrode and may be formed of, for example, n ⁺ GaN having an N _D (effective electron carrier density) of low 10 ¹⁸ /cm 3 or higher, n ⁺ (Al)GaN, n ^{+ + (} Al)GaN, superlattice (AlGaN/GaN, AlInN/GaN, GaInN/GaN), etc. The thickness of the drain region 83 is important in terms of the thickness and doping concentration required to form an ohmic contact electrode, and for example, a thickness of 1 nm to 100 nm may be applied.

The drift region 84 generally has an effective electron carrier density lower than N _D of the drain region 83, and may increase as its thickness increases, for example, N _D of low 10 ¹⁶ /cm 3 or less, Preferably, it may be made of n ^- GaN having N _D in the range of 2x10 ¹⁴ /cm 3 to 2x0 ¹⁶ /cm 3 . The thickness may range from 3㎛ to 20㎛, and the threshold voltage at which the device is destroyed by improving crystallinity and dispersing and mitigating electrical stress applied from the outside, along with crystal defects that are reduced as the thickness is formed, that is, the breakdown voltage (Breakdown/Blocking Voltage) is known to be dramatically improved.

Next, as shown in FIG. 30, an etching mask 91 (eg, PR, metal, and/or oxide (eg, SiO ₂ )) is formed on the drift region 84, and etching (eg, dry etching and A channel 85 is formed by removing a portion of the drift region 84 through wet etching. The remaining etching mask 91 is removed. The height of the channel 85, which is a movement path of electron carriers having charge (electrical mass), is in the range of 100 nm to 1000 nm, preferably around 500 nm, and the cross-sectional width is usually 10 nm or less. A preferred shape is a rectangle, but square and circular shapes are also possible.

Next, as shown in FIG. 31 , the gate region 86 is formed through regrowth. In order to form the source electrode, the gate region 86 on the upper side of the channel 85 is removed so that the drift region 84 forming the channel 85 is exposed. The gate region 86 may be formed of, for example, p GaN, p ⁺ (Al, In) GaN, p ⁺⁺ (Al, In) GaN, or the like. The conductivity of the gate region 86 and the drift region 84 may be changed, but this is not common in the case of using a different substrate. Here, n ^- is N _D ≤ 2x0 ¹⁶ /cm 3, n,p is 2x0 ¹⁶ /cm ≤ N _D ,N _A ≤ 2x0 ¹⁸ /cm 3, n ⁺ ,p ⁺ is 2x0 ¹⁸ /cm ≤ N _D ,N _A ≤ 2x0 ¹⁹ /cm3, n ⁺⁺ ,p ⁺⁺ is defined as 2x0 ¹⁹ /cm3 ≤ N _D ,N _A. In general, the flattening operation to alleviate the step difference in the thin film involves coating and curing a liquid photoresist (PR) material, followed by a dry etch process, and the protruded gate area (86) with the coated PR material. ) parts are sequentially etched until the drift region 84 of the channel 85 is exposed.

Next, as shown in FIG. 32, a source electrode 87 and a gate electrode 88 are formed. The source electrode 87 is formed to make ohmic contact with the drain region 84 , and the gate electrode 88 is formed to make ohmic or Schorky contact with the gate region 86 . The source electrode 87 may be formed of at least two layers of Cr, Ti, Al, V, W, Re, TiN, CrN, Ni, Pt, and Au materials, for example, Cr/W/Pt/Au or It may be composed of 4 or 5 layers such as Ti/Cr/W/Pt/Au. The gate electrode 88 may be formed of at least two layers of Pd, Ni, Pt, Ru, Rh, Cr, Ti, TiN, NiO, RuO ₂ , and Au materials, for example, Pd/Ni/Pt/ It consists of 4 or 5 layers such as Au or Cr/Ni/Pt/W/Au.

Next, as shown in FIG. 33, a passivation layer 89 serving as a protective film is formed to cover the entire upper surface of the device where the source electrode 87 and the gate electrode 88 are located, and then the temporary substrate 92 ) is attached using the bonding layer 93. Preferably, a sacrificial layer 94 for separating the temporary substrate 92 is provided between the temporary substrate 92 and the bonding layer 93 thereafter. The bonding layer 93 may be provided on both sides or one side. It is preferable to use the same material as the growth substrate 81 for the temporary substrate 92. For example, when the growth substrate 81 is a sapphire substrate, the temporary substrate 92 may also be made of sapphire. Details of this technique are presented in International Publication Nos. WO2020/175971 and WO2021/112648.

Next, as shown in FIG. 34, the growth substrate 81 is removed (e.g., after the LLO process, the buffer layer 82 is removed along with residues generated during the removal process of the growth substrate 81 (e.g., : dry etching and/or wet etching) to expose the drain region 83 .

Next, as shown in FIG. 35 , the drain electrode 95 is formed to make ohmic contact with the drain region 83 exposed by removing the growth substrate 81 and the buffer layer 82 . In the process of removing the buffer layer 82, a surface texture may be formed in the exposed drain region 83 to increase a junction area with the drain electrode 95, and active gas plasma treatment may be performed. It is also possible to do The drain electrode 95 is formed over the entire exposed drain region 83 . The material of the drain electrode 95 may be formed the same as or similar to that of the source electrode 87, and may be made of at least two layers of Cr, Ti, Al, V, W, Re, TiN, CrN, Ni, Pt, and Au materials. It may be formed, for example, it may be composed of 4 or 5 layers, such as Cr/W/Pt/Au or Ti/Cr/W/Pt/Au.

Next, as shown in FIG. 36 , the support substrate 97 is attached to the drain electrode 95 via the bonding layer 96 . The bonding layer 96 may be provided on both sides or one side. The support substrate 97 may be made of a composite such as a ceramic material (eg, Sapphire, AlN, Si), CMC (Cu/Mo/Cu, Cu/MoCu/Cu), or CIC (Cu/Invar/Cu). A material having a difference in coefficient of thermal expansion between the temporary substrate 92 and the thermal expansion coefficient of less than ±5 ppm is preferable. For example, when the temporary substrate 92 is a sapphire substrate, it may be made of sapphire. However, when the support substrate 97 is made of an insulating material, since a JFET having a vertical structure cannot be implemented, it is necessary to provide thermal and electrical passages in the support substrate 97, which will be described later. In addition to forming the support substrate 97 using a wafer bonding method, it is possible to form a thick film of a highly heat dissipating electrically conductive metallic material (eg, Cu, MoCu) using a high-speed PVD deposition machine or use plating. Next, laser is irradiated on the sacrificial layer 94 to separate the temporary substrate 92, and the bonding layer 93 is removed to expose the passivation layer 89.

Next, as shown in FIG. 37, an opening 98 is formed in the passivation layer 89, and a source electrode 99S and a gate electrode 99G for bonding are formed through deposition. If necessary, a drain electrode 99D for bonding is formed on the support substrate 97 through deposition. Prior to the process of forming the bonding electrode 99D on the support substrate 97, a process of reducing the thickness of the support substrate 97 through a method such as polishing may be added, and through these processes, according to the present disclosure As an example of a non-emissive Group III nitride laminate or device, a JFET having a vertical structure may be completed.

38 to 40 are diagrams for explaining an example of a support substrate used in the laminate shown in FIG. 37, and as shown in FIG. 38, the support substrate 97 (eg, sapphire, AlN, Si substrate) is A plurality of trenches or vias 97T are provided on the upper surface, and the trenches or vias 97T are filled with a conductive material 97C. The conductive material 97C serves as a thermal and electrical passage when the support substrate 97 is made of an insulating material, and may serve as a more improved thermal and/or electrical passage even when the support substrate 97 is made of a conductive material. The bonding layer or the upper layer 96 of the supporting substrate may be formed separately or may be formed as part of a process of forming the conductive material 97C. Various methods (plating, wire bonding, press fit, insert, etc.) of forming the trench or via 97T and filling it with the conductive material 97C are proposed in International Patent Publication Nos. WO2020/262957 and WO2018/106070. FIG. 39 shows a state in which the conductive material 97C is exposed through the rear surface by polishing the support substrate 97 as shown in FIG. 37 . Through this, the conductive material 97C can serve as a thermal and electrical passage in the support substrate 97 . FIG. 40 shows a state in which a drain electrode 99D for bonding is formed on the exposed conductive material 97C as shown in FIG. 37 .

42 to 46 are diagrams illustrating an example of a method of manufacturing the non-emission group III nitride semiconductor laminate or device shown in FIG. 41. First, as shown in FIG. 42, a growth substrate 42 (eg: sapphire) substrate, Si substrate), a seed layer 423 (eg AlN), a buffer layer 435, a channel layer 46 (eg 2 μm thick GaN) and a barrier layer 49 (eg 20 nm or less AlGaN) are sequentially formed. form with As shown in FIG. 8, of course, an interlayer 48 and a cap layer 50 may be provided, and as shown in FIG. 41, a group III nitride layer 26 (eg: p-type GaN within 20 nm) ) can be provided as well. Here, HEMT is exemplified, but it goes without saying that it can be extended to a non-emissive group III nitride device. Preferably, the buffer layer 435 may be formed by applying the method described above with reference to FIGS. 8 to 25 . Next, the barrier layer 49 and the channel layer 46 are mesa-etched to expose the buffer layer 435, and then the source electrode 51 and the drain electrode 53 are formed on the upper surface of the barrier layer 49. form Here, the source electrode 51 and the drain electrode 53 may be formed directly on the upper surface of the buffer layer 435 or the channel layer 46 exposed to air (not shown).

Next, as shown in FIG. 43, a gate electrode 52 is formed, and an insulating layer or passivation layer 61 serving as a protective film is formed to cover the entire upper surface of the device. If necessary, a step of forming a field plate 51F by forming necessary openings in the passivation layer 61 is performed. In FIG. 42, the field plate 51F is formed on the source electrode 51, but as shown in FIG. 41, the field plate 26 may also be provided on the gate electrode 52, and the drain electrode 53 Of course, it can also be provided. It goes without saying that the order of forming the electrodes 51, 52, and 53 can be changed.

Next, as shown in FIG. 44 , similar to that described in FIG. 33 , a temporary substrate 92 having a sacrificial layer 94 is attached to the group III nitride semiconductor laminate through an adhesive layer 93 . At this time, the passivation layer 61 functions the same as the passivation layer 89 of FIG. 33 . Organic adhesives such as SOG, BCB, and FO _x may be used as the adhesive layer 93, and after bonding the temporary substrate 92 to the laminate for non-emitting group III nitride devices, a subsequent process at a high temperature of 250 ° C. or higher When this is required, a material including metal (Sn, In, Zn, Au, Ag, Cu, Pd, Ni) is preferable for the adhesive layer 93. In this case, the gate electrode 52 and/or the field plate 51F The formation process is performed after bonding the support substrates 97 and 97a.

Next, as shown in FIG. 45, as shown in FIG. 34, the growth substrate 42 is removed (eg, a LLO process in the case of a sapphire substrate, a CLO process in the case of a Si substrate), and the growth substrate ( 42), the buffer layer 435 (eg, undoped GaN (uGaN)) is exposed by removing a portion of the buffer layer 435 together with the residue generated during the removal process (eg, dry etching and/or wet etching). Preferably, dry etching is performed until a part of the surface of N-polar uGaN is exposed, and a rough surface or surface texture 435a is formed through surface texturing to enhance adhesion. It is also possible to perform an active gas plasma treatment. Then, in order to prevent dielectric breakdown and enhance high heat dissipation, a multilayer thin film 62 composed of an electrically insulating ceramic layer and a metal layer is formed. The multi-layered thin film 62 configures at least one pair (ceramic/metal) in the buffer layer 435, but can function to buffer stress by repeatedly progressing n pairs. The electrical insulating ceramic layer may be made of, for example, AlN, BN, Diamond, SiN _x , SiO ₂ , and the metal layer may be Pt, W, Ru, Rh, Mo, Cu, Cr, TiW, or MoW having excellent atomic filling rate and thermal conductivity. , CuW, and the like. Specifically, it may be made of N-polar GaN (buffer layer)/AlN/Pt, N-polar GaN (buffer layer)/AlN/TiW, N-polar GaN (buffer layer)/SiNx/Pt, or the like. Subsequently, support substrates 97 and 97a are attached to the multilayer thin film 62 via a bonding layer 96, as in FIG. 36 . The bonding layer 96 may be provided on both sides or one side. The supporting substrates 97 and 97a are ceramic materials (eg, Sapphire, AlN, Si), CMC (Cu/Mo/Cu, Cu/MoCu/Cu), Cu/MoCu/Cu, CIC (Cu/Invar/Cu), etc. It may be made of a composite, etc., and a material having a thermal expansion coefficient difference of less than ±5 ppm from the temporary substrate 92 is preferable. For example, when the temporary substrate 92 is a sapphire substrate, it may be made of sapphire. In addition to forming the support substrate 97 using a wafer bonding method, a high heat dissipation electrically conductive metallic material (eg, Cu, MoCu) is formed as a thick film using a high-speed PVD deposition machine or a support substrate 97a is formed using plating. It is also possible to form

Next, as shown in FIG. 46 , the temporary substrate 92 is removed (eg, a LLO process in the case of a sapphire substrate or a CLO process in the case of a Si substrate), as shown in FIG. 36 . Then, the adhesive layer 93 is removed to complete the device. When the support substrate 97 is made of an insulating substrate (eg, a sapphire substrate, an AlN substrate, or a Si substrate), a support substrate 97 provided with a thermal passage is used as shown in FIGS. 37 to 40, and the thickness is reduced through polishing, and then bonding pads 63 are formed here to complete the device.

47 is a view showing another example of a method for manufacturing a non-emission Group III nitride semiconductor laminate or device according to the present disclosure. Unlike the laminate or device shown in FIG. 46, the growth substrate 42 is not completely removed. It has a difference in that it has a form with a part left without it. After going through the process shown in FIG. 43 and attaching the temporary substrate 92 using the bonding layer 93, the growth substrate 42 is not completely removed, but an appropriate method (eg, mechanical polishing, ultra-precision CMP) ) through which the thickness of the growth substrate 42 is reduced. Since sapphire or Si, which is a material constituting the growth substrate 42, has poor heat dissipation characteristics, the thickness of the growth substrate 42 is reduced to a minimum thickness (eg, around 10 μm) required for subsequent processes. Next, as shown in FIG. 45 , a support substrate 97 is attached to the growth substrate 42 having a reduced thickness using a bonding layer 96 . Preferably, the support substrate 97 can be made by the method shown in Figs. 38 to 40. Next, as shown in FIG. 46, the thickness of the support substrate 97 is reduced through polishing to expose the conductive material 97C (see FIG. 38) to the lower surface of the support substrate 97 to effectively function as a thermal passage. . Next, the temporary substrate 92 is removed. Of course, the sacrificial layer 94 may be provided as in FIG. 46 if necessary. Depending on the process, it is also possible to first remove the temporary substrate 92 as shown in FIG. 46 .

48 is a view showing another example of a method of manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure. Unlike the laminate or device shown in FIG. 47, the support substrate 97 is made of a ceramic material ( Example: Sapphire, AlN, Si, Diamond), CMC (Cu/Mo/Cu, Cu/MoCu/Cu), Cu/MoCu/Cu, CIC (Cu/Invar/Cu), etc. differ in points. Preferably, a material having a difference in coefficient of thermal expansion from that of the temporary substrate 92 is less than ±5 ppm.

49 is a view showing another example of a method for manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure. Unlike the laminate or device shown in FIGS. 47 and 48, a support substrate 97a It has a difference in that it is formed as a thick film using a high heat dissipation electrically conductive metallic material (eg, Cu, MoCu) using a high-speed PVD deposition machine or as a thick film using plating (eg, Cu).

50 is a view showing another example of a method for manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure, and unlike the laminate or device shown in FIGS. 47 to 49, a growth substrate having a reduced thickness. There is a difference in that trenches or vias 42T are formed (eg, laser drilling) in 42 and the support substrate 97b is formed therein. The trench or via 42T is filled with a conductive material 97C. As described above, the process of filling the trench or via 42T with the conductive material 97C may be performed using a method such as plating, wire bonding, press fitting, insert, etc. (eg, copper plating, copper deposition, wire bonding & stitching, Au stud bonding <RTI ID=0.0> Corning), and is presented in detail in International Patent Publication Nos. WO2020/262957 and WO2018/106070. In the example shown in FIG. 50, the support substrate 72b may be formed continuously or discontinuously, and in the case of discontinuous formation (for example, wire bonding & stitching, Au stud bonding & coining), additional plating or deposition may be performed. Through this, it is possible to form a continuous form of the support substrate 72b.

51 is a view showing another example of a method for manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure. Unlike the laminate or device shown in FIG. 50, trenches or vias 42T are formed in a nitride layer It has a difference in that it is connected to the phosphorus buffer layer 423. These trenches or vias 42T may be formed by dry etching after reducing the thickness of the growth substrate 42 to about 20 to 30 μm. Of course, the buffer layer 423 may be formed so as not to be exposed. Since the conductive material 97C, that is, the thermal path passes through the growth substrate 42 and continues to the buffer layer 423, which is a nitride layer, it has an advantage of improving thermal characteristics. However, when the trench or via 42T is formed deeply, it is not easy to form the conductive material 97C through plating or deposition. To solve this problem, wire bonding & stitching and Au stud bonding & coining are useful. can be used Of course, one of the methods shown in FIGS. 47 to 49 may be added to the configurations shown in FIGS. 50 and 51 . As shown in FIG. 46 , the complete removal of the growth substrate 42 has the advantage of improving heat dissipation, but may be caused by thermo-mechanical impact or material diffusion during the process of removing the growth substrate 42 and forming a high heat dissipation support substrate. Since this may adversely affect the long-term reliability of the device, by using the growth substrate 42 whose thickness is reduced to about 10 μm, it is possible to guarantee the long-term reliability of the device without significantly damaging radiation heat. On the other hand, long-term reliability of the device is further ensured by using the growth substrate 42 whose thickness is reduced to around 20 to 30 μm, while trenches or vias 42T are formed to form a thermal passage through the conductive material 97C. It becomes possible to improve the heat dissipation performance as well.

52 and 53 are diagrams showing another example of a method of manufacturing a group III nitride semiconductor stack or device according to the present disclosure, a junction type field effect transistor of a vertical structure as shown in FIGS. 26 and 27 (Vertical Junction Field Effect Transistor), and is the same as the method presented in FIGS. 28 to 37 as a whole, but has a difference in the process from the method shown in FIG. 30 to the form shown in FIG.

30 and 31, it is necessary to form a channel 85 by removing a part of the drift region 84, and to form a gate region 86 through regrowth. In this case, the gate region (86; Example: p-type GaN) is the bottom surface (G; see FIG. 52) which is the c-face of the drift region (84; Example: n-type GaN) and the m-face or a-face (a-face) is formed on two contact surfaces called the side (H; drift region 84 corresponds to the surface exposed through etching) of the channel 85, which is the leakage current ( Leakage Current) is generated.

To prevent this, first, as shown in FIG. 52, a buffer layer 82, a drain region 83, a drift region 84, and a channel 85 are formed on the growth substrate 81 through the process shown in FIG. 30. Next, an interlayer (84T) is introduced without directly regrowing the gate region 86 . As described above, the gate region 86 may be made of p GaN, p ⁺ (Al,In)GaN, p ⁺⁺ (Al,In)GaN, or the like. The intervening layer 84T may be formed of undoped (Al,In)GaN or n-type (Al,In)GaN by the same method as the drift region 84 (e.g., MOCVD), or may be formed of AlN, and may also be formed by sputtering. It can be formed of AlN and AlNO using. In addition, it may be formed as a multilayer composed of two or more layers, such as (Al _a ,In _b )Ga _cN /(Al _x ,In _y )Ga _zN , or a well-known superlattice structure. It goes without saying that n-type dopants (Si, Ge) can be implanted into multilayer and superstructures. The structure introducing the intervening layer 84T between the drift region 84 and the gate region 86 is designed to be identical to the n ^- /i/p ⁺⁺ diode structure, so that the contact surface, the bottom surface (G) It performs a rectifying function by serving as a depletion layer in the vertical or horizontal direction on the and side (H), respectively. Therefore, the thickness of the intervening layer 84T, which is the same as the role of "i", is not limited as long as it can enhance the rectification function. 50 nm or less is preferentially preferred, and leakage current can be reduced by introducing the intervening layer 84T having such a function. After partially removing the drift region 84, which is n ^- semiconductor, through an etching process, the gate region 86, which is p ⁺⁺ semiconductor, is re-grown to complete the rectification function through the n ^- /p ⁺⁺ diode structure. Ideally, if a part of the n ^- semiconductor drift region 84 is etched and the p ⁺⁺ semiconductor gate region 86 is continuously re-grown, the drift region 84 will have a leakage current due to surface damage. The possibility of occurrence increases. In order to improve this, it is preferable to introduce an intervening layer 84T. Although the intervening layer 84T is shown as not covering the upper portion of the channel 85 , it goes without saying that the intervening layer 84T may also be formed on the upper portion of the channel 85 .

Next, a gate region 86 is formed as shown in FIG. 31 . Of course, the gate region 86 may be formed to cover the top of the channel 85 .

Next, as shown in FIG. 53, a planarization operation is performed to alleviate the level difference between the channel 85 and the gate region 86, similarly to that shown in FIG. At this time, the upper part 85A of the channel 85 may be left in a form in which the side surface is exposed by removing the intervening layer 84T. When the upper portion 85A is left, the thickness of the drift region 84 is increased, so it is expected that the breakdown voltage can be strengthened due to the electric field dispersion, and on the other hand, energy consumption due to the increase in electrical resistance during driving ( Energy Loss) may increase, so it must be designed with these factors in mind.

Subsequently, as shown in FIG. 32, a source electrode 87 and a gate electrode 88 are formed.

Returning to FIGS. 8 to 23 , in the process of forming the growth prevention film 44 , it is easy to align the growth prevention film 44 to the top of the protrusion 41 (an example of the alignment is shown in FIG. 9 ). not only In particular, in order to align the upper part of the protrusion 41, an aligned pattern process is usually performed using a photolithography process, but this process is complicated, so the defect reduction effect is reduced and the process cost is greatly increased. there is

54 and 55 are diagrams showing another example of the arrangement relationship between the protrusion and the growth preventing film according to the present disclosure. For better understanding, as shown in FIG. lower surface), when the growth prevention film 44 is not aligned with the protrusion 41, defects (Threading Dislocations) located on the top or upper surface 41a of the protrusion 41 are reduced through the growth prevention film 44. It may not have any effect.

That is, as shown at the top of FIG. 54 , when the growth-preventing film 44 and the protrusion 41 are precisely aligned, the threading dislocation 54 located on the top or upper surface 41a of the protrusion 41 and the growth The threading dislocation 55 located on the bottom surface of the substrate 42 or the bottom surface 42a of the protrusion 41 is blocked by the growth prevention film 44, specifically, the growth prevention film 44a and the growth prevention film 45b. can

In the middle part of FIG. 54 , the growth prevention film 44 is shown slightly displaced from the protrusion 41 , and the threading dislocations 54 and 55 are still blocked by the growth prevention films 44a and 44b.

In the lower part of FIG. 54 , the growth prevention film 44 is shown completely out of alignment with the protrusion 41. In this case, the growth prevention films 44a and 44b do not function to block threading dislocations 54 and 55, and simply It serves to improve the film quality to a certain extent by enabling ELOG (Epitaxially Lateral Overgrowth) of the second buffer layer 45 (see FIG. 8) grown thereon.

In Fig. 55, a growth prevention film 44 (44a) longer than the width of the projection 41 (the width at the bottom surface 42a of the projection 41) is introduced. 41), and the threading dislocation 54 is blocked by the growth prevention film 44a in the subsequent growth process, and the film quality is improved. state, and the threading dislocation 54 is still blocked by the growth prevention film 44a. The lower part of Fig. 54 shows a state in which the growth prevention film 44a is displaced from the protrusion 41 to the maximum limit. Although the growth prevention film 44a does not block the threading dislocation 54, it blocks the threading dislocation 55, that is, functions as the growth prevention film 44b, so that the threading dislocation 55 grows in the subsequent growth process. It is blocked by the prevention film 44b and the film quality is improved.

In summary, by designing the anti-growth film 44 of a specific scale, at least some of the threading dislocations 54 and 54 present in the first buffer layer 43, regardless of whether the anti-growth film 44 is aligned with the protrusion 41 or not. can be blocked.

54 and 55 illustrate the case where the width of the projections 41 and the distance between the projections 41 are the same, but when the width of the projections 41 is greater than the distance between the projections 41, the growth prevention film 44 By making the length equal to or greater than the width of the protrusion 41, some of the threading dislocations 54 and 54 can be blocked regardless of whether they are aligned with the protrusion 41, and the width of the protrusion 41 is the distance between the protrusions 41. If the length of the growth prevention layer 44 is equal to or greater than the distance between the protrusions 41, some of the threading dislocations 54 and 54 can be blocked regardless of whether they are aligned with the protrusions 41. That is, if the growth prevention layer 44 is well designed in consideration of the size and arrangement of the protrusions 41 on the growth substrate 42, the threading dislocations 54 and 54 can be blocked to a desired level regardless of whether they are aligned with the protrusions 41 or not. know that it can. It is possible to consider making the growth prevention layer 44 infinitely large, but the upper limit of the size of the growth prevention layer 44 should be limited considering the growth region of the second buffer layer 44 .

In the above, for better understanding, the size and arrangement of the growth prevention film 44 has been described one-dimensionally (based on a longitudinal cross-sectional view), but the actual growth prevention film 44 is two-dimensionally as shown in FIG. It must be explained (based on a plan view) (both deviations in the x-axis direction and the y-axis direction must be considered), so the concept of length mentioned above can be explained by the concept of area. That is, when the length of the growth-preventing film 44a positioned on the protrusion 41 is equal to or greater than the width of the protrusion 41, the area of the growth-preventing film 44a positioned on the protrusion 41 is equal to or greater than the width of the protrusion 41. ) It is replaced by the case of making it equal to or larger than the area (the area on the bottom surface 42a of the projection 41). When the length of the growth-prevention film 44b positioned on the bottom surface 42a of the growth substrate 42 is equal to or greater than the distance between the protrusions 41, the area of the growth-prevention film 44b is the distance between the protrusions 41. It can be replaced by the case of making it larger than the area of a circle with a diameter (a shape other than a circle can be considered). As described above, the distance between the growth prevention films 44a and 44b whose area is set (that is, the upper limit and shape of the area of the growth prevention films 44a and 44b) is determined from the viewpoint of securing the growth region of the second buffer layer 44. can be determined In general, in the case of micro-scale protrusions 41 having a width of 1 μm or more, they have a width of 1 to 2.5 μm and an interval of 0.4 μm or less, and in the case of nano-scale protrusions 41 having a width of less than 1 μm, they are 500 nm or less. Since it has a width of 50 nm or less, the area of the growth prevention film 44a may be designed according to the width and shape of the protrusion 41 . Instead of area, the size of the growth barrier may be defined in terms of horizontal width and vertical width. One of the horizontal width and vertical width may be equal to or larger than the size and / or spacing of the projections, preferably the horizontal width and Both of the vertical widths may be equal to or greater than the size and/or spacing of the bumps.

Looking at this problem from the perspective of Threading Dislocation Density (TDD) from a different point of view, since the target TDD is 10 ⁷ /cm 2 or less, for example, the TDD after the growth of the first buffer layer 43 Assuming that is 10 ^{8 /} cm2 (in reality ^it will be higher than this), TDD 10 ⁸ /cm2 means that 10 This means ^that there are ⁸ , that is, ^100,000,000 threading dislocations (54,55), and from a statistical point of view, one threading dislocation (54, 55) can be seen. That is, assuming that the threading dislocations 54 and 55 are uniformly distributed when the TDD of the first buffer layer 43 is 10 ⁸ /cm 2 , (width * length) 10 ³ nm*10 ³ nm (1 μm* One threading dislocation 54 and 55 exists within an area of 1 μm (this is referred to as a unit area). When the TDD of the first buffer layer 43 is 10 ⁹ /cm 2 , it can be understood that one threading dislocation 54 and 55 exists for every unit area of 316nm*316nm (0.316㎛*0.316㎛). there is. Therefore, if the TDD of the first buffer layer 43 is 10 ⁹ /cm 2 or more, by forming a pattern (circle, hexagon, rhombus, rectangle, stripe, etc.) having a width or diameter of 0.3 μm, the protrusion 41 and the growth prevention film 44 It can be seen that threading dislocations 54 and 55 can be reduced to a desired level or less without alignment.

56 is an example of an image (Monochromatic CL image) showing crystal defects formed in the first buffer layer, in which black dots represent threading dislocations (specifically, screw-type TDs), and black dots The line-shaped crystal defects connecting them represent mixed threading dislocations (Mixed TD, that is, a combination of edge-type TD and threaded threading dislocation). The threading dislocations 54 formed on the top or upper surface of the protrusion 41 (see FIG. 54) correspond to the screw threading dislocations of the black dots. For reference, threading dislocations generated from the bottom surface 42a of the growth substrate 42 (see FIG. 55 ) consist of a majority of knife-like threading dislocations, and the reason why they appear independent, that is, connected rather than dotted on the CL image, is shows a shape in which the threading dislocation generated in the growth substrate 42 is slanted at an angle and interacts with another threading dislocation existing in the vicinity in the growth direction. Therefore, after forming the first buffer layer 43 (see FIG. 54 ), the density or average distance of threading dislocations on the first buffer layer 43 (for example, considering the average distance of threaded threading dislocations), It becomes possible to determine the size (horizontal width and vertical width) Preferably, one of the horizontal width and the vertical width of the growth prevention film 44 is designed to be equal to or longer than the average distance of the threading dislocation, so that the growth prevention film 44 and Even when the projections 41 are not aligned, it is possible to reduce the threading dislocation to a required level, for example, in the case of micro-scale projections 41 having a width of 1 μm or more, a width of 1 to 2.5 μm and a width of 0.4 μm. In the case of the nano-scale projections 41 having a spacing of less than ㎛ and a width of less than 1 μm, since they have a width of 500 nm or less and a spacing of 50 nm or less, the growth prevention film according to the width, spacing, and shape of the projections 41 It is only necessary to design the area of (44) Although the threading dislocation is a crystal defect, there are cases where it is necessary from the viewpoint of relieving the stress of the semiconductor laminate, so when it is necessary to reduce the threading dislocation to a certain level or less. , It is possible to reduce the knife-like threading potential by forming a SiN _x nano mask prior to forming the growth prevention film 44 (at the end of the process of growing the first buffer layer 43) (Dissertation: Improving Transport Properties of GaN-Based HEMT on Si(111) by Controlling SiH ₄ Flow Rate of the SiNx Nano-Mask, MDPI, Published on 25 December 2020).

60 is a view showing another example of a method of manufacturing a non-emission group III nitride semiconductor laminate or device according to the present disclosure. First, a channel layer 46, a 2DEG 47, and a barrier are formed on a growth substrate 42. A layer 49 and a gate electrode 52 are formed. By providing the group III nitride layer (26; see FIG. 41), it is possible to implement a device in a normally-off state. Of course, a first buffer layer 43, a growth prevention layer 44, a second buffer layer 45, an interlayer 48, and/or a cap layer 50 may be provided (see FIG. 8).

Next, as shown in FIG. 33 , a passivation layer 89 functioning as a protective film is formed, and then a temporary substrate 92 is attached using a bonding layer 93 . Preferably, a sacrificial layer 94 for separating the temporary substrate 92 is provided between the temporary substrate 92 and the bonding layer 93 thereafter. The bonding layer 93 may be provided on both sides or one side. The temporary substrate 92 is not particularly limited, but it is preferable to lift off the temporary substrate 92 in a subsequent process relatively easily and process it at low cost, and can use a laser beam (Laser Beam). Apply transparent materials suitable for the Lift Off process. Of course, chemical lift off (CLO) or a process in which chemical etching and mechanical polishing are simultaneously combined (chemical-mechanical polishing (CMP)) is also possible. In particular, in the case of the LLO process, the temporary substrate 92 made of a transparent material includes glass, sapphire, quartz, and the like. When the temporary substrate 92 is formed of a non-light-transmitting material such as metal or Si, it is possible to remove the temporary substrate 92 through wet etching and/or mechanical polishing. As shown, the passivation layer 89 may be formed to completely cover the gate electrode 52 and then expose the gate electrode 52 . It is desirable to minimize the difference in height between the passivation layer 89 and the gate electrode 52, and even if there is a difference in height, it is possible to reduce the difference in height through the bonding layer 93 in a subsequent wafer bonding process and flatten it.

Next, as shown in FIG. 34, the growth substrate 42 is removed (eg, an LLO process) to completely remove the seed layer and buffer layer introduced to form the non-emission Group III nitride semiconductor laminate, The channel layer 46 is exposed.

Finally, a source electrode 51 and a drain electrode 53 are formed on the channel layer 46 . Preferably, an insulating layer 24 (SiN insulating layer) is formed before or after forming the source electrode 51 and the drain electrode 53, similarly to those shown in FIGS. 1 and 41 . The source electrode 51 and the drain electrode 53 are formed on the channel layer 46 exposed after the growth substrate 42 is removed. At this time, since the exposed channel layer 46 becomes a Nitrogen (N) Polarity Surface, -It is easy to form alloyed Ohmic Contact, and it is also possible to form Alloyed Ohmic Contact at a relatively lower temperature. On the other hand, since the barrier layer 49 on which the gate electrode 52 is formed is a metallic (Ga, Al) polarity surface as it is grown, it is easy to form the gate electrode 52 with a Schottky contact or an ohmic contact. In addition, in order to form the source electrode 51 and the drain electrode 53 to have an ohmic contact characteristic with low contact resistance, the surface having nitrogen polarity is subjected to plasma treatment or surface roughness prior to depositing the two electrode materials. Texture) process may be introduced.

61 and 62 are views illustrating various types of non-emission group III nitride semiconductor laminates or devices manufactured according to the method shown in FIG. 60, and in FIG. 61, a gate electrode 52 is provided throughout the laminate or device. formed, and the passivation layer 89 is omitted. Through this configuration, current leakage may be reduced. 62, the gate electrode 52 is located close to the source electrode 51, and by reducing the distance between the gate electrode 52 and the source electrode 51, the size of the device can be reduced, resulting in a parasitic effect. ) has an advantage of reducing electrical resistive parasitic capacitance during high-speed switching operation by minimizing ).

FIG. 63 is a view showing an example of a method of transferring a non-emission group III nitride semiconductor laminate or device manufactured according to the method shown in FIG. 60, wherein the laminate or device W is placed on a support substrate 99. . In the case where the stack or element is individualized, it can be transferred onto the support substrate 99 by the Pick&Place method. When the support substrate 99 is the support substrate 4110 described in FIG. 57 (eg, a wiring board, a backplane substrate), the source electrode 51 and the drain electrode 53 may be attached to the support substrate 99. . As described above, when the temporary substrate 92 and the bonding layer 93 are made of a conductive material, current can be supplied to the gate electrode 52, so they can be left as they are, and the temporary substrate 92 and/or the bonding layer 93 ) is a non-conductive material, the temporary substrate 92 may be removed. As described above, when the temporary substrate 92 is a light-transmitting substrate, it is possible to remove the temporary substrate 92 while minimizing damage to the support substrate 99 through the configuration and method (LLO process) shown in FIG. 36 If necessary, it is also possible to remove the bonding layer 93 or the bonding layer/passivation layer 93 and expose the gate electrode 52. Of course, even if the temporary substrate 92 is made of a conductive material, it can be removed.

FIG. 64 is a view showing another example of a method of transferring a non-emission Group III nitride semiconductor stack or element manufactured according to the method shown in FIG. 60, and a plurality of stacks or elements (W, Y) of a temporary substrate 92 ) is transferred to the supporting substrate 99 while being provided. At this time, since the bonding layer 93 is not provided on the temporary substrate 92, the bonding layer 93 can be omitted between the plurality of laminates or the elements W and Y. Temporary substrate 92 Arrangement of a plurality of stacks or elements (W, Y) placed on the wafer state is performed by photolithography & etching processes on stacks or elements in a wafer state, or temporary stacks or elements (W, Y) already individualized are Pick & Place. This is possible by transferring it to the substrate 92. The specific form of arrangement may vary depending on the wiring form of the substrate 99, and a plurality of stacked bodies or elements W and Y correspond to subpixels in one pixel. In this case, a solution capable of transferring while reducing minute errors is provided A method of removing the temporary substrate 92 has already been described in the example shown in FIG.

65 is a view showing another example of a non-emission group III nitride semiconductor laminate or device according to the present disclosure, wherein the non-emission group III nitride semiconductor laminate or device (eg, HEMT) includes a growth substrate 42, a seed layer (423), a buffer layer 435, a channel layer 46 (eg: 2 μm thick GaN) and a barrier layer 49 (eg: 20 nm or less AlGaN). Preferably, a pre-seeding layer 42j (formed by supplying TMAl gas as an aluminum (Al) source alone without ammonia (NH ₃ ) gas as a nitrogen (N) source), an interlayer 48; 8) and/or the cap layer 50 may be provided, and as shown in FIG. 41, a group III nitride layer 26 (eg: p-type GaN within 20 nm) may be provided. Of course. When the Si substrate is used as the growth substrate 42, the seed layer 423 may be made of AlN to prevent a reaction with GaN present in the upper layer, and the seed layer 423 made of AlN is a low temperature (500 -900 ℃) can be formed to a thickness of 50 nm or less. The buffer layer 435 includes a first layer 43m (Al _a Ga _1-a N (0≤a≤1)) and a second layer 43n (Al _b Ga _1-b N (0≤b<1)). The first layer 43m is to solve the gap constant difference between the seed layer 423 made of AlN and the layer made of GaN located on the top (the second layer 43n, the channel layer 46). It functions as a strain control layer (corresponding to the first layer in FIG. 12 ), and the second layer 43n corresponds to the second layer in FIG. 12 and the second buffer layer 45 in FIG. 17 . Preferably, the buffer layer 435 is grown at a high temperature (1000 ° C. or more) to improve the crystallinity of itself (43m, 43n) and the Group III nitride laminates (46, 47, 49) located on the upper layer, and has a thickness of 1 μm. and an AlN layer 43k having a thickness equal to or greater than 43k.

FIG. 66 is a view explaining the bowing of a wafer during the growth process of the non-emission group III nitride semiconductor laminate or device shown in FIG. 65 .

First, the warpage behavior of a wafer not provided with the AlN layer 43k grown at high temperature (HT) is examined. Before growth, the growth substrate 42 is flat, and the seed layer 423 made of AlN grown at a low temperature (LT) on the growth substrate 42 is concave downward to the maximum in a state in which it is grown. do. This is due to the difference between the lattice constant and thermal expansion coefficient of the growth substrate 42 made of Si and AlN, and when it is excessively bent, that is, when the tensile stress becomes larger than a certain level, cracks occur in the AlN epitaxial layer and the wafer. . On this wafer, a first layer (43m; Al _a Ga _1-a N (0≤a≤1)) in which the component ratio (1-a) of GaN gradually increases and a second layer (43m) in which the component ratio (b-1) of GaN is high (b-1) When 43n; Al _b Ga _1-b N (0≤b<1)) is grown, it changes from convex downward to upward convex, and cracks occur on the wafer when compressive stress is applied. It doesn't happen. Subsequently, when the channel layer 46 (eg GaN), 2DEG 47, and the barrier layer 49 (eg AlGaN) are grown, the degree of convexity is reduced, but the growth is performed without cracks while maintaining the convex state. It is done. For reference, the second layer 43n and the channel layer 46 are distinguished from the viewpoint of device behavior, but from the viewpoint of manufacturing the device, they may form one layer made of GaN without aluminum (Al).

Next, the warpage behavior of the wafer having the AlN layer 43k grown at high temperature (HT) is examined. Before growth, the growth substrate 42 is flat, and a seed layer 423 made of AlN grown at a low temperature (LT) and an AlN layer 43k grown at a high temperature (HT) are grown on the growth substrate 42. state to the maximum concave state. Since the AlN layer 43k of 1 μm or more is grown in addition to the seed layer 423, the convexity of the wafer becomes much greater, and the risk of wafer cracking becomes much greater. Subsequently, when the first layer 43m and the second layer 43n are grown, the degree of convexity decreases, but as shown in FIG. 66, a flat state or an upward convex state may not be reached. When the channel layer 46 (eg GaN), the 2DEG 47, and the barrier layer 49 (eg AlGaN) are grown, the degree of convexity increases again, resulting in a possibility of wafer cracking. In order to reduce the risk of such cracks, it is necessary to adjust the growth conditions so that the final wafer is flat or convex upward.

67 is a view showing another example of a non-emission group III nitride semiconductor laminate or device according to the present disclosure, compared to the laminate or device shown in FIG. 65, in an AlN layer 43k grown at a high temperature (HT) It has a difference in that it has air voids (AV). By providing the air voids (AV), it is possible to relieve tensile stress, while improving the crystallinity of the AlN layer 43k grown at high temperature (HT) grown on the air voids (AV). It becomes possible to improve the layers (43m, 43n, 46, 47, 49) grown on it (Paper: Effectively releasing tensile stress in AlN thick film for low-defect-density AlN/sapphire template; 24 semiconductor July 2020; TODAY). The role of the AlN layer 43k grown at high temperature (HT) with air voids (AV) is largely due to ① the rapidly increasing tensile stress in the process of growing an AlN thin film at a high temperature of 100 ° C or higher; shape) to suppress cracks in a subsequently grown non-emissive group III nitride semiconductor laminate or Si wafer, and ② air voids (AV) introduced into the high-temperature AlN thin film form the Si growth substrate 42 or Crystalline defects generated from the pre-seeding layer 42j or the seed layer 423, particularly misfit and threading, are filtered to dramatically reduce the density of dislocations.

68 is a view explaining the bowing of a wafer during the growth process of the non-emissive group III nitride semiconductor laminate or device shown in FIG. 67, made of AlN grown at high temperature (HT) having air voids (AV) It can be seen that the maximum concave degree of the layer 43k (AV) is smaller than that of the layer 43k made of AlN grown at high temperature (HT) without air voids (AV). It can be seen that the final finished wafer can be made in a convex shape upward.

69 is a view showing another example of a non-emissive group III nitride semiconductor laminate or device according to the present disclosure. In the layer 43k made of AlN grown at high temperature (HT) of the laminate or device shown in FIG. 67, A protrusion 44c as shown in FIG. 18 is additionally provided. As described above, the addition of the protrusion 44c brings about improvement in film quality of the laminate or element. At this time, it is important to prevent the air voids (AV) from being exposed to the top of the protrusions 44c. (HT) The layer 43k made of AlN to be grown is sufficiently thick. The formation of air voids (AV) occurs when the growth temperature of the AlN layer 43k grown at high temperature (HT) is 1000 ° C or higher and the growth temperature of the seed layer 423 made of AlN grown at low temperature (LT) is 500- At 900°C, it can be formed by growing a layer 43k of AlN at an intermediate temperature (MT; 900-1000°C) between them (Paper: Effectively releasing tensile stress in AlN thick film for low-defect-density). AlN/sapphire template; 24 July 2020; semiconductor TODAY). Therefore, by controlling the growth conditions, it is possible to control the position where air voids AV are formed in the AlN layer 43k grown at high temperature (HT). Preferably, as shown in FIG. 21, a material layer 45a (eg, PVD AlN, PVD AlNO) may be introduced. The air voids AV may have various shapes such as a sawtooth shape, a circular shape, a claw-shaped formation, and a nail shape. It can be formed to occupy an area of about /4 to 1/3.

FIG. 70 is a view explaining the bowing of a wafer during the growth process of the non-emissive group III nitride semiconductor laminate or device shown in FIG. 69, made of AlN grown at high temperature (HT) having air voids (AV) At the point where growth starts after forming the protrusions 44c and the material layer 45a on the layers 43k and AV, both a state in which the warpage of the wafer is increased (Q) and a state in which the warpage is reduced (P) are both show that you can have

71 is a view showing another example of a non-emission group III nitride semiconductor laminate or device according to the present disclosure. Unlike the laminate or device shown in FIG. 69, the protrusion 44c is provided on the first layer 43m. There is little concern that air voids (AV) lead to the top of the projections 44c, and the thickness of the layer 43k can be reduced with AlN grown at high temperature (HT), which takes a lot of tensile stress. , it is possible to impart elasticity to the growth conditions of the layer 43k with AlN grown at high temperature (HT). Of course, the material layer 45a may be provided on the protrusion 44c.

FIG. 72 is a diagram explaining the bowing of a wafer during the growth process of the non-emissive group III nitride semiconductor stack or device shown in FIG. The first layer 43m, which is a layer that changes in a close shape (eg, the composition of Al decreases in the order of 0.8->0.5->0.2), can be convex upward after growth, and such a wafer In the state, even if the protrusion 44c and the material layer 45a are provided, the formation of the protrusion 44c and the material layer 45a increases the warp of the wafer to a downward concave state (S) or Regardless of whether the warp is reduced to an upwardly convex state (T), the state of the final wafer can be adjusted to an upwardly convex state. It is not excluded that the protrusion 44c is formed below the second layer 43c and the channel layer 46 .

Hereinafter, various embodiments of the present disclosure will be described.

(1) A method for manufacturing a non-emissive group III nitride semiconductor laminate, comprising: preparing a growth substrate containing silicon (Si); Forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; Forming a plurality of growth prevention films on the first buffer layer; growing a second buffer layer from the first buffer layer exposed through the growth prevention layer; And, forming a non-emission Group III nitride semiconductor laminate on the second buffer layer; a method for manufacturing a non-emission Group III nitride semiconductor laminate.

(2) In the step of forming the growth prevention film, a plurality of growth prevention films are formed to be positioned on top of each protrusion and between the protrusions.

(3) A method of manufacturing a non-luminescent group III nitride semiconductor laminate in which a plurality of protrusions and a growth substrate are made of the same material.

(4) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the growth substrate containing silicon (Si) is one of a Si growth substrate and a SiC growth substrate.

(5) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which the plurality of protrusions and the growth substrate are made of different materials.

(6) prior to the step of forming a plurality of protrusions, forming a protrusion base layer; further comprising, wherein the plurality of protrusions are formed by etching the protrusion base layer, to produce a non-emitting group III nitride semiconductor laminate method.

(7) A method for manufacturing a non-emitting group III nitride semiconductor laminate, wherein the projection base layer is composed of a seed layer formed on the growth substrate and a group III nitride semiconductor layer formed on the seed layer.

(8) A method for manufacturing a non-emissive group III nitride semiconductor laminate in which the group III nitride semiconductor layer of the protrusion base layer is exposed through etching.

(9) A method of manufacturing a non-emitting group III nitride semiconductor laminate in which the seed layer of the protrusion base layer is exposed through etching.

(10) prior to the step of forming a plurality of protrusions, forming a protrusion base layer; further comprising, the plurality of protrusions are formed by lifting-off the protrusion base layer, the non-emitting group III nitride semiconductor laminate How to manufacture.

(11) forming a seed layer covering the lift-off protrusion base layer and the lift-off exposed growth substrate; a method for manufacturing a non-emission Group III nitride semiconductor laminate, further comprising the step.

(12) A method of manufacturing a non-emissive group III nitride semiconductor laminate, comprising: preparing a growth substrate; Forming a plurality of protrusions on the growth substrate; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth inhibiting films on the first buffer layer; growing a second buffer layer from the first buffer layer exposed from the plurality of growth suppression films; And, forming a non-emission Group III nitride semiconductor laminate on the second buffer layer; a method for manufacturing a non-emission Group III nitride semiconductor laminate.

(13) In the step of forming a plurality of growth suppression films, a plurality of growth suppression films are formed so as to be positioned on top of each protrusion and between the protrusions.

(14) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which a plurality of protrusions and a growth substrate are made of the same material.

(15) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the plurality of growth suppression films contain a dielectric material.

(16) The plurality of growth suppression films are capable of growing a second buffer layer therefrom, but the growth rate of the first buffer layer is slower than the growth rate of the first buffer layer from the first buffer layer. method.

(17) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the plurality of growth suppression films contain one of AlN, AlNO, and AlO.

(18) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the plurality of growth suppression films are made of a material constituting the first buffer layer.

(19) prior to the step of growing the second buffer layer, forming a material layer that slows the growth rate of the second buffer layer from the first buffer layer compared to the rate at which the second buffer layer grows; A method for manufacturing a nitride semiconductor laminate.

(20) prior to growing the second buffer layer, forming a material layer that slows the growth rate of the second buffer layer from the first buffer layer compared to the rate at which the second buffer layer grows; A method for manufacturing a nitride semiconductor laminate.

(21) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the plurality of growth suppression films contain one of AlN, AlNO, and AlO.

(22) A method for manufacturing a non-emissive group III nitride semiconductor laminate, comprising: preparing a growth substrate; growing a first buffer layer on the growth substrate; Forming a plurality of protrusions made of the first buffer layer on the first buffer layer; growing a second buffer layer over the first buffer layer; Forming a non-emission Group III nitride semiconductor laminate on the second buffer layer; And, prior to the step of growing the second buffer layer, forming a material layer to slow down or prevent the growth of the second buffer layer on a plurality of protrusions; including, a method for manufacturing a non-emission Group III nitride semiconductor laminate.

(23) A method of manufacturing a non-emission group III nitride semiconductor laminate, wherein the material layer is made of a material that slows down the growth of the second buffer layer and is formed over the entire first buffer layer in which a plurality of protrusions are formed.

(24) A method for manufacturing a non-emitting group III nitride semiconductor laminate, wherein the first buffer layer is composed of a seed layer formed on the growth substrate and a group III nitride semiconductor layer formed on the seed layer.

(25) Separating the growth substrate from the non-emission group III nitride semiconductor laminate side; a method for manufacturing a non-emission group III nitride semiconductor laminate, further comprising.

(26) In a non-luminescent group III nitride semiconductor laminate, sequentially stacked drain regions; drift area; and a gate region; a support substrate electrically connected to the drain region; a gate electrode electrically connected to the gate region; a source electrode electrically connected to a channel formed by the drift region exposed through the gate region; a passivation layer covering the entire stack where the gate electrode and the source electrode are positioned and having a plurality of openings; a gate electrode for bonding electrically connected to the gate electrode through one of the plurality of openings; And, a source electrode for bonding electrically connected to the source electrode through the other one of the plurality of openings; including, a non-emitting group III nitride semiconductor laminate.

(27) The support substrate is made of the same material as the growth substrate, has a plurality of thermal and electrical passages, and the laminate is a bonding drain electrode provided below the support substrate; further comprising a non-emitting group III nitride semiconductor. laminate.

(28) A non-luminescent group III nitride semiconductor laminate in which the support substrate is made of sapphire.

(29) A non-luminescent group III nitride semiconductor laminate in which the support substrate is made of AlN.

(30) A non-luminescent group III nitride semiconductor laminate in which the support substrate is made of Si.

(31) A method for manufacturing a non-emissive group III nitride semiconductor laminate, comprising: forming a non-emissive group III nitride laminate on a growth substrate; attaching a temporary substrate to the side of the stack facing the growth substrate; removing the growth substrate; forming a multi-layered thin film including an electrically insulating ceramic layer and a metal layer on a side of the stack from which the growth substrate is removed, in that order; attaching a support substrate to the multilayer thin film; and removing the temporary substrate.

(32) the support substrate has a thermal passage, reducing the thickness of the support substrate; and forming bonding pads on the support substrate having a reduced thickness.

(33) forming at least one electrode of the laminate from which the temporary substrate is removed;

(34) A laminate for a non-emissive group III nitride semiconductor element, comprising: a support substrate, which is sequentially laminated; a multilayer thin film composed of an electrically insulating ceramic layer and a metal layer; a non-emitting group III nitride semiconductor region composed of a buffer layer, a channel layer, and a barrier layer; a gate electrode, a source electrode, and a drain electrode electrically connected to the non-emitting group III nitride semiconductor region; a passivation layer covering a non-emitting group III nitride semiconductor region where the source electrode, the drain electrode, and the gate electrode are positioned, and opening the source electrode, the drain electrode, and the gate electrode to enable electrical connection with the outside; And, a field plate provided on top of the passivation layer so as to be electrically connected to one of the source electrode and the gate electrode; including, a non-emitting group III nitride semiconductor laminate.

(35) A method for manufacturing a non-emissive group III nitride semiconductor laminate, comprising: forming a non-emissive group III nitride laminate on a non-conductive growth substrate; attaching a temporary substrate to the side of the stack facing the growth substrate; reducing the thickness of the growth substrate; attaching a support substrate to a growth substrate having a reduced thickness; and removing the temporary substrate.

(36) The support substrate has a thermal passage, and prior to the step of removing the temporary substrate, reducing the thickness of the support substrate to expose the thermal passage; How to.

(37) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the supporting substrate is attached to the growth substrate having a reduced thickness through a bonding layer.

(38) forming a thermal passage in the growth substrate having a reduced thickness;

(39) A method for manufacturing a non-emissive group III-nitride semiconductor laminate, wherein the thermal passage is connected to the non-emissive group III-nitride laminate.

(40) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the growth substrate is a sapphire substrate or a Si substrate.

(41) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, comprising the steps of sequentially growing a drain region and a drift region; forming a channel by removing a part of the drift region; and re-growing the gate region in the partially removed drift region, and prior to the regrowth, forming an intervening layer positioned between the gate region and the drift region; further comprising a non-emission group 3. A method for manufacturing a nitride semiconductor laminate.

(42) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein the intervening layer is formed on the bottom surface of the drift region exposed by removal and on the side surface of the channel.

(43) mitigating the level difference between the gate region and the drift region;

(44) A method for manufacturing a non-emission group III nitride semiconductor laminate, wherein in the relaxing step, the intervening layer is removed to expose the upper side surface of the channel.

(45) A method of manufacturing a non-emissive group III nitride semiconductor laminate comprising: preparing a growth substrate having a plurality of protrusions; growing a first buffer layer to cover the plurality of protrusions on the growth substrate; forming a plurality of growth-preventing films on the first buffer layer that are not aligned with respect to the plurality of protrusions; And, growing a second buffer layer from the first buffer layer exposed through the plurality of growth-preventing films; a method for manufacturing a non-light emitting group III nitride semiconductor laminate.

(46) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein each of the plurality of growth prevention films has a horizontal width and a vertical width, the horizontal width and vertical width being determined from the density of threading dislocations on the first buffer layer. Here, the horizontal width and the vertical width mean the maximum widths in the horizontal and vertical directions, and when the growth prevention film is circular, the widths are the same.

(47) Manufacturing a non-emission group III nitride semiconductor laminate in which each of the plurality of growth prevention films has a horizontal width and a vertical width, and at least one of the horizontal width and the vertical width is equal to or longer than the average distance of threading dislocations on the first buffer layer. How to.

(48) Each of the plurality of growth prevention films has a horizontal width and a vertical width, and the plurality of protrusions have a constant spacing, a constant horizontal width, and a constant vertical width, and the horizontal width and vertical width are constant spacing, constant horizontal width, and constant vertical width. A method for producing a non-emissive group III nitride semiconductor laminate, determined from the width.

(49) Each of the plurality of growth prevention films has a horizontal width and a vertical width, and the plurality of protrusions have a constant interval, a constant horizontal width, and a constant vertical width, and at least one of the horizontal width and the vertical width is a constant horizontal width and a constant vertical width. A method of manufacturing a non-emissive group III nitride semiconductor laminate having a width equal to or longer than the width.

(50) Each of the plurality of growth prevention films has a horizontal width and a vertical width, and the plurality of protrusions have a constant interval, a constant horizontal width, and a constant vertical width, and at least one of the horizontal width and the vertical width is equal to or longer than the regular interval. , A method for producing a non-luminescent group III nitride semiconductor laminate.

(51) prior to the step of forming the growth prevention film, forming a SiN _x nano mask on the first buffer layer; further comprising a method for manufacturing a non-emission group III nitride semiconductor laminate.

(52) forming a non-emissive group III nitride semiconductor laminate on the second buffer layer; a method for manufacturing a non-emissive group III nitride semiconductor laminate, further comprising.

(53) A method for manufacturing a non-emission Group III nitride semiconductor laminate comprising: forming a channel layer, a 2DEG, a barrier layer, and a gate electrode on a growth substrate; attaching a temporary substrate using a bonding layer; removing the growth substrate; And, forming a source electrode and a drain electrode on the channel layer from which the growth substrate is removed; a method of manufacturing or transferring a non-light emitting group III nitride semiconductor laminate including the step.

(54) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which an insulating layer is provided between a source electrode and a drain electrode.

(55) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which a gate electrode is formed over the entire barrier layer.

(56) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which the gate electrode is provided closer to the source electrode than the drain electrode.

(57) A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein a gate electrode is provided so as to overlap the source electrode at least partially thereon.

(58) attaching the source electrode and the drain electrode to the support substrate; and removing the temporary substrate.

(59) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which the gate electrode is exposed in the step of removing the temporary substrate.

(60) A method for manufacturing a non-emitting group III nitride semiconductor laminate, comprising: forming a seed layer made of AlN on a growth substrate made of silicon (Si) at a first temperature; Forming a layer of AlN on the seed layer at a second temperature higher than the first temperature; forming a channel layer, a 2DEG and a barrier layer on the AlN layer; And, prior to forming the channel layer, forming at least one of air voids and protrusions; including, a method for manufacturing a non-emission group III nitride semiconductor laminate.

(61) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which projections are formed on an AlN layer.

(62) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which air voids are formed in an AlN layer.

(63) A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which air voids are formed at a third temperature higher than the first temperature and lower than the second temperature.

(64) prior to forming the channel layer, forming a strain control layer that relieves the strain caused by the difference in lattice constant between the layer made of AlN and the channel layer; How to manufacture.

(65) A method for manufacturing a non-emitting group III nitride semiconductor laminate in which projections are formed on the strain control layer.

(66) Forming a material layer on the protrusion; further comprising a method for manufacturing a non-luminescent group III nitride semiconductor laminate.

According to one non-emission Group III nitride semiconductor laminate or device according to the present disclosure, a laminate or device having a Threading Dislocation Density (TDD) of 10 ⁷ /cm 2 or less can be implemented.

According to another non-emissive group III nitride semiconductor laminate or device according to the present disclosure, a new type of vertical structure JFET can be implemented.

According to another non-emission group III nitride semiconductor laminate or device according to the present disclosure, a JFET having a vertical structure having a Threading Dislocation Density (TDD) of 10 ⁷ /cm 2 or less can be implemented.

Protrusion 41, growth substrate 42, first buffer layer 43, growth prevention layer 44, second buffer layer 45, channel layer 46, 2DEG 47, interlayer 48, barrier layer (49), cap layer 50, source electrode 51, gate electrode 52, drain electrode 53

Claims (7)

In the method for manufacturing a non-luminescent group III nitride semiconductor laminate,
Forming a seed layer made of AlN at a first temperature on a growth substrate made of silicon (Si);
Forming a layer of AlN on the seed layer at a second temperature higher than the first temperature;
forming a channel layer, a 2DEG and a barrier layer on the AlN layer; and,
Prior to forming the channel layer, forming at least one of air voids and protrusions; a method for manufacturing a non-light emitting group III nitride semiconductor laminate including. The method of claim 1,
A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which projections are formed on a layer of AlN. The method of claim 1,
A method for manufacturing a non-luminescent group III nitride semiconductor laminate in which air voids are formed in an AlN layer. The method of claim 3,
A method for manufacturing a non-luminescent group III nitride semiconductor laminate, wherein air voids are formed at a third temperature higher than the first temperature and lower than the second temperature. The method of claim 1,
Prior to forming the channel layer, forming a strain control layer to relieve the strain caused by the difference in lattice constant between the layer made of AlN and the channel layer; method. The method of claim 5,
A method for manufacturing a non-emitting group III nitride semiconductor laminate, wherein projections are formed on the strain control layer. The method according to any one of claims 1 to 6,
Forming a material layer on the protrusion; further comprising a method for manufacturing a non-emission Group III nitride semiconductor laminate.

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