KR20230007913A - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to one embodiment of the present invention may comprise: a semiconductor layer of silicon carbide (SiC); a plurality of well regions disposed in the semiconductor layer, spaced from each other, and having a second conductivity type; a plurality of source regions formed in the semiconductor layer on the plurality of well regions, respectively, spaced apart from each other, and having a first conductivity type which is opposed to the second conductivity type; a drift region having the first conductivity type and formed in the semiconductor layer, so that the drift region extends from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions; a plurality of trenches formed to be recessed to the inside of the semiconductor layer from the surface of the semiconductor layer such that each of the plurality of trenches connects at least two source regions among the plurality of source regions by crossing respective regions in which the plurality of well regions are spaced apart from each other; a gate insulating layer formed on inner walls of the plurality of trenches; a gate electrode layer formed on the gate insulating layer and including a first portion burying the plurality of trenches and a second portion on the surface of the semiconductor layer; and a pillar region having the second conductivity type and located below the plurality of well regions to be in contact with the drift region and the plurality of well regions in the semiconductor layer. According to the present invention, well regions surrounding both edges of a trench are formed so that the magnitude of the electric field concentrated at the edges of the trench can be reduced.

Description

Power semiconductor device and method of manufacturing the same {Power semiconductor device and method of fabricating the same}

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a manufacturing method thereof.

A power semiconductor device is a semiconductor device operating in a high voltage and high current environment. These power semiconductor devices are used in fields requiring high power switching, such as power conversion, power converters, and inverters. Power semiconductor devices include insulated gate bipolar transistors (IGBTs) and power MOSFETs (Power Metal Oxide Semiconductor Field Effect Transistors).

Since these power semiconductor devices are required to satisfy withstand voltage characteristics for high voltages and to perform stable operation at high temperatures, power semiconductor devices using silicon carbide (SiC) instead of conventional silicon (Si) have been actively researched.

As for the characteristics of silicon carbide (SiC), first, it can maintain stability even at high temperatures because it has a higher band gap than silicon. Second, the dielectric breakdown field of silicon carbide is very high compared to silicon, so it can operate stably even at high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, but exhibits excellent heat dissipation and thus exhibits characteristics capable of operating at high temperatures.

However, in the case of a power semiconductor device using silicon carbide, the band gap of the silicon carbide surface rises upward due to the negative charge caused by the trap existing at the gate and silicon carbide interface, resulting in a high threshold voltage and a high channel resistance. there is In addition, there is a limit to increasing the channel density only with the existing planar structure or trench structure.

Embodiments of the present invention may provide the following features.

First, channel density can be increased by realizing a hybrid structure in which the gate electrode layer includes both a trench gate structure and a planar gate structure so that current can flow both under the planar gate electrode layer and through a channel on the sidewall of the trench gate structure.

Second, by forming a pillar region in the drift region to realize a super junction, a higher breakdown voltage can be obtained with the same thickness of the epitaxial layer.

Third, the size of the electric field concentrated at the corner of the trench can be reduced by forming well regions surrounding both edges of the trench.

However, these tasks are illustrative, and the scope of the present invention is not limited thereby.

A power semiconductor device according to an embodiment of the present invention includes a semiconductor layer of silicon carbide (SiC); a plurality of well regions spaced apart from each other in the semiconductor layer and having a second conductivity type; a plurality of source regions formed in the semiconductor layer on the plurality of well regions to be spaced apart from each other and having a first conductivity type opposite to the second conductivity type; a drift region having a first conductivity type and formed in the semiconductor layer so as to be connected to the surface of the semiconductor layer from below the plurality of well regions through between the plurality of well regions; a plurality of trenches formed to be recessed from the surface of the semiconductor layer into the interior of the semiconductor layer so as to connect at least two source regions among the plurality of source regions across the spaced apart portions of the plurality of well regions; a gate insulating layer formed on inner walls of the plurality of trenches; a gate electrode layer formed on the gate insulating layer and including a first portion filling the plurality of trenches and a second portion on the surface of the semiconductor layer; and a pillar region having a second conductivity type and positioned under the plurality of well regions to contact the drift region and the plurality of well regions in the semiconductor layer.

A method of manufacturing a power semiconductor device according to another embodiment of the present invention includes forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a plurality of well regions having a second conductivity type spaced apart from each other in the semiconductor layer; forming a pillar region having a second conductivity type and positioned under the plurality of well regions to contact the drift region and the plurality of well regions in the semiconductor layer; forming a plurality of source regions each having a first conductivity type in the semiconductor layer on the plurality of well regions; forming a plurality of trenches recessed from a surface of the semiconductor layer into an interior of the semiconductor layer to connect at least two source regions among the plurality of source regions across the spaced apart portions of the plurality of well regions; forming a gate insulating layer on inner walls of the plurality of trenches; and forming a gate electrode layer on the gate insulating layer, including a first portion filling the plurality of trenches and a second portion on a surface of the semiconductor layer, wherein the plurality of well regions includes a plurality of well regions. A plurality of well regions from below the regions may be formed to be in contact with the drift region so as to be connected to the surface of the semiconductor layer through a spaced apart part.

The power semiconductor device according to an embodiment of the present invention made as described above can provide the following effects.

First, the degree of integration can be increased by increasing the channel density by allowing current to flow both under the planar gate electrode layer and through the channel on the sidewall of the trench gate structure.

Second, by forming the pillar region in the drift region, the thickness of the epitaxial layer for generating the same breakdown voltage can be formed thinner, thereby reducing the drift resistance and reducing the overall Rsp (Specific Resistance) value.

Third, destruction of the gate insulating layer can be delayed and reliability can be improved by reducing the magnitude of the maximum electric field applied to the insulating layer through the charge sharing effect through the plurality of well regions and the well region protecting the trench corner.

Fourth, it is possible to provide an effect of lowering the JFET resistance and reducing the Rsp value by adjusting the concentrations of the pillar region and the drift region.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a perspective view schematically showing the structure of a power semiconductor device according to an embodiment of the present invention;
FIG. 2 is a plan view illustratively showing a structure cut along a cut line I-I in FIG. 1; FIG.
FIG. 3 is a cross-sectional view exemplarily showing a structure cut along the line II-II in FIG. 2;
4 is a cross-sectional view showing a structure cut along the line III-III in FIG. 2 as an example;
FIG. 5 is a cross-sectional view illustrating a structure cut along a cut line IV-IV in FIG. 2 as an example;
FIG. 6 is a plan view exemplarily showing a structure cut along a cut line V-V in FIG. 1;
7 is a plan view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention;
8 and 9 are cross-sectional views schematically showing the structure of a power semiconductor device according to another embodiment of the present invention.
10 to 12 are cross-sectional views schematically illustrating a method of manufacturing the power semiconductor device of FIG. 1 .
13 is a plan view schematically showing the structure of the power semiconductor device of FIG. 12;
14 is a cross-sectional view schematically illustrating a method of manufacturing a power semiconductor device after FIG. 12;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform you. Also, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. Like symbols in the drawings refer to like elements.

Unless defined otherwise, all terms used herein are used with the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and are therefore provided to illustrate the general structures of the present invention.

Like reference numerals denote like elements. It will be understood that when one element, such as a layer, region, or substrate, is referred to as being on another element, it may be directly on top of or intervening elements may also exist. On the other hand, when referring to a component being “directly on” another component, it is understood that there are no intervening components present.

1 is a perspective view schematically showing the structure of a power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view (horizontal cross-sectional view) exemplarily showing the structure cut along the line I-I in FIG. 1 . 3 is a cross-sectional view exemplarily showing a structure cut along the line II-II in FIG. 2, and FIG. 4 is a cross-sectional view exemplarily showing the structure cut along the line III-III in FIG. 2, and FIG. is a cross-sectional view exemplarily showing a structure cut along the cut line IV-IV in FIG. 2, and FIG. 6 is a plan view (horizontal cross-sectional view) exemplarily showing a structure cut along the cut line V-V in FIG.

1 to 6, the power semiconductor device 100 includes at least a semiconductor layer 105, a gate insulating layer 118, a gate electrode layer 120, a plurality of interlayer insulating layers 130, and a source electrode layer 140. can include For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may include one or a plurality of semiconductor material layers. For example, the semiconductor layer 105 may include one or multiple epitaxial layers. Alternatively, the semiconductor layer 105 may include one or multiple epitaxial layers on a semiconductor substrate. For example, the semiconductor layer 105 may include silicon carbide (SiC). Alternatively, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider band gap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high dielectric breakdown field compared to silicon, so it can operate stably even at high voltage. Therefore, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has excellent heat dissipation characteristics while having a higher breakdown voltage than when silicon is used, and can exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 includes a drain region 102, a drift region 107, a plurality of pillar regions 108, a plurality of well regions 110, and a plurality of sources. It may include source regions 112 , a plurality of well contact regions 114 , and a plurality of trenches 116 .

Here, the drift region 107 may be formed of a first conductivity type (eg, N type), and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by implanting impurities of the first conductivity type into an epitaxial layer of silicon carbide. The drift region 107 may provide a movement path for charges during operation of the power semiconductor device 100 .

The well regions 110 may be formed in the semiconductor layer 105 and may include impurities of the second conductivity type. For example, the well regions 110 may be formed to be spaced apart from the drift region 107 in the semiconductor layer 105 . In some embodiments, the well regions 110 are formed by implanting impurities of a second conductivity type (eg, P-type) opposite to the first conductivity type into the semiconductor layer 105 or the drift region 107 . It can be.

The pillar region 108 may be formed in the semiconductor layer 105 under the well region 110 to be connected to the well region 110 . The pillar region 108 may be formed to contact the drift region 107 to form a super junction with the drift region 107 . For example, the pillar region 108 may be disposed below the well region 110 such that its top surface contacts the well region 110 and its side surface and bottom surface respectively contact the drift region 107 .

The pillar region 108 may be formed in the semiconductor layer 105 to have a conductivity type opposite to that of the drift region 107 so as to form a super junction with the drift region 107 . For example, the pillar region 108 may include impurities of the same second conductivity type as the well region 110 while being opposite to the drift region 107 , and impurities of the second conductivity type of the pillar region 108. Their doping concentration can be adjusted. In some embodiments, the doping concentration of the second conductivity type impurities of the pillar region 108 may be equal to or less than the doping concentration of the second conductivity type impurities of the well region 110 , but is not limited thereto.

For example, FIGS. 1, 3, 4, and 5 show that one pillar region 108 is integrally formed under each well region 110 . However, in another embodiment, a plurality of pillar regions 108 may be formed under each well region 110 . That is, a plurality of pillar regions 108 narrower than the pillar regions 108 shown in FIGS. 1, 3, 4, and 5 may be formed under one well region 110 . In this case, the plurality of pillar regions 108 disposed under one well region 110 may be alternately disposed such that the side surfaces of the drift region 107 come into contact with each other.

In some embodiments, the pillar region 108 may be formed below the well region 110 . According to an embodiment, the pillar region 108 may be narrower than the well region 110 and may be formed by retracting inward from an end of the well region 110 so as to expose at least a portion of the bottom surface of the well region 110 . there is. Accordingly, the well region 110 may protrude further in the direction of the protruding portion 107a of the drift region 107 than the pillar region 108 .

The source regions 112 may be formed in the well regions 110 and have a first conductivity type. For example, the source regions 112 may be formed by implanting first conductivity type impurities into the semiconductor layer 105 or the well region 110 . The source regions 112 may be formed by implanting impurities of the first conductivity type at a higher concentration than the drift region 107 .

A plurality of well contact regions 114 may be formed in the source regions 112 and on the well regions 110 . For example, the well contact regions 114 may be formed on the well regions 110 to pass through the source regions 112 and be connected to the well regions 110 . The well contact regions 114 may include impurities of the second conductivity type.

The well contact regions 114 may be connected to the source electrode layer 140 . The well contact regions 114 may be doped with impurities of the second conductivity type at a high concentration. According to an embodiment, the well contact regions 114 may be doped with impurities of the second conductivity type at a higher concentration than the well regions 110 , but is not limited thereto. For example, the well contact region 114 may be a P+ region.

In some embodiments, the well contact regions 114 may be formed in recess grooves that abut the well regions 110 . In this case, the source electrode layer 140 may be formed to fill the recess groove and be connected to the well contact region 114 .

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may include impurities of the first conductivity type. For example, the drain region 102 may include impurities of the first conductivity type injected at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be formed as a part of the semiconductor layer 105 or may be formed as a substrate separate from the semiconductor layer 105 . Furthermore, the drift region 107 may be formed of one or more epitaxial layers on the drain region 102 .

In some embodiments, the well regions 110 may be formed to be spaced apart from each other in the semiconductor layer 105 . The well regions 110 adjacent to each other among the well regions 110 may be disposed in the semiconductor layer 105 while being spaced apart from each other by a predetermined interval without contacting each other. Two adjacent well regions 110 may be spaced apart from each other by a predetermined distance at the center of the bottom surface of the trench 116 . In this case, the central portion of the bottom of the first portion 120a of the gate electrode layer 120 is exposed as the well regions 110, but at least both bottom edges of the gate electrode layer 120 are covered by the well regions 110. can be surrounded In this embodiment, since the well regions 110 are spaced apart, near the bottom center of the trenches 116 may contact the drift region 107 .

Furthermore, the well regions 110 may have a shape in which the width increases from the surface of the semiconductor layer 105 to the inside of the semiconductor layer 105 and then decreases again. More specifically, the well regions 110 adjacent to each other among the well regions 110 may be spaced apart from each other at a predetermined interval on the surface of the semiconductor layer 105 as shown in FIG. 2 . Also, among the well regions 110 , adjacent well regions 110 may be spaced apart from each other by a predetermined distance at least in a portion having the largest width inside the semiconductor layer 105 , as shown in FIG. 6 .

In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 to pass between the well regions 110 from below the well regions 110 and connect to the surface of the semiconductor layer 105 . For example, the drift region 107 may include protruding portions 107a extending to the surface of the semiconductor layer 105 between the well regions 110 . Here, the protruding portions 107a may represent a region corresponding to a depth from the lowermost end of the well regions 110 to the surface of the semiconductor layer 105 as shown in FIG. 4 . In other words, the protruding portions 107a may correspond to regions positioned in contact with side surfaces of the well regions 110 .

The plurality of trenches 116 may be formed by being recessed from the surface (upper surface) of the semiconductor layer 105 into the interior of the semiconductor layer 105 by a predetermined depth. For example, the trenches 116 may cross spaced portions of the well regions 110 adjacent to each other among the well regions 110 and may include two trenches 116 disposed on both sides of the source regions 112 . It may be formed to connect each of the four source regions 112 . More specifically, each trench 116 includes one source region 112, one well region 110 surrounding the source region 112, the protruding portion 107a of the drift region 107, and an adjacent well. It may be formed in a line type that crosses the region 110 and is connected to an adjacent source region 112 .

For example, the trenches 116 may be formed to penetrate portions of the source regions 112 and to be recessed to a predetermined depth in the well regions 110 and the protruding portions 107a of the drift region 107. can Thus, at least both corners of the trenches 116 may be surrounded by the well regions 110 . Furthermore, when viewed in cross section along the extension direction of the trenches 116 , portions of the bottom surfaces of the trenches 116 may be surrounded by the well regions 110 . For example, the well regions 110 adjacent to each other among the well regions 110 may be formed at or near the bottom surface of the trenches 116 and spaced apart from each other by a predetermined distance, and thus the trenches 116 A part of both sides of the bottom surface of may be surrounded by the well regions 110 at least along a line along the extension direction.

The gate insulating layer 118 may be formed on inner walls of the trenches 116 and at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on inner surfaces of the trenches 116 and on the surface of the semiconductor layer 105 . The thickness of the gate insulating layer 118 may be uniform, or portions formed on the bottom and corners of the trench 116 may be thicker than portions formed on the sidewalls in order to reduce an electric field concentrated at the corner of the trench 116 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, and aluminum oxide, or may include a stacked structure thereof.

The gate electrode layer 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may include a first portion 120a filling the trenches 116 and a second portion 120b on the surface of the semiconductor layer 105 . For example, the first portion 120a of the gate electrode layer 120 may have a trench type gate structure, and the second portion 120b may have a planar type gate structure. Accordingly, the gate electrode layer 120 may have a hybrid structure including both a trench-type gate structure and a planar-type gate structure.

For example, the second portion 120b of the gate electrode layer 120 may be formed on the protruding portions 107a of the drift region 107 and the well regions 110 . More specifically, the second portion 120b of the gate electrode layer 120 includes the protruding portions 107a of the drift region 107 and the well regions 110 exposed on the surface of the semiconductor layer 105. It may be formed on the surface and the surface of a portion of the edge of the source regions 112 . The remaining portions of the well contact regions 114 and the source regions 112 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120 .

At least corner portions of both sides of the bottom surface of the first portion 120a of the gate electrode layer 120 may be surrounded by the well regions 110 . Furthermore, when viewed from a cross-sectional view of the first portion 120a in the elongation direction, portions of both sides of the bottom surface of the first portion 120a may be surrounded by the well regions 110 . For example, portions of the well regions 110 surrounding some corners of the bottom surface of the first portion 120a may gradually become thicker toward the corner portions.

For example, the gate electrode layer 120 may include a conductive material such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include an insulating material for electrical insulation between the gate electrode layer 120 and the source electrode layer 140, for example, an oxide layer, a nitride layer, or a stacked structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 . The source electrode layer 140 may be connected to the source contact region 112 and the well contact region 114 in common. Furthermore, the source electrode layer 140 may be electrically connected to the source regions 112 and the well contact regions 114 . For example, the source electrode layer 140 is connected to the source regions 112 and the well contact regions 114 through a portion exposed by the gate electrode layer 120 and further extends onto the gate electrode layer 120. can be placed. For example, the source electrode layer 140 may include a conductive material such as metal.

The first channel region C1 is connected to the source regions 112 and the drift region 107 along the trenches 116 to correspond to the first portion 120a of the gate electrode layer 120. The semiconductor layer 105 can be formed in For example, the first channel region C1 is a drift region 107 under the trenches 116 or on the side of the trenches 116, for example, the protruding portion 107a of the drift region 107 and the trenches 116 It may be formed in the semiconductor layer 105 along the sidewalls of the trenches 116 so as to connect the source regions 112 in contact with each other. Accordingly, the first channel region C1 may have a trench-type channel structure.

The second channel region C2 may be formed in the semiconductor layer 105 under the second portion 120b of the gate electrode layer 120 to contact the source regions 112 . For example, the second channel region C2 may be formed on the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the source regions 112 . The second channel region C2 may be formed to cover surfaces of the well regions 110 . Accordingly, the second channel region C2 may have a planar channel structure.

For example, the first channel region C1 and the second channel region C2 may have a first conductivity type such that an accumulation channel is formed. The first channel region C1 and the second channel region C2 may have a doping type opposite to that of the well regions 110 .

For example, the first channel region C1 and the second channel region C2 form an inversion channel (first conductivity type) by applying a gate bias in the well region 110 of the second conductivity type (P type). Alternatively, when the well region 110 is formed, the first channel region C1 is formed by increasing the electron density by forming an accumulation channel (first conductivity type) by making the surface have a relatively low second conductivity type through energy control. and channel resistance of the second channel region C2 may be reduced.

Also, the first channel region C1 and the second channel region C2 may have the same doping type as the source region 112 and the drift region 107 . In this case, the source region 112, the first channel region C1 or the second channel region C2, and the drift region 107 have a structure that can be electrically connected normally. However, in the structure of the semiconductor layer 105 made of silicon carbide, the first channel region C1 and the second channel region C1 and the second channel region have negative charges due to traps present at the interface between the gate insulating layer 118 and silicon carbide. As the band of (C2) bends upward, a potential barrier is formed. Due to this, the movement of the current may be blocked.

Accordingly, as in the present embodiment, even if the source regions 112 are formed to contact the vertical portions 107a of the drift region 107, the flow of current is stopped only when an operating voltage is applied to the gate electrode layer 120. A permissive channel may be formed. Here, the operating voltage (threshold voltage) to be applied to the gate electrode layer 120 to form a channel in the first channel region C1 or the second channel region C2 is the gate electrode layer 120 to form a normal channel. ) may be significantly lower than the operating voltage that should be applied to

For example, the first channel region C1 and the second channel region C2 may be portions of the well regions 110 . More specifically, the first channel region C1 may be a portion of the well regions 110 adjacent to the lower portion of the first portion 120a of the gate electrode layer 120 . Also, the second channel region C2 may be a portion of the well regions 110 adjacent to the lower portion of the second portion 120b of the gate electrode layer 120 . That is, the second channel region C2 may correspond to a region between the protruding portion 107a of the drift region 107 and the source region 112 .

In this case, the first channel region C1 and the second channel region C2 may be integrally or continuously connected to the well region 110 . Doping concentrations of first conductivity type impurities in the first channel region C1 and the second channel region C2 may be adjusted according to the threshold voltage value.

The second channel region C2 and the source region 112 may be connected to both side walls of the vertical portion 107a. The vertical portion 107a of the drift region 107 connected in this way, the second channel region C2 and the source region 112 may become a current movement path when the power semiconductor device 100 operates.

In some embodiments, intervals between three adjacent well regions 110 of the well regions 110 may be the same. Furthermore, the spacing of each of the three adjacent source regions 112 of the source regions 112 may be equal to each other. For example, the center of each of the three adjacent well regions 110 may be disposed at the vertex of an equilateral triangle, and the center of each of the three adjacent source regions 112 on the well regions 110 is also the same equilateral triangle. can be placed at the vertex of For example, it may be understood that the well regions 110 and the source regions 112 refer to three arranged in a triangle in FIG. 2 .

In some embodiments, the centers of each of the seven adjacent well regions 110 among the well regions 110 may be disposed at the center and vertices of the regular hexagon. Furthermore, the centers of each of the seven source regions 112 on each of the seven adjacent well regions 110 among the source regions 112 may be disposed at the center and vertices of the regular hexagon. For example, it may be understood that FIGS. 1 to 5 illustrate these seven well regions 110 and seven source regions 112 .

In this structure, the well regions 110 and the source regions 112 may be disposed similarly to a planar arrangement structure in a hexagonal closed packed arrangement structure. Further, the intervals between adjacent well regions 110 may be all the same, and the intervals between adjacent source regions 112 may also be all the same.

In this structure, the trenches 116 may be arranged to form portions of lines connecting between the center of the regular hexagon and two adjacent vertices to connect each of the seven adjacent source regions 112 . More specifically, the trenches 116 in FIG. 2 include six lines connecting one source region 112 disposed at the center of a regular hexagon to six source regions 112 disposed at vertices; It may include six lines connecting two adjacent six source regions 112 disposed at vertices.

In some embodiments, well regions 110 may be a portion of a spherical shape. A planar cross section of the well regions 110 is circular in a region including the source region 112 and the well contact region 114, and ring in a region not including the source region 112 and the well contact region 114. It can be shaped or donut shaped. Furthermore, the well contact regions 114 may be formed in a ring shape or a donut shape when viewed in plan view. For example, when viewed in plan view, ring-shaped well contact regions 114 are formed in the ring-shaped well regions 110, and circular source regions are formed in the ring-shaped well contact regions 114. (112) may be formed. The well contact regions 114 may be connected to the well regions 110 at the bottom. When viewed from a plan view, the source regions 112 may be formed in a donut shape surrounding the well contact regions 114 . This planar shape may extend from the surface of the semiconductor layer 105 to a predetermined depth.

In some embodiments, a portion of the well regions 110 below the bottom surface of the trenches 116 , for example, a first channel region C1 formed in the well regions 110 near the center of the bottom surface of the trenches 116 . may be connected to the protruding portion 107a below the corresponding portion.

As another example, when the overall thickness of the well regions 110 under the bottom surface of the trenches 116 is thicker than the first channel region C1, the first channel region C1 is the drift region below the trenches 116. It is difficult to connect with (107). However, when the well regions 110 have a spherical shape, since at least the side surfaces of the trenches 116 are exposed from the well regions 110 and are surrounded by the protruding portions 107a of the drift regions 107, the first The one-channel region C1 is connected to the source regions 112 from the protruding portion 107a of the drift region 107 on the sidewall of the trenches 116 or the sidewall of the first portion 120a of the gate electrode layer 120. can

In the above-described embodiment, the first conductivity type and the second conductivity type have opposite conductivity types, and the first conductivity type is N-type and the second conductivity type is P-type. However, the opposite may be true. .

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, and the first channel region C1 ) and the second channel region C2 may be an N- region, the well region 110 and the pillar region 108 may be a P- region, and the well contact region 114 may be a P+ region.

According to the power semiconductor device 100 , depths of the well regions 110 may be greater than those of the trenches 116 and the gate electrode layer 120 . Accordingly, both edges of the trench bottom of the first portion 120a of the gate electrode layer 120 may be surrounded by the well regions 110 . Furthermore, some of the edges of both sides of the bottom surface of the first portion 120a may be surrounded by the well regions 110, and such a structure is such that an electric field is generated at some edges of the trench bottom in a trench-type gate structure. It can alleviate the concentrated part.

When an operating voltage is applied to the gate electrode layer 120, an electric field may be concentrated on both lower corner portions of the gate electrode layer 120, and when the electric field is concentrated, the gate insulating layer 118 in the corresponding region is subjected to severe stress, so that the gate Dielectric breakdown of the insulating layer 118 may occur. Therefore, in the present embodiment, in the gate electrode layer 120, the lower side corner regions of the portions formed in the well region 110 are surrounded by the P-type well region 110 to achieve charge sharing, thereby insulating the gate. It is possible to prevent dielectric breakdown of the gate insulating layer 118 by concentrating the electric field on both corner portions of the layer 118 .

During operation of the power semiconductor device 100, current mainly flows in a vertical direction from the drain region 102 along the drift region 107, and then flows through the first channel region C1 and the second channel region C2 to the source. can flow into region 112 .

The power semiconductor device 100 may have a hybrid structure including both a trench-type structure and a planar-type structure. Furthermore, the power semiconductor device 100 may have a regular hexagonal arrangement structure and a high degree of integration by implementing a high channel density by combining a trench structure and a planar structure. Furthermore, the power semiconductor device 100 may increase channel mobility while maintaining integration due to the addition of a trench type structure compared to the case of having only a planar structure.

Meanwhile, since the power semiconductor device 100 is used for high-power switching, high withstand voltage characteristics are required. When a high voltage is applied to the drain region 102 , a depletion region may be extended from the semiconductor layer 105 adjacent to the drain region 102 , and thus a voltage barrier of a channel may be lowered. This phenomenon is called drain induced barrier lowering (DIBL).

Such DIBL may cause abnormal turn-on of the first channel region C1 and the second channel region C2, and furthermore, the depletion layer between the drain region 102 and the source region 112 expands and contacts. This can lead to punch through.

However, in the power semiconductor device 100 described above, the drift region 107, the first channel region C1 and the second channel region ( The resistance of C2) can be reduced, and proper withstand voltage characteristics can be secured by suppressing the abnormal current flow and punch-through phenomenon caused by DIBL. Therefore, even if the thickness of the drift region 107 constituting the body is reduced, a high breakdown voltage can be maintained.

In addition, in the power semiconductor device 100, since a current flows through the vertical portions 107a of the drift region 107, a current movement path may be narrowed and resistance (JFET resistance) may increase. However, in the power semiconductor device 100 according to the present embodiment, the JFET resistance can be reduced by using the drift region 107 and the pillar region 108 forming a super junction. For example, the JFET resistance may be reduced by adjusting the amount of charge in the pillar region 108 and the amount of charge in the drift region 107 .

That is, when the amount of charge in the pillar region 108 is greater than the amount of charge in the drift region 107, the maximum electric field during operation of the power semiconductor device 100 is on the same line as the bottom surface of the pillar region 108 in the drift region 107. ), the breakdown voltage can be increased. For example, by making the doping concentration of impurities of the second conductivity type in the pillar region 108 higher than the doping concentration of impurities of the first conductivity type in the drift region 107, the amount of electric charge in the pillar region 108 is reduced in the drift region ( 107), it is possible to improve the withstand voltage characteristics of the power semiconductor device 100 and reduce the JFET resistance.

7 is a plan view (horizontal cross-sectional view) illustrating a power semiconductor device 100a according to another embodiment of the present invention.

Referring to FIG. 7 , the power semiconductor device 100a shows a portion of a structure in which a plurality of power semiconductor devices 100 of FIGS. 1 to 6 are disposed, and the same reference numerals may be used, and redundant descriptions are omitted. do.

The power semiconductor device 100a may have a high degree of integration by repeating the hexagonal dense arrangement structure disclosed in FIGS. 1 to 6 .

8 and 9 are cross-sectional views showing a power semiconductor device 100b according to another embodiment of the present invention. The power semiconductor device 100b is obtained by modifying some configurations of the power semiconductor device 100 of FIGS. 1 to 6 and may be referred to each other, and redundant descriptions are omitted.

Referring to FIGS. 8 and 9 , in the power semiconductor device 100b, the second channel region C2a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the second channel region C2a may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The second channel region C2a may include impurities of the first conductivity type to form an accumulation channel. Here, the storage channel may mean that holes are accumulated in the P-type well region 110, which is the second conductivity type. However, in an embodiment of the present invention, forming a channel of the first conductivity type by adjusting the energy for forming the well region 110 to form a low concentration second conductivity type (eg, P type) on the surface, and All cases of producing the same effect or ion implantation of impurities of the first conductivity type are used as the term accumulation channel.

For example, the second channel region C2a may have the same doping type as the source region 112a and the drift region 107 . In this case, the source region 112, the second channel region C2a, and the drift region 107 have a structure that can be electrically connected normally. However, since the semiconductor layer 105 of silicon carbide has a negative charge due to a trap at the interface with the gate insulating layer, the band of the second channel region C2a bends upward to form a potential barrier. The threshold voltage rises. However, if the well is formed to have a low concentration of the second conductivity type on the surface, the threshold voltage applied to the gate electrode layer 120 may be lowered.

In some embodiments, the second channel region C2a may be a part of the drift region 107 . More specifically, the second channel region C2a may be a part of the protruding portion 107a of the drift region 107 . For example, the second channel region C2a may be integrally formed with the drift region 107 . Accordingly, in the power semiconductor device 100b, the source regions 112a are in direct contact with the drift region 107, for example, the protruding portions 107a, and the second channel is formed in a portion of the drift region 107 in the contact region. Area C2a may be limited.

For example, the doping concentration of the dopant of the first conductivity type of the second channel region C2a may be adjusted to adjust the threshold voltage.

In some embodiments, the well regions 110 may be formed below the source regions 112a to protrude in the direction of the protruding portion 107a of the drift region 107 more than the source regions 112a. In this case, the second channel region C2a may be formed on the semiconductor layer 105 on the protruding portions of the well regions 110 . For example, the protruding portion 107a of the drift region 107 may further extend to a groove portion between the well regions 110 and the second portion 120b of the gate electrode layer 120, and the second channel region (C2a) may be formed in this part. In this structure, the second channel region C2a may be limited between the second portion 120b of the gate electrode layer 120 and the well regions 110 .

In the power semiconductor device 100b, the first channel region C1 may serve as an accumulation channel similarly to the power semiconductor device 100 of FIGS. 1 to 6 .

10 to 12 and 14 are cross-sectional views illustrating a method of manufacturing a power semiconductor device 100 according to an embodiment of the present invention, and FIG. 13 is a plan view (vertical cross-sectional view) of FIG. 12 .

Referring to FIG. 10 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC) to provide a vertical movement path for charges. For example, the drift region 107 may be formed on the drain region 102 having the first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of a first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

Subsequently, well regions 110 having a second conductivity type may be formed in the semiconductor layer 105 to contact the drift region 107 . For example, the well regions 110 adjacent to each other among the well regions 110 may be formed to be spaced apart from each other by a predetermined distance without contacting each other. Furthermore, the forming of the well regions 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105 . The well regions 110 may be substantially formed to a predetermined depth from the surface of the semiconductor layer 105 .

For example, the well regions 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes protruding portions 107a at least partially surrounded by the well region 110 . More specifically, the well regions 110 may be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107 .

The pillar region 108 may be formed in contact with the well region 110 in the semiconductor layer 105 under the well region 110 . The pillar region 108 may have a second conductivity type to form a super junction with the drift region 107 . For example, the pillar region 108 may be formed by implanting impurities of the second conductivity type into the drift region 107 .

Source regions 112 having a first conductivity type may be formed in the well regions 110 or in the semiconductor layer 105 on the well regions 110 . For example, the forming of the source regions 112 may be performed by implanting impurities of the first conductivity type into the well regions 110 and the drift region 107 . The source regions 112 may be formed substantially from the surface of the semiconductor layer 105 to a predetermined depth within the well region 110 .

Furthermore, well contact regions 114 having a second conductivity type may be formed in the source regions 112 and on the well regions 110 . For example, the well contact regions 114 may be formed by implanting dopants of the second conductivity type at a high concentration into the well regions 110 or the source regions 112 . For example, the well contact regions 114 may be formed to have a circular shape in plan view.

In some embodiments, the well regions 110 have a drift region 107 such that the drift region 107 is connected to the surface of the semiconductor layer 105 by passing between the well regions 110 from under the well regions 110 . It can be formed to come into contact with.

In a modified example of this embodiment, the impurity doping order of the well regions 110, the pillar regions 108, the well contact regions 114, and the source regions 112 may be arbitrarily changed.

In the above-described manufacturing method, impurity implantation or impurity doping may be performed by ion implanting impurities into the semiconductor layer 105 or mixing impurities during formation of the epitaxial layer. However, an ion implantation method using a mask pattern may be used for impurity implantation in a selective region.

Optionally, the ion implantation may be followed by a heat treatment step to activate or diffuse impurities.

Referring to FIG. 11 , a plurality of trenches 116 may be formed to be recessed by a predetermined depth from the surface of the semiconductor layer 105 into the inside of the semiconductor layer 105 .

For example, the trenches 116 may be formed to penetrate portions of the source regions 112 and be recessed to a predetermined depth in the well regions 110 and the protruding portions 107a of the drift region 107. can More specifically, the trenches 116 are disposed on both sides of the trenches 116 in the source regions 112 across spaced portions of the well regions 110 adjacent to each other among the well regions 110 . It may be formed to be recessed from the surface of the semiconductor layer 105 to the inside of the semiconductor layer 105 so as to connect the two source regions 112 respectively.

For example, the trenches 116 may be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 using the photomask as an etch protection layer.

Referring to FIGS. 12 and 13 , a gate insulating layer 118 may be formed on inner walls of the trenches 116 and a surface of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed of oxide by oxidizing the semiconductor layer 105 or by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Subsequently, gate electrode layers 120 including a first portion 120a filling the trenches 116 on the gate insulating layer 118 and a second portion 120b on the surface of the semiconductor layer 105 are formed. can do. Here, the gate electrode layers 120 are not formed in some regions of the well contact regions 114 and the source regions 112 adjacent to the well contact regions 114 . For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping polysilicon with impurities or may include a conductive metal or metal silicide.

The patterning process may be performed using photo lithography and etching processes. The photolithography process includes a process of forming a photo resist pattern as a mask layer using a photo process and a development process, and the etching process includes a process of selectively etching a lower structure using the photoresist pattern. can do.

Referring to FIG. 14 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

Subsequently, a source electrode layer 140 may be formed on the interlayer insulating layer 130 . Furthermore, the source electrode layer 140 may be formed to be connected to the source regions 112 and the well contact regions 114 . For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning the conductive layer.

According to the manufacturing method described above, it is possible to economically form a MOSFET structure having a hexagonal close-packed arrangement in the semiconductor layer 105 .

As described above, the power semiconductor device according to the embodiment of the present invention may have advantages in vertical and horizontal aspects by forming a super junction in a MOSFET structure having a three-dimensional hexagonal dense arrangement. In the vertical aspect, a high breakdown voltage can be formed at the same thickness of the drift region 107 (epitaxial layer) compared to the two-dimensional MOSFET structure due to the higher spatial charge sharing effect. Since the thickness of the epitaxial layer is thinner at the same breakdown voltage, the drift resistance can be reduced and the total resistance (Rsp) can be reduced. On the horizontal side, in the case of complete depletion, the charge sharing effect occurs horizontally between the pillar region 108 and the drift region 107 (epitaxial layer), resulting in a trench-type gate insulating layer or a planar gate insulating layer. Reliability of the gate oxide layer can be improved by reducing the magnitude of the applied maximum electric field.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100, 100a, 100b: power semiconductor device
102: drain area
105: semiconductor layer
107: drift area
108: pillar area
110: well area
112: source area
114: well contact area
116: trench region
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (20)

a semiconductor layer of silicon carbide (SiC);
a plurality of well regions spaced apart from each other in the semiconductor layer and having a second conductivity type;
a plurality of source regions formed in the semiconductor layer on the plurality of well regions to be spaced apart from each other and having a first conductivity type opposite to the second conductivity type;
a drift region having the first conductivity type and formed in the semiconductor layer to be connected to a surface of the semiconductor layer from below the plurality of well regions through between the plurality of well regions;
a plurality of trenches formed to be recessed from a surface of the semiconductor layer into the interior of the semiconductor layer to connect at least two source regions among the plurality of source regions, respectively, across the spaced apart portions of the plurality of well regions;
a gate insulating layer formed on inner walls of the plurality of trenches;
a gate electrode layer formed on the gate insulating layer and including a first portion filling the plurality of trenches and a second portion on a surface of the semiconductor layer; and
and a pillar region having the second conductivity type and positioned under the plurality of well regions to contact the drift region and the plurality of well regions in the semiconductor layer. According to claim 1,
Intervals at which three adjacent well regions of the plurality of well regions are spaced apart are equal to each other;
A distance at which three adjacent source regions of the plurality of source regions are spaced apart is equal to each other. According to claim 1,
The drift region includes protruding portions extending to the surface of the semiconductor layer between spaced apart portions of each of the three adjacent well regions among the plurality of well regions,
The second part of the gate electrode layer is formed on a part where the plurality of adjacent well regions are spaced apart and on the protruding part of the drift region. According to claim 1,
Centers of each of the 7 adjacent well regions among the plurality of well regions are arranged at the center and vertices of a regular hexagon,
Centers of each of the 7 source regions on each of the 7 adjacent well regions among the plurality of source regions are disposed at the center and vertices of the regular hexagon. According to claim 4,
The plurality of trenches form part of lines connecting two adjacent source regions among the centers and vertices of the regular hexagon to connect each of the seven adjacent source regions. According to claim 1,
a first channel region defined in the semiconductor layer to correspond to the first portion of the gate electrode layer and to be connected to the drift region along the plurality of trenches and to the source regions contacting the plurality of trenches; and
and a second channel region defined in the semiconductor layer to contact the plurality of source regions under the second portion of the gate electrode layer. According to claim 6,
The first channel region and the second channel region are formed by forming an inversion channel of the first conductivity type in the plurality of well regions formed of the second conductivity type or adjusting energy during formation of the plurality of well regions to form a surface A relatively low concentration of the second conductivity type is formed to form an accumulation channel of the first conductivity type;
The first channel region and the second channel region are parts of the plurality of well regions. According to claim 6,
the first channel region and the second channel have the first conductivity type such that an inversion channel and an accumulation channel are formed;
the first channel region and the second channel region are portions of the drift region;
The plurality of source regions on the surface of the semiconductor layer are in contact with the drift region. According to claim 1,
a plurality of well contact regions formed in the plurality of source regions and on the plurality of well regions and having the second conductivity type; and
The power semiconductor device further includes a source electrode layer connected to the plurality of source regions and the plurality of well contact regions. According to claim 9,
The plurality of well contact regions are formed in a circular shape when viewed in plan view;
The plurality of source regions are formed in a donut shape surrounding the plurality of well contact regions. According to claim 1,
The plurality of well regions have a shape in which a width increases and then decreases again from the surface of the semiconductor layer to the inside of the semiconductor layer,
Adjacent well regions among the plurality of well regions are spaced apart from each other in the interior of the semiconductor layer and on the surface of the semiconductor layer. According to claim 1,
When viewed in a cross section of the first portion of the gate electrode layer in the extension direction, corners of bottom surfaces of both sides of the first portion are surrounded by the plurality of well regions. According to claim 1,
A central portion of a bottom of the first portion of the gate electrode layer is exposed to the well regions, and a central portion of a bottom of each of the plurality of trenches contacts the drift region. According to claim 1,
a drain region having the first conductivity type in the semiconductor layer under the drift region;
The drift region is formed as an epitaxial layer on the drain region. forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC);
forming a plurality of well regions having a second conductivity type spaced apart from each other in the semiconductor layer;
forming a pillar region having the second conductivity type and positioned under the plurality of well regions to contact the drift region and the plurality of well regions in the semiconductor layer;
forming a plurality of source regions each having a first conductivity type in the semiconductor layer on the plurality of well regions;
Forming a plurality of trenches recessed from the surface of the semiconductor layer into the interior of the semiconductor layer to connect at least two source regions among the plurality of source regions across the spaced apart portions of the plurality of well regions, respectively. step;
forming a gate insulating layer on inner walls of the plurality of trenches; and
Forming a gate electrode layer on the gate insulating layer, including a first portion filling the plurality of trenches and a second portion on a surface of the semiconductor layer;
The plurality of well regions are formed to be in contact with the drift region such that the drift region is connected to the surface of the semiconductor layer through a part where the plurality of well regions are separated from below the plurality of well regions. Way. According to claim 15,
The method of manufacturing a power semiconductor device in which the plurality of well regions are formed to have a shape in which a width of the well region increases from the surface of the semiconductor layer to the inside of the semiconductor layer and then decreases again. According to claim 16,
The method of manufacturing a power semiconductor device in which well regions adjacent to each other among the plurality of well regions are formed to be spaced apart from each other in the interior of the semiconductor layer and on the surface of the semiconductor layer. According to claim 15,
The forming of the plurality of well regions includes forming centers of each of the 7 adjacent well regions among the plurality of well regions to be disposed at the center and vertices of a regular hexagon. According to claim 15,
The method of manufacturing a power semiconductor device further comprising forming a plurality of well contact regions having a second conductivity type in the plurality of source regions and on the plurality of well regions. According to claim 19,
The method of manufacturing a power semiconductor device further comprising forming a source electrode layer to be connected to the plurality of source regions and the plurality of well contact regions.

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