KR20220080835A - Gate circuit and display device - Google Patents

Abstract

Embodiments of the present invention relate to a gate circuit and a display device, and by arranging a plurality of sub-switching transistors electrically connected between a QB node and a first gate driving voltage in the gate circuit, control of the QB node is more stably performed provide a way to do it. In addition, by preventing AC stress from being applied to the source node of the switching transistor that performs control of the QB node during the period in which the gate circuit outputs the scan signal of the turn-off level, the deterioration or delay of the switching transistor is reduced or delayed and reliability and reliability are improved. It is possible to provide a gate circuit having an improved lifespan.

Description

GATE CIRCUIT AND DISPLAY DEVICE

Embodiments of the present invention relate to a gate circuit and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing, and various types of display devices such as a liquid crystal display device and an organic light emitting display device are utilized.

The display device may include a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are disposed, and several driving circuits for driving the display panel. For example, the display device may include a gate driving circuit driving a plurality of gate lines, a data driving circuit driving the plurality of data lines, and a controller controlling the gate driving circuit and the data driving circuit.

The gate driving circuit may supply a scan signal to the gate line at a predetermined timing and may control the driving timing of the subpixel connected to the gate line.

The gate driving circuit may include several circuit elements for outputting a scan signal. Various circuit elements included in the gate driving circuit may deteriorate as the driving time increases, and an output abnormality of the scan signal may occur due to deterioration of the circuit elements included in the gate driving circuit.

Since driving of the sub-pixels is controlled according to the scan signal supplied by the gate driving circuit, when an output abnormality of the scan signal occurs, an image displayed through the display panel may be abnormal.

Accordingly, there is a need for a method capable of improving the stability of the scan signal output of the gate driving circuit and improving the reliability.

SUMMARY Embodiments of the present invention provide a method for reducing deterioration of circuit elements included in a gate driving circuit and improving reliability and lifespan of the gate driving circuit.

Embodiments of the present invention provide a method for stably outputting a signal supplied to a gate line by a gate driving circuit and preventing an image abnormality due to an abnormal signal output of the gate driving circuit.

Embodiments of the present invention provide a plurality of subpixels disposed on a display panel, a plurality of gate lines disposed on the display panel and electrically connected to at least one subpixel of the plurality of subpixels, and a plurality of gate lines. A display device including a plurality of gate circuits for driving is provided.

In one aspect, each of the plurality of gate circuits is controlled by a QB node and drives a first gate, a pull-up transistor controlled by a Q node and electrically connected between an input end of the first gate clock signal and an output end of the scan signal At least one first switching controlled by a pull-down transistor electrically connected between the input terminal of the voltage and the output terminal of the scan signal, and a Q1 node electrically connected to the Q node and electrically connected between the input terminal of the gate start signal and the QB node It may include a transistor.

After a turn-on level scan signal is output through an output terminal of the scan signal, before a gate start signal of a level for turning on at least one first switching transistor is inputted, the input terminal of the gate start signal and at least one first switching The voltage level at the node between the transistors may be kept constant.

Each of the plurality of gate circuits includes a first sub-switching transistor controlled by a Q1 node and electrically connected to the QB node, and a first sub-switching transistor controlled by a first gate clock signal and between an input terminal of the first gate driving voltage and the first sub-switching transistor. It may further include a second sub-switching transistor electrically connected to.

A period in which the first sub-switching transistor and the second sub-switching transistor are simultaneously turned on may be a part of a period in which the at least one first switching transistor is turned on.

In another aspect, each of the plurality of gate circuits is a pull-up transistor controlled by a Q node and electrically connected between an input end of a first gate clock signal and an output end of a scan signal, controlled by a QB node and driving a first gate At least one first pull-down transistor electrically connected between the input terminal of the voltage and the output terminal of the scan signal, controlled by a Q1 node electrically connected to the Q node, and electrically connected between the input terminal of the second gate clock signal and the QB node It may include a switching transistor, and a degradation delay transistor electrically connected between the input terminal of the second gate clock signal and the at least one first switching transistor and having a gate node electrically connected to the at least one first switching transistor.

Between the deterioration delay transistor and the at least one first switching transistor after the turn-on level scan signal is output through the output terminal of the scan signal and before the gate start signal of the level for turning on the at least one first switching transistor is input The voltage level of the node of may be kept constant.

Each of the plurality of gate circuits includes a first sub-switching transistor controlled by a Q1 node and electrically connected to the QB node, and a first sub-switching transistor controlled by a first gate clock signal and between an input terminal of the first gate driving voltage and the first sub-switching transistor. It may further include a second sub-switching transistor electrically connected to.

A turn-on level scan signal may be output through an output terminal of the scan signal during a period in which the first sub-switching transistor and the second sub-switching transistor are simultaneously turned on.

In another aspect, each of the plurality of gate circuits is a pull-up transistor controlled by a Q node and electrically coupled between an input end of the first gate clock signal and an output end of the scan signal, controlled by a QB node and a first gate A pull-down transistor electrically connected between the input terminal of the driving voltage and the output terminal of the scan signal, at least one first switching transistor controlled by a Q1 node electrically connected to the Q node and controlling the voltage level of the QB node, to the Q1 node a first sub-switching transistor controlled by and electrically connected to the QB node, and a second sub-switching transistor controlled by a first gate clock signal and electrically connected between the input terminal of the first gate driving voltage and the first sub-switching transistor; can do.

According to embodiments of the present invention, by reducing the stress applied to the switching transistor controlling the voltage level of the QB node of the gate driving circuit, deterioration of the switching transistor can be reduced and reliability and lifespan of the gate driving circuit can be improved. .

According to embodiments of the present invention, by arranging a sub-switching transistor capable of controlling the QB node between the QB node of the gate driving circuit and the input terminal of the gate high voltage, the stability of the signal output of the gate driving circuit is improved and the gate driving It is possible to prevent an image abnormality due to an abnormal signal output of the circuit.

1 is a diagram schematically illustrating a configuration included in a display device according to embodiments of the present invention.
2 is a diagram schematically illustrating a configuration of a gate circuit included in a gate driving circuit according to embodiments of the present invention.
3 is a diagram illustrating an example of a driving state of a sub-pixel when a gate circuit is abnormally driven according to embodiments of the present invention.
4 is a diagram illustrating an example of a structure of a gate circuit according to embodiments of the present invention.
5 to 8 are diagrams illustrating examples of a driving method of the gate circuit shown in FIG. 4 .
9 is a diagram illustrating an example of stress applied to a circuit element in the gate circuit when the gate circuit shown in FIG. 4 is driven.
10 to 12 are diagrams illustrating another example of a structure of a gate circuit according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when it is described that two or more components are "connected", "coupled" or "connected", two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal relationship or flow relationship of the components, for example, a temporal precedence or flow precedence relationship is When described, cases that are not continuous unless "immediately" or "directly" are used may also be included.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no separate explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a diagram schematically illustrating a configuration included in a display apparatus 100 according to embodiments of the present invention.

Referring to FIG. 1 , the display device 100 includes a display panel 110 , a gate driving circuit 120 for driving the display panel 110 , a data driving circuit 130 , a controller 140 , and the like. can do.

The display panel 110 may include an active area AA in which a plurality of subpixels SP are disposed, and a non-active area NA positioned outside the active area AA.

A plurality of gate lines GL and a plurality of data lines DL may be disposed on the display panel 110 . The subpixel SP may be positioned in a region where the gate line GL and the data line DL intersect.

The gate driving circuit 120 is controlled by the controller 140 , and sequentially outputs scan signals to the plurality of gate lines GL disposed on the display panel 110 to drive timing of the plurality of subpixels SP. to control

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and may be located on only one side or both sides of the display panel 110 depending on the driving method. may be

Each gate driver integrated circuit GDIC may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method. Alternatively, each gate driver integrated circuit (GDIC) may be implemented as a GIP (Gate In Panel) type and disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. . Alternatively, each gate driver integrated circuit GDIC may be implemented in a chip on film (COF) method mounted on a film connected to the display panel 110 .

The data driving circuit 130 receives a data signal from the controller 140 and converts the data signal into an analog data voltage Vdata. In addition, the data voltage Vdata is output to each data line DL according to the timing at which the scan signal is applied through the gate line GL so that each subpixel SP expresses the brightness according to the data signal. .

The data driving circuit 130 may include one or more source driver integrated circuits (SDICs).

Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

Each source driver integrated circuit SDIC may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method. Alternatively, each source driver integrated circuit SDIC may be directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. Alternatively, each source driver integrated circuit (SDIC) may be implemented in a chip-on-film (COF) method, in this case, each source driver integrated circuit (SDIC) is mounted on a film connected to the display panel 110 and , may be electrically connected to the display panel 110 through wires on the film.

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 , and controls operations of the gate driving circuit 120 and the data driving circuit 130 .

The controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the printed circuit board or the flexible printed circuit. .

The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts image data received from the outside to match the signal format used by the data driving circuit 130 , The converted data signal may be output to the data driving circuit 130 .

The controller 140 externally transmits various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK) together with the image data. Receive from (eg host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130 .

For example, in order to control the gate driving circuit 120 , the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE: Gate Output Enable) and the like may output various gate control signals GCS.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits GDIC constituting the gate driving circuit 120 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits GDIC, and controls shift timing of the scan signal. The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits GDIC.

In addition, in order to control the data driving circuit 130 , the controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Output Enable) and the like may output various data control signals DCS.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits SDIC constituting the data driving circuit 130 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130 .

The display device 100 supplies various voltages or currents to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , or the like, or a power management integrated circuit for controlling various voltages or currents to be supplied. may include

Each subpixel SP may be a region defined by the intersection of the gate line GL and the data line DL, and at least one circuit element including a light emitting element may be disposed thereon.

For example, when the display device 100 is a liquid crystal display device, the display panel 110 may include a liquid crystal layer. In addition, the arrangement of the liquid crystal may be adjusted according to the electric field formed by each of the plurality of sub-pixels SP, the brightness of the sub-pixels SP may be adjusted, and an image may be displayed.

As another example, when the display device 100 is an organic light emitting display device, an organic light emitting diode (OLED) and various circuit elements may be disposed in the plurality of subpixels SP. By controlling the current supplied to the organic light emitting diode (OLED) disposed in the subpixel (SP) by various circuit elements, each subpixel (SP) may display brightness corresponding to image data.

Alternatively, in some cases, a light emitting diode (LED) or a micro light emitting diode (μLED) may be disposed in the subpixel SP.

As such, the display apparatus 100 may control the driving timing of the sub-pixel SP according to the scan signal supplied by the gate driving circuit 120 , and display an image through the display panel 110 .

The gate driving circuit 120 may output a scan signal to the plurality of gate lines GL, and may include a plurality of gate circuits controlling at least one gate line GL among the plurality of gate lines GL. can

2 is a diagram schematically illustrating a configuration of a gate circuit included in the gate driving circuit 120 according to embodiments of the present invention.

Referring to FIG. 2 , the gate circuit may include a pull-up transistor Tup controlled by a Q node and a pull-down transistor Tdn controlled by a QB node. The pull-up transistor Tup may control the output of the gate signal GOUT of the turn-on level, and the pull-down transistor Tdn may control the output of the gate signal GOUT of the turn-off level. have.

The gate signal GOUT may be a scan signal supplied to the subpixel SP or a light emission control signal.

The gate circuit may include a plurality of transistors and at least one capacitor for controlling the voltage level of the Q node and the voltage level of the QB node.

The gate circuit may receive various signals and voltages, and may output the gate signal GOUT according to the driving of the pull-up transistor Tup and the pull-down transistor Tdn by the Q node and the QB node.

For example, the gate circuit may receive a gate start signal GVST and at least one gate clock signal GCLK for controlling driving timing. The gate start signal GVST may be a carry signal output from another gate circuit.

The gate circuit may receive one or more driving voltages, and may receive a first gate driving voltage VGH and a second gate driving voltage VGL as inputs. For example, the first gate driving voltage VGH may be a high potential driving voltage and the second gate driving voltage VGL may be a low potential driving voltage.

The gate circuit may control the Q node and the QB node according to various signals and voltages inputted thereto, and may output the gate signal GOUT at a predetermined timing.

Circuit elements controlling the Q node and the QB node in the gate circuit may be configured in various ways, and circuit elements included in the gate circuit may be deteriorated according to the driving of the gate circuit.

When a driving abnormality of the gate circuit occurs due to deterioration of a circuit element included in the gate circuit, an abnormality in the gate signal GOUT supplied to the subpixel SP may occur. When an abnormality occurs in the gate signal GOUT output from the gate circuit, an image abnormality may occur due to an abnormal driving of the subpixel SP.

3 is a diagram illustrating an example of a driving state of a sub-pixel SP when a gate circuit is abnormally driven according to embodiments of the present invention.

Referring to FIG. 3 , the subpixel SP may include a light emitting device ED and various circuit devices for driving the light emitting device ED.

For example, the sub-pixel SP may include a driving transistor DRT for controlling a driving current supplied to the light emitting device ED.

The subpixel SP may include six transistors T1 , T2 , T3 , T4 , T5 , and T6 in addition to the driving transistor DRT. The sub-pixel SP may include a storage capacitor Cstg.

3 shows an example of the structure of 7T1C in which seven transistors and one capacitor are disposed in the subpixel SP, but the type and number of circuit elements disposed in the subpixel SP and the circuit of the subpixel SP The structure may vary.

The first transistor T1 may be controlled by the scan signal Scan[n] and may be electrically connected between the second node N2 and the third node N3 . The second node N2 may be a gate node of the driving transistor DRT. The third node N3 may be a drain node or a source node of the driving transistor DRT.

The second transistor T2 is controlled by the scan signal Scan[n] and may be electrically connected between the first node N1 and the data line DL to which the data voltage Vdata is supplied. The first node N1 may be a source node or a drain node of the driving transistor DRT.

The third transistor T3 may be controlled by the emission control signal EM[n] and may be electrically connected between the first node N1 and a voltage line to which the first emission driving voltage VDDEL is supplied. The first light emission driving voltage VDDEL may be a high potential driving voltage.

The fourth transistor T4 may be controlled by the emission control signal EM[n] and may be electrically connected between the third node N3 and the fourth node N4 . The fourth node N4 may be a node electrically connected to the anode electrode of the light emitting device ED.

The fifth transistor T5 is controlled by the scan signal Scan[n-1] and may be electrically connected between the second node N2 and a voltage line to which the first initialization voltage Vint1 is supplied.

The sixth transistor T6 is controlled by the scan signal Scan[n] and may be electrically connected between the fourth node N4 and a voltage line to which the second initialization voltage Vint2 is supplied. The level of the second initialization voltage Vint2 may be different from the level of the first initialization voltage Vint1 .

The initialization of each node is performed by setting the level of the second initialization voltage Vint2 for initialization of the fourth node N4 to be different from the level of the first initialization voltage Vint1 for initialization of the second node N2. For this purpose, it is possible to set an appropriate voltage level and to improve a color difference that occurs when the light emitting device ED is driven.

The storage capacitor Cstg may be electrically connected between the third transistor T3 electrically connected to the first node N1 and the second node N2 . The storage capacitor Cstg may maintain the data voltage Vdata for driving the driving transistor DRT for one frame.

The light emitting device ED may be electrically connected between the fourth node N4 and a voltage line to which the second light emission driving voltage VSSEL is supplied. The second light emission driving voltage VSSEL may be a low potential driving voltage.

Briefly describing the driving method of the sub-pixel SP, one frame period in which the sub-pixel SP is driven may include an initialization period, a data writing period, and a light emission period.

In the initialization period, the turn-on level scan signal Scan[n-1] may be supplied to the subpixel SP. In the initialization period, the scan signal Scan[n] of the turn-off level and the emission control signal EM[n] of the turn-off level may be supplied to the sub-pixel SP.

During the initialization period, the fifth transistor T5 may be turned on, and the first initialization voltage Vint1 may be supplied to the second node N2 .

In the data writing period, the turn-on level scan signal Scan[n] may be supplied to the subpixel SP. In the data writing period, the scan signal Scan[n-1] of the turn-off level and the emission control signal EM[n] of the turn-off level may be supplied to the sub-pixel SP.

In the data writing period, the sixth transistor T6 may be turned on, and the second initialization voltage Vint2 may be supplied to the fourth node N4 .

In the data writing period, the first transistor T1 and the second transistor T2 may be turned on. Since the first transistor T1 is turned on, the second node N2 and the third node N3 may be electrically connected.

Also, since the second transistor T2 is turned on, the data voltage Vdata may be supplied to the second node N2 through the first node N1 and the third node N3 . The voltage applied to the second node N2 may be a voltage in which a voltage corresponding to the threshold voltage of the driving transistor DRT is compensated for the data voltage Vdata.

In the light emission period, the light emission control signal EM[n] of the turn-on level may be supplied to the subpixel SP. In the light emission period, the turn-off level scan signal Scan[n-1] and the turn-off scan signal Scan[n-1] may be supplied to the subpixel SP.

During the light emission period, the third transistor T3 and the fourth transistor T4 may be turned on. Since the third transistor T3 is turned on, the first light emission driving voltage VDDEL may be supplied to the first node N1 .

Since the first light emitting driving voltage VDDEL is applied to the first node N1 and the data voltage Vdata for which the threshold voltage of the driving transistor DRT is compensated is applied to the second node N2, the driving transistor (DRT) may be in a state in which it can operate. Since the fourth transistor T4 is turned on, a driving current corresponding to the data voltage Vdata may be supplied to the light emitting device ED. The light emitting device ED may exhibit luminance corresponding to the data voltage Vdata.

If the scan signals Scan[n-1], Scan[n] or the emission control signal EM[n] supplied to the sub-pixel SP are not normally supplied, the The light emitting device ED may not exhibit luminance corresponding to the data voltage Vdata.

For example, when the scan signal Scan[n] is not normally supplied, the first transistor T1 that controls the application of the data voltage Vdata to the second node N2 is not normally turned on. may not be In this case, the level of the voltage applied to the second node N2 may decrease. Since the voltage applied to the second node N2 is reduced, the voltage level difference between the first node N1 and the second node N2 may not correspond to the data voltage Vdata. Accordingly, the data voltage Vdata may not be sufficiently charged in the subpixel SP, and an image abnormality may occur in the region where the subpixel SP driven by the gate line GL to which the scan signal is not normally supplied. can occur

Embodiments of the present invention provide a structure and a driving method of a gate circuit capable of stably outputting a signal supplied to the gate line GL. In addition, although the gate circuit to be described later describes an example of a gate circuit that outputs a scan signal, embodiments of the present invention may also be applied to a gate circuit that outputs a light emission control signal.

4 is a diagram illustrating an example of a structure of a gate circuit according to embodiments of the present invention.

Referring to FIG. 4 , a plurality of transistors and at least one capacitor may be included to output a scan signal.

The gate circuit illustrated in FIG. 4 exemplifies a case in which a plurality of transistors included in the gate circuit are P-type, but in some cases, at least some of the plurality of transistors included in the gate circuit may be N-type. Also, at least one of the plurality of transistors included in the gate circuit may be disposed as a dual transistor.

The gate circuit shown in FIG. 4 is driven by two types of gate clock signals GCLK1 and GCLK2 as an example, but in some cases, the gate clock signal driving the gate circuit is 4 or 8. can be varied.

As an example, the gate circuit may include a pull-up transistor Tup that controls an output of a turn-on level scan signal. The gate circuit may include a pull-down transistor Tdn that controls an output of a scan signal of a turn-off level.

The pull-up transistor Tup may be controlled by the voltage level of the Q node. The pull-up transistor Tup may be electrically connected between an input terminal of the first gate clock signal GCLK1 and an output terminal of the scan signal. A Q node capacitor CQ may be electrically connected between the Q node and the output terminal of the scan signal.

The pull-down transistor Tdn may be controlled by the voltage level of the QB node. The pull-down transistor Tdn may be electrically connected between an input terminal of the first gate driving voltage VGH and an output terminal of the scan signal. A QB node capacitor CQB may be electrically connected between the QB node and the input terminal of the first gate driving voltage VGH.

The gate circuit may include a plurality of transistors Tsw1, Tsw11, Tsw12, Tsw2, Tsw3, Tsw4, Tsw5, and Tdmy for controlling the voltage level of the Q node and the voltage level of the QB node.

The first switching transistor Tsw1 may be controlled by the voltage level of the Q1 node. The first switching transistor Tsw1 may be electrically connected between the input terminal of the second gate clock signal GCLK2 and the QB node. The second gate clock signal GCLK2 may be a signal having a phase different from that of the first gate clock signal GCLK1 .

The first switching transistor Tsw1 may control the voltage level of the QB node.

The second switching transistor Tsw2 may be controlled by the second gate clock signal GCLK2 . The second switching transistor Tsw2 may be electrically connected between the input terminal of the gate start signal GVST and the Q1 node.

The second switching transistor Tsw2 may control the voltage level of the Q1 node.

The third switching transistor Tsw3 may be controlled by the first gate clock signal GCLK1 . The third switching transistor Tsw3 may be electrically connected between the Q1 node and the fourth switching transistor Tsw4.

The fourth switching transistor Tsw4 may be controlled by the voltage level of the QB node. The fourth switching transistor Tsw4 may be electrically connected between the input terminal of the first gate driving voltage VGH and the node Q1 .

The fifth switching transistor Tsw5 may be controlled by the second gate clock signal GCLK2 . The fifth switching transistor Tsw5 may be electrically connected between the input terminal of the second gate driving voltage VGL and the node QB.

The dummy transistor Tdmy may be controlled by the second gate driving voltage VGL. The dummy transistor Tdmy may be electrically connected between the Q node and the Q1 node.

Since the dummy transistor Tdmy is controlled by the second gate driving voltage VGL, a turn-on state may be maintained while the gate circuit is driven.

Since the dummy transistor Tdmy is located between the Q node and the Q1 node, even if the voltage level of the Q node coupled to the output terminal of the scan signal by the Q node capacitor CQ varies when the scan signal is output, the voltage level of the Q1 node is It may not fluctuate or the voltage level of the Q1 node may have a small fluctuation range.

By reducing the fluctuation of the voltage level of the Q1 node, deterioration of the first switching transistor Tsw1 controlled by the Q1 node may be reduced. By reducing the deterioration of the first switching transistor Tsw1, the QB node can be stably controlled.

In addition, by disposing the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 in the gate circuit, the QB node can be controlled more stably.

The first sub-switching transistor Tsw11 may be controlled by the voltage level of the Q1 node. The first sub-switching transistor Tsw11 may be electrically connected between the QB node and the second sub-switching transistor Tsw12.

The second sub-switching transistor Tsw12 may be controlled by the first gate clock signal GCLK1 . The second sub-switching transistor Tsw12 may be electrically connected between the input terminal of the first gate driving voltage VGH and the first sub-switching transistor Tsw11.

The first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 are electrically connected between the input terminal of the first gate driving voltage VGH and the QB node, thereby controlling the voltage level of the QB node. .

The first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 may be simultaneously turned on during a portion of the period in which the first switching transistor Tsw1 is turned on. The first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 may control the supply of the first gate driving voltage VGH to the QB node.

Due to the arrangement of the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12, the voltage level of the QB node may be stably controlled and the reliability of the gate circuit may be improved.

5 to 8 are diagrams illustrating examples of a driving method of the gate circuit illustrated in FIG. 4 .

Referring to FIG. 5 , a low-level gate start signal GVST may be supplied to the gate circuit in the first period P1 .

In the first period P1 , the high level first gate clock signal GCLK1 may be supplied to the gate circuit. In the first period P1 , the low-level second gate clock signal GCLK2 may be supplied to the gate circuit.

Since the low-level second gate clock signal GCLK2 is supplied to the gate circuit, the second switching transistor Tsw2 and the fifth switching transistor Tsw5 may be turned on. The source node of the first switching transistor Tsw1 may be in the second low level state LOW2 .

Since the second switching transistor Tsw2 is turned on, the low-level gate start signal GVST may be supplied to the Q1 node.

Since the low-level gate start signal GVST is supplied to the Q1 node, the first switching transistor Tsw1 may be turned on.

The gate node of the first switching transistor Tsw1 may be in the first low level state LOW1 . The first low-level state LOW1, for example, is a level at which the first switching transistor Tsw1 can be turned on, and may mean a voltage level state higher than the voltage level of the second low-level state LOW2. have.

Also, since the dummy transistor Tdmy is turned on, the Q node may be in the first low level state LOW1 like the Q1 node.

Since the Q node is in the first low level state LOW1 , the pull-up transistor Tup may be turned on.

Since the fifth switching transistor Tsw5 is turned on, the second gate driving voltage VGL may be supplied to the QB node. Also, since the first switching transistor Tsw1 is turned on, the low-level second gate clock signal GCLK2 may be supplied to the QB node.

The QB node may be in the first low level state LOW1. Since the QB node is in the first low level state LOW1 , the pull-down transistor Tdn may be turned on.

The fourth switching transistor Tsw4 is turned on by the QB node, but the third switching transistor Tsw3 is turned off by the first gate clock signal GCLK1, so the first gate driving voltage ( VGH) may not be supplied to the Q1 node.

Since the pull-up transistor Tup is in the turned-on state, the high-level first gate clock signal GCLK1 may be output through the output terminal of the scan signal. Since the pull-down transistor Tdn is in the turned-on state, the high level first gate driving voltage VGH may be output through the output terminal of the scan signal.

The first period P1 may be viewed as a period in which both the Q node and the QB node are at the turn-on level and output a scan signal of the turn-off level.

Since the Q1 node is in the first low-level state LOW1 in the first period P1 , the first sub-switching transistor Tsw11 may be in a turned-on state.

Since the first gate clock signal GCLK1 is at a high level in the first period P1 , the gate node of the second sub-switching transistor Tsw12 may be in a high level state (HIGH). In the first period P1 , the second sub-switching transistor Tsw12 may be in a turned-off state.

Accordingly, in the first period P1 , the first sub-switching transistor Tsw11 and the second switching transistor Tsw12 may not affect the voltage level of the QB node.

In the second period P2 in which the turn-on level scan signal is output, the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 may affect the voltage level of the QB node.

Referring to FIG. 6 , a high-level gate start signal GVST may be supplied to the gate circuit in the second period P2 .

In the second period P2 , the low-level first gate clock signal GCLK1 may be supplied to the gate circuit. In the second period P2 , the high-level second gate clock signal GCLK2 may be supplied to the gate circuit.

Since the high-level second gate clock signal GCLK2 is supplied to the gate circuit, the second switching transistor Tsw2 and the fifth switching transistor Tsw5 may be turned off. The source node of the first switching transistor Tsw1 may be in the high level state HIGH.

Since the second switching transistor Tsw2 is turned off, the high-level gate start signal GVST may not be supplied to the Q1 node. The Q1 node may maintain the first low level state LOW1.

Since the Q1 node maintains the first low level state LOW1 , the first switching transistor Tsw1 may maintain the turn-on state. Also, the pull-up transistor Tup may maintain a turned-on state.

Since the first switching transistor Tsw1 is in the turned-on state, the high-level second gate clock signal GCLK2 may be supplied to the QB node.

The QB node may be in a high level state (HIGH). Since the QB node is in the high level state HIGH, the pull-down transistor Tdn may be turned off.

Since the pull-up transistor Tup is in a turned-on state and the pull-down transistor Tdn is in a turned-off state, the low-level first gate clock signal GCLK1 may be output through an output terminal of the scan signal. Accordingly, the gate circuit may output a scan signal of a turn-on level.

Since the low-level first gate clock signal GCLK1 is output through the output terminal of the scan signal, the voltage level of the Q node coupled by the output terminal of the scan signal and the Q node capacitor CQ may be reduced. The Q node may be in the third low level state LOW3. The third low level state LOW3 may mean, for example, a voltage level lower than the voltage level of the second low level state LOW2 .

Even when the Q node is in the third low level state LOW3 , since the dummy transistor Tdmy is disposed between the Q node and the Q1 node, the Q1 node may maintain the first low level state LOW1 .

Also, since the node Q1 is in the first low-level state LOW1 in the second period P2 , the first sub-switching transistor Tsw11 may be in the turn-on state. Since the low-level first gate clock signal GCLK1 is supplied to the gate circuit in the second period P2 , the second sub-switching transistor Tsw12 may also be turned on.

Since the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 are simultaneously turned on, the high-level first gate driving voltage VGH may be supplied to the QB node.

Accordingly, in some cases, even if the first switching transistor Tsw1 does not operate normally, the level of the QB node may be controlled by the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12.

Also, since the level of the QB node is stably controlled, the fourth switching transistor Tsw4 may be turned off in the second period P2 .

Even when the third switching transistor Tsw3 is turned on by the first gate clock signal GCLK1 , since the fourth switching transistor Tsw4 is turned off, the first gate driving voltage VGH is applied to the Q1 node may not be supplied.

After the gate circuit outputs the scan signal of the turn-on level, the output of the scan signal of the turn-off level may be maintained. Accordingly, the Q node may maintain a high level, and the QB node may maintain a low level.

Referring to FIG. 7 , in the third period P3 , the gate start signal GVST may maintain a high level.

In the third period P3 , the first gate clock signal GCLK1 may have a high level, and the second gate clock signal GCLK2 may have a low level.

Since the low-level second gate clock signal GCLK2 is supplied to the gate circuit, the second switching transistor Tsw2 and the fifth switching transistor Tsw5 may be turned on.

Since the second switching transistor Tsw2 is turned on, the high-level gate start signal GVST may be supplied to the Q1 node.

The Q1 node and the Q node may be in a high level state (HIGH). The first switching transistor Tsw1 and the pull-up transistor Tup may be in a turn-off state.

Since the fifth switching transistor Tsw5 is turned on, the second gate driving voltage VGL may be supplied to the QB node.

The QB node may be in the first low level state LOW1. The pull-down transistor Tdn may be in a turn-on state.

Since the pull-down transistor Tdn is turned on, the first gate driving voltage VGH may be output through the output terminal of the scan signal.

Referring to FIG. 8 , the gate start signal GVST may maintain a high level in the fourth period P4 .

In the fourth period P4 , the first gate clock signal GCLK1 may have a low level, and the second gate clock signal GCLK2 may have a high level.

Since the high level second gate clock signal GCLK2 is supplied to the gate circuit, the second switching transistor Tsw2 and the fifth switching transistor Tsw5 may be turned off.

Since the Q1 node maintains the high level state HIGH, the first switching transistor Tsw1 may maintain the turn-off state. Also, since the Q node maintains the high level state HIGH, the pull-up transistor Tup may maintain the turn-off state.

Since the first switching transistor Tsw1 maintains the turn-off state, the QB node may maintain the first low level state LOW1 .

The second sub-switching transistor Tsw12 may be turned on by the low-level first gate clock signal GCLK1. However, since the first sub-switching transistor Tsw11 is turned off by the Q1 node, the first gate driving voltage VGH may not be supplied to the QB node.

Since the QB node maintains the first low level state LOW1 , the pull-down transistor Tdn may maintain the turn-on state.

Since the pull-down transistor Tdn maintains the turned-on state, the first gate driving voltage VGH may be output through the output terminal of the scan signal.

After the fourth period P4, the high-level gate start signal GVST may be maintained until the low-level gate start signal GVST is input to the gate circuit. Also, since the level of the first gate clock signal GCLK1 and the level of the second gate clock signal GCLK2 are repeatedly changed, the driving state of the third period P3 and the driving state of the fourth period P4 are repeated. can be

For example, the driving state of the gate circuit in the fifth period P5 may be the same as the driving state of the gate circuit in the third period P3 . The driving state of the gate circuit in the sixth period P6 may be the same as the driving state of the gate circuit in the fourth period P4 .

As described above, by disposing the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 in the gate circuit, the control of the QB node can be stably performed.

Accordingly, in the second period P2 , the gate circuit may stably output a scan signal having a turn-on level. It is possible to prevent abnormal driving of the sub-pixel SP due to an abnormality in the scan signal output from the gate circuit.

The gate circuit may repeat the driving state of the third period P3 and the fourth period P4 for a long period of time after outputting the scan signal of the turn-on level and before outputting the scan signal of the next turn-on level. . In addition, stress may be applied to the first switching transistor Tsw1 controlling the QB node due to the repetition of the driving state of the third period P3 and the fourth period P4 .

9 is a diagram illustrating an example of stress applied to a circuit element in the gate circuit when the gate circuit shown in FIG. 4 is driven.

Referring to FIG. 9 , in the first period P1 , the low-level second gate clock signal GCLK2 is supplied to the gate circuit, and both the Q1 node and the QB node are low-level, so that the first switching transistor Tsw1 The gate node, the source node, and the drain node may all be at a low level.

In the second period P2 , the node Q1 is at the low level and the second gate clock signal GCLK2 of the high level is supplied to the gate circuit, so the gate node of the first switching transistor Tsw1 maintains the low level, and the first A source node and a drain node of the switching transistor Tsw1 may be at a high level.

Since the gate node of the first switching transistor Tsw1 has a low level and a source node of the first switching transistor Tsw1 has a high level, the first switching transistor Tsw1 may be in a state of receiving Negative Bias Temperature Stress (NBTS).

After the third period P3 , the Q1 node maintains a high level, so the gate node of the first switching transistor Tsw1 may have a high level. After the third period P3 , the QB node maintains the low level, so the drain node of the first switching transistor Tsw1 may be at the low level.

Since the second gate clock signal GCLK2 of the low level is supplied to the gate circuit in the third period P3, the source node of the first switching transistor Tsw1 may be at the low level.

Since the gate node of the first switching transistor Tsw1 has a high level and a source node of the first switching transistor Tsw1 has a low level, the first switching transistor Tsw1 may be in a state of receiving a positive bias temperature stress (PBTS).

Since the second gate clock signal GCLK2 having a high level is supplied to the gate circuit in the fourth period P4 , the source node of the first switching transistor Tsw1 may have a high level.

Since the gate node of the first switching transistor Tsw1 is at a high level and the source node is at a high level, the first switching transistor Tsw1 may be in a state of receiving high junction stress (HJS).

In the fifth period P5 and the sixth period P6 , the first switching transistor Tsw1 may repeatedly receive the stress received in the third period P3 and the fourth period P4 . Since the level of the source node of the first switching transistor Tsw1 repeats a low level and a high level, the threshold voltage of the first switching transistor Tsw1 may be changed by AC stress.

Embodiments of the present invention provide a method for stably outputting a scan signal of a turn-on level through stable control of the QB node, as well as controlling the QB node during a period in which the gate circuit outputs a scan signal of a turn-off level. 1 A method for reducing the stress applied to the switching transistor Tsw1 is provided.

10 to 12 are diagrams illustrating another example of a structure of a gate circuit according to embodiments of the present invention. 10 to 12 exemplarily show a structure in which reliability of the first switching transistor Tsw1 is improved in a structure in which the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 are disposed in the gate circuit.

The gate circuit according to embodiments of the present invention, which will be described later, has a structure in which reliability of the first switching transistor Tsw1 is improved in a state in which the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 are not disposed. may include

Referring to FIG. 10 , the gate circuit may include, for example, a plurality of first switching transistors Tsw1a and Tsw1b.

The plurality of first switching transistors Tsw1a and Tsw1b may be controlled by the voltage level of the Q1 node. The plurality of first switching transistors Tsw1a and Tsw1b may be connected in parallel between the input terminal of the second gate clock signal GCLK2 and the QB node.

By arranging the plurality of first switching transistors Tsw1a and Tsw1b in parallel, it is possible to secure a margin for reliability of the first switching transistor Tsw1 subjected to stress while the gate circuit outputs a turn-off level scan signal. can

When the transistors in the gate circuit are dually arranged, the reliability of the first switching transistor Tsw1 can be improved by arranging them in a parallel-connected structure instead of in a series-connected structure like the second switching transistor Tsw2. have.

In addition, according to the embodiments of the present invention, the voltage level of the source node of the first switching transistor Tsw1 is constantly maintained during the period in which the gate circuit outputs the scan signal of the turn-off level, so that AC stress is reduced by the first switching transistor Tsw1. (Tsw1) can be prevented from being applied.

Referring to FIG. 11 , the gate circuit may further include a degradation delay transistor Tdly.

The degradation delay transistor Tdly may be electrically connected between an input terminal of the second gate clock signal GCLK2 and a source node of the first switching transistor Tsw1 . A gate node of the degradation delay transistor Tdly may be electrically connected to a source node of the first switching transistor Tsw1 .

The degradation delay transistor Tdly may be electrically connected to a source node of the first switching transistor Tsw1 in a diode connection structure.

In the deterioration delay transistor Tdly, a second gate clock signal GCLK2 repeating a low level and a high level is applied to the source node of the first switching transistor Tsw1 during a period in which a turn-off level scan signal is output. can block it

Accordingly, the source node of the first switching transistor Tsw1 may maintain a high level during a period in which the turn-off level scan signal is output.

Since the source node of the first switching transistor Tsw1 maintains a constant voltage level, it is possible to prevent AC stress from being applied to the first switching transistor Tsw1.

The reliability and lifespan of the first switching transistor Tsw1 is prevented by preventing AC stress applied to the first switching transistor Tsw1 during the period in which the scan signal of the turn-off level is output, which occupies most of the driving period of the gate circuit. can be improved

Alternatively, embodiments of the present invention may provide a structure capable of preventing AC stress from being applied to the first switching transistor Tsw1 without adding a separate transistor to the gate circuit.

Referring to FIG. 12 , the first switching transistor Tsw1 may be electrically connected between the input terminal of the gate start signal GVST and the QB node.

In the first period P1 and the second period P2 , the first switching transistor Tsw1 may maintain a turned-on state.

Since the low-level gate start signal GVST is supplied to the gate circuit in the first period P1, the QB node may have a low level. Since the high level gate start signal GVST is supplied to the gate circuit in the second period P2, the QB node may have a high level.

In a structure in which the source node of the first switching transistor Tsw1 is electrically connected to the input terminal of the gate start signal GVST, the control of the QB node may be normally performed.

The high level gate start signal GVST may be maintained from the third period P3 .

Accordingly, the source node of the first switching transistor Tsw1 may maintain a high level during a period in which the scan signal of the turn-off level is output after the gate circuit outputs the scan signal of the turn-on level.

Since the source node of the first switching transistor Tsw1 maintains a high level, it is possible to prevent AC stress from being applied to the first switching transistor Tsw1.

As described above, the reliability of the gate circuit may be improved by preventing AC stress applied to the first switching transistor Tsw1 without adding a separate circuit element.

According to the above-described embodiments of the present invention, the first sub-switching transistor Tsw11 and the second sub-switching transistor Tsw12 electrically connected to the QB node are disposed in the gate circuit, so that the QB node control can be performed more stably.

Also, after the gate circuit outputs a scan signal of a turn-on level, the voltage level of the source node of the first switching transistor Tsw1 is prevented from being repeated to a low level and a high level, so that the gate circuit is turned off at the turn-off level It is possible to prevent AC stress from being applied to the first switching transistor Tsw1 during the period in which the scan signal of .

Accordingly, by reducing or delaying the deterioration of the first switching transistor Tsw1 and stably controlling the QB node, the reliability and lifespan of the gate circuit can be improved, and an image abnormality caused by abnormal driving of the gate circuit can be prevented.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. In addition, since the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device 110: display panel
120: gate driving circuit 130: data driving circuit
140: controller

Claims (20)

a plurality of sub-pixels disposed on the display panel;
a plurality of gate lines disposed on the display panel and electrically connected to at least one subpixel of the plurality of subpixels; and
a plurality of gate circuits for driving the plurality of gate lines;
Each of the plurality of gate circuits,
a pull-up transistor controlled by the Q node and electrically connected between an input terminal of the first gate clock signal and an output terminal of the scan signal;
a pull-down transistor controlled by the QB node and electrically connected between an input terminal of a first gate driving voltage and an output terminal of the scan signal; and
and at least one first switching transistor controlled by a Q1 node electrically connected to the Q node and electrically connected between an input terminal of a gate start signal and the QB node.
According to claim 1,
After the scan signal of a turn-on level is output through the output terminal of the scan signal, before the gate start signal of the level for turning on the at least one first switching transistor is inputted, the input terminal of the gate start signal and the at least A display device in which a voltage level of a node between one first switching transistor is maintained constant.
According to claim 1,
Each of the plurality of gate circuits,
a first sub-switching transistor controlled by the Q1 node and electrically connected to the QB node; and
and a second sub-switching transistor controlled by the first gate clock signal and electrically connected between an input terminal of the first gate driving voltage and the first sub-switching transistor.
4. The method of claim 3,
A period in which the first sub-switching transistor and the second sub-switching transistor are simultaneously turned on is a part of a period in which the at least one first switching transistor is turned on.
According to claim 1,
Each of the plurality of gate circuits,
The display further comprising at least one second switching transistor controlled by a second gate clock signal having a phase different from that of the first gate clock signal and electrically connected between the input terminal of the gate start signal and the Q1 node Device.
6. The method of claim 5,
Each of the plurality of gate circuits,
a third switching transistor controlled by the first gate clock signal and electrically connected to the Q1 node; and
and a fourth switching transistor controlled by the QB node and electrically connected between the input terminal of the first gate driving voltage and the third switching transistor.
7. The method of claim 6,
In a first period in which the at least one first switching transistor and the at least one second switching transistor are simultaneously turned on, the third switching transistor is turned off and the fourth switching transistor is turned on become a state,
After the first period, in a second period in which the at least one first switching transistor maintains a turn-on state and the at least one second switching transistor becomes a turn-off state, the third switching transistor is turned on state and the fourth switching transistor is turned off.
8. The method of claim 7,
In a period other than the first period and the second period, voltage levels across the at least one first switching transistor are different from each other.
6. The method of claim 5,
The at least one first switching transistor is electrically isolated from an input terminal of the second gate clock signal.
6. The method of claim 5,
The at least one first switching transistor includes two or more transistors connected in parallel, and the at least one second switching transistor includes two or more transistors connected in series.
According to claim 1,
Each of the plurality of gate circuits,
a dummy transistor controlled by a second gate driving voltage different from the first gate driving voltage and electrically connected between the Q node and the Q1 node;
The dummy transistor maintains a turned-on state during a period in which the gate circuit is driven.
a plurality of sub-pixels disposed on the display panel;
a plurality of gate lines disposed on the display panel and electrically connected to at least one subpixel of the plurality of subpixels; and
a plurality of gate circuits for driving the plurality of gate lines;
Each of the plurality of gate circuits,
a pull-up transistor controlled by the Q node and electrically connected between an input terminal of the first gate clock signal and an output terminal of the scan signal;
a pull-down transistor controlled by the QB node and electrically connected between an input terminal of a first gate driving voltage and an output terminal of the scan signal;
at least one first switching transistor controlled by a Q1 node electrically connected to the Q node and electrically connected between an input terminal of a second gate clock signal and the QB node; and
and a degradation delay transistor electrically connected between the input terminal of the second gate clock signal and the at least one first switching transistor, and a gate node electrically connected to the at least one first switching transistor.
13. The method of claim 12,
After the turn-on level scan signal is output through the output terminal of the scan signal, the deterioration delay transistor and the at least one first switching transistor are output before the gate start signal of the level for turning on the at least one first switching transistor is input 1 A display device in which the voltage level at the node between the switching transistors is kept constant.
13. The method of claim 12,
Each of the plurality of gate circuits,
a first sub-switching transistor controlled by the Q1 node and electrically connected to the QB node; and
and a second sub-switching transistor controlled by the first gate clock signal and electrically connected between an input terminal of the first gate driving voltage and the first sub-switching transistor.
15. The method of claim 14,
A display device configured to output a turn-on level scan signal through an output terminal of the scan signal during a period in which the first sub-switching transistor and the second sub-switching transistor are simultaneously turned on.
a pull-up transistor controlled by the Q node and electrically connected between an input terminal of the first gate clock signal and an output terminal of the scan signal;
a pull-down transistor controlled by the QB node and electrically connected between an input terminal of a first gate driving voltage and an output terminal of the scan signal;
at least one first switching transistor controlled by a Q1 node electrically connected to the Q node and configured to control a voltage level of the QB node;
a first sub-switching transistor controlled by the Q1 node and electrically connected to the QB node; and
a second sub-switching transistor controlled by the first gate clock signal and electrically connected between the input terminal of the first gate driving voltage and the first sub-switching transistor
A gate circuit comprising a.
17. The method of claim 16,
A period in which the first sub-switching transistor and the second sub-switching transistor are simultaneously turned on is a part of a period in which the at least one first switching transistor is in a turned-on state.
17. The method of claim 16,
and the at least one first switching transistor is electrically connected between an input terminal of a gate start signal and the QB node.
17. The method of claim 16,
the at least one first switching transistor is electrically connected between an input terminal of a second gate clock signal and the QB node;
and a degradation delay transistor electrically connected between the input terminal of the second gate clock signal and the at least one first switching transistor, and a gate node electrically connected to the at least one first switching transistor.
20. The method of claim 18 or 19,
A source of the at least one first switching transistor after a turn-on level scan signal is output through the output terminal of the scan signal and before a gate start signal of a level for turning on the at least one first switching transistor is input A gate circuit in which the voltage level at the node is kept constant.

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