KR20220052684A - Three dimensional flash memory for improving program and operation method thereof - Google Patents

Abstract

Disclosed are a three-dimensional flash memory for improving a program operation and an operation method thereof. According to an embodiment of the present invention, the three-dimensional flash memory comprises: a plurality of word lines horizontally extended and formed on a substrate and successively laminated; and a plurality of strings penetrating the plurality of word lines and extended in one direction and formed on the substrate. Each of the plurality of strings includes: a channel layer extended in the one direction; and an electric charge storage layer extended in the one direction to surround the channel layer. The channel layer and the electric charge storage layer configure a plurality of memory cells corresponding to the plurality of word lines. The channel layer includes: a back gate extended in one direction with at least a part surrounded by the channel layer; and an insulation film formed between the back gate and the channel layer and extended in the one direction. When the program operates, a ground selection line (GSL) placed on a lower end of the plurality of word lines is floated.

Description

THREE DIMENSIONAL FLASH MEMORY FOR IMPROVING PROGRAM AND OPERATION METHOD THEREOF

The following embodiments relate to a three-dimensional flash memory, and more particularly, a description of a three-dimensional flash memory for improving a program operation and an operation method thereof.

A flash memory element is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory of which can be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line LSL.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking insulating layers 242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. For example, in a plan view, the vertical structures 230 may be arranged in a matrix form along the first and second directions. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in a hollow tube shape therein, and in this case, a buried film 228 filling the inside of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating layers 242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the 3D flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and others may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking insulating layers 242 and 243 are the horizontal structures 250 . can be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

The conventional three-dimensional flash memory having such a structure has a problem in that cell characteristics and reliability are deteriorated due to an increase in the number of vertical memory cells.

Accordingly, the following embodiments intend to propose a technique for improving cell characteristics and reliability.

In order to improve cell characteristics and reliability, one embodiment proposes a three-dimensional flash memory having a structure in which a back gate is extended inside a channel layer.

In this case, one embodiment proposes a method of operating a 3D flash memory to improve problems that may occur in a program operation.

In more detail, embodiments relate to a problem in which boosting efficiency is reduced in an unselected string that does not include a target memory cell that is a target of a program operation, and a fringing field generated in the target memory cell is a target memory cell. We propose an operating method of a 3D flash memory that solves the problem of affecting adjacent memory cells adjacent to the upper and lower parts of

According to an embodiment, a 3D flash memory for improving a program operation includes: a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. and a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer, wherein the three-dimensional flash memory includes: It is characterized in that the GSL (Ground Selection Line) disposed at the lower end of the lines is floated.

According to one aspect, the 3D flash memory is configured to improve boosting efficiency in an unselected string except for a selected string including a target memory cell to be subjected to the program operation among the plurality of strings; The GSL may be floated during the program operation.

According to another aspect, the 3D flash memory may float a common source line (CSL) together with the GSL during the program operation.

According to another aspect, the 3D flash memory may be characterized in that the GSL is floated during a read operation.

According to an embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. A method of operating a 3D flash memory program comprising: a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer; Floating a Ground Selection Line (GSL) disposed at the bottom; applying a program voltage to a target word line corresponding to a target memory cell that is a target of a program operation, and floating word lines other than the target word line among the plurality of word lines; and performing a program operation on the target memory cell by applying a voltage for the program operation to the back gate.

According to an aspect, the floating of the GSL may include floating the GSL in order to improve boosting efficiency in an unselected string except for the selected string including the target memory cell. .

According to another aspect, the floating of the GSL may include floating a Common Source Line (CSL) together with the GSL.

According to an embodiment, a 3D flash memory for improving a program operation includes: a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. and a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer, wherein the three-dimensional flash memory is configured to: A program voltage is applied to a target word line corresponding to a target memory cell as a target, and a pass voltage is applied to adjacent word lines adjacent to upper and lower portions of the target word line.

According to an aspect, in the 3D flash memory, in order to prevent a fringing field generated in the target memory cell from affecting adjacent memory cells adjacent to upper and lower portions of the target memory cell, the program The pass voltage may be applied to the adjacent word lines during operation.

According to another aspect, the 3D flash memory may float word lines other than the target word line and the adjacent word lines among the plurality of word lines.

According to an embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. A three-dimensional flash memory program operation method comprising: a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer; applying a program voltage to a target word line corresponding to a target memory cell; applying a pass voltage to adjacent word lines adjacent to upper and lower portions of the target word line; floating word lines other than the target word line and the adjacent word lines among the plurality of word lines; and performing a program operation on the target memory cell by applying a voltage for the program operation to the back gate.

According to an aspect, the applying the pass voltage to the adjacent word lines may include causing a fringing field generated in the target memory cell to affect adjacent memory cells adjacent to upper and lower portions of the target memory cell. In order to prevent this, a pass voltage may be applied to the adjacent word lines.

In order to improve cell characteristics and reliability, one embodiment may propose a three-dimensional flash memory having a structure in which a back gate is extended inside a channel layer.

In this case, embodiments may propose a method of operating a 3D flash memory that improves problems that may occur in a program operation.

In more detail, embodiments relate to a problem in which boosting efficiency is reduced in an unselected string that does not include a target memory cell that is a target of a program operation, and a fringing field generated in the target memory cell is a target memory cell. It is possible to propose a method of operating a 3D flash memory that solves the problem of affecting adjacent memory cells adjacent to the upper and lower portions of .

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.
2 is a perspective view showing the structure of a conventional three-dimensional flash memory.
3A is a YZ cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment.
FIG. 3B is an XY plan view illustrating a cross-section taken along line A-A' of the three-dimensional flash memory shown in FIG. 3A.
4 is a flowchart illustrating a program operation method for improving boosting efficiency in an unselected string according to an exemplary embodiment.
FIG. 5 is a YZ cross-sectional view of a 3D flash memory for explaining a program operation method for improving boosting efficiency in the non-selected string shown in FIG. 4 .
6 is a flowchart illustrating a program operation method for preventing a fringing field of a target memory cell from affecting adjacent memory cells according to an exemplary embodiment.
7 is a YX cross-sectional view of a 3D flash memory for explaining a program operation method for preventing the fringing field of the target memory cell shown in FIG. 6 from affecting adjacent memory cells.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

3A is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment, and FIG. 3B is an X-Y plan view illustrating a cross-section A-A′ of the three-dimensional flash memory shown in FIG. 3A.

3A to 3B , the 3D flash memory 300 according to an embodiment includes a plurality of word lines 310 and a plurality of strings 320 and 330 .

The plurality of word lines 310 are sequentially stacked while extending in the horizontal direction (eg, Y direction) on the substrate 305 , respectively, W (tungsten), Ti (titanium), Ta (tantalum), Cu ( Copper), Mo (molybdenum), Ru (ruthenium), or Au (gold) is formed of a conductive material (all metal materials capable of forming ALDs are included in addition to the described metal materials), and a voltage is applied to the corresponding memory cells. Memory operations (such as a read operation, a program operation, and an erase operation) may be performed. A plurality of insulating layers 311 formed of an insulating material may be interposed between the plurality of word lines 310 .

Here, a String Selection Line (SSL) may be disposed at an upper end of the plurality of word lines 310 , and a Ground Selection Line (GSL) 312 may be disposed at a lower end of the plurality of word lines 310 . A common source line (CSL) 313 may be formed in a lower region of the GSL 312 on the substrate 305 .

The plurality of strings 320 and 330 pass through the plurality of word lines 310 to extend in one direction (eg, the Z direction) on the substrate 305 , and each of the channel layers 321 and 331 and It may include charge storage layers 322 and 332 .

The charge storage layers 322 and 332 are formed to extend to surround the channel layers 321 and 331 , and trap charges or holes due to voltages applied through the plurality of word lines 310 , or the states of charges (eg, For example, as a component for maintaining the polarization state of electric charges), the three-dimensional flash is divided into regions corresponding to the plurality of word lines 310 and constitutes a plurality of memory cells together with the channel layers 321 and 331 . The memory 300 may serve as a data store. For example, an oxide-nitride-oxide (ONO) layer or a ferroelectric layer may be used as the charge storage layers 322 and 332 .

The channel layers 321 and 331 are a component that transfers charges or holes to the charge storage layers 322 and 332 by a voltage applied through the plurality of word lines 310, SSL, GSL 312, and bit lines. As such, it may be formed of di-crystalline silicon or polysilicon. In addition, the channel layers 321 and 331 may serve to transfer charges or holes to the charge storage layers 322 and 332 by a voltage applied through the back gates 323 and 333 to be described later. A detailed description thereof will be provided below.

The channel layers 321 and 331 have back gates 323 and 333 and back gates 323 and 333 extending in one direction (eg, the Z direction) while being at least partially surrounded by the channel layers 321 and 331 . and insulating layers 324 and 334 extending in one direction between the channel layers 321 and 331 . Hereinafter, that the back gates 323 and 333 are at least partially covered by the channel layers 321 and 331 means that the back gates 323 and 333 are included in at least a portion of the channel layers 321 and 331 . or penetrating the channel layers 321 and 331 .

Here, the channel layers 321 and 331 may have a structure to prevent leakage current from the GSL 312 . For example, a region corresponding to the GSL 312 disposed below the plurality of word lines 310 among the channel layers 321 and 331 corresponds to the GSL 312 among the channel layers 321 and 331 . The region may have a structure in which B (boron) is further added to increase the threshold voltage of the corresponding region.

The back gates 323 and 333 may include W (tungsten), Ti (titanium), Ta (tantalum), Cu (copper), Mo (molybdenum), and Ru (ruthenium) to enable voltage application to the channel layers 321 and 331 . ) or a conductive material such as Au (gold) (all metal materials capable of forming an ALD are included in addition to the described metal materials), or may be formed of doped polysilicon, and a plurality of word lines are formed in the channel layers 321 and 331 . It may be formed to extend over an inner region corresponding to 310 (a region from the GSL 312 to the plurality of word lines 310 ). However, the present invention is not limited thereto, and the channel layers 321 and 331 may be formed to extend from the GSL 312 to the SSL in the corresponding inner region.

In addition, the back gates 323 and 333 pass through the substrate 305 on which the plurality of strings 320 and 330 are extended, and are substrates for the back gates 323 and 333 positioned below the substrate 305 . It may be formed extending up to 315 . That is, the 3D flash memory 300 including the back gates 323 and 333 may have a double substrate structure.

In the double-substrate structure, the lower substrate 315 may be used for heat dissipation of the plurality of strings 320 and 330 . As the heat dissipation path of the plurality of strings 320 and 330 is located on the substrate 315 that is distinct from the substrate 305 on which the plurality of strings 320 and 330 are extended, the plurality of strings 320 , 330 may be formed on the substrate 305 on which the plurality of strings 320 and 330 are extended, so that the problem that the cell transistor is affected can be solved.

However, the present invention is not limited thereto, and the 3D flash memory 300 including the back gates 323 and 333 may have a single substrate structure. In this case, the back gates 323 and 333 are internal regions corresponding to the plurality of word lines 310 in the channel layers 321 and 331 on the substrate 305 on which the plurality of strings 320 and 330 are formed to extend. In the channel layers 321 and 331 on the substrate 305 extending from the GSL 312 to the plurality of word lines 310) or formed to extend over the plurality of strings 320 and 330, the GSL ( 312) to SSL may be formed to extend over the corresponding inner region.

In addition, the 3D flash memory 300 including the back gates 323 and 333 includes a substrate 305 on which a plurality of word lines 310 are stacked and a plurality of strings 320 and 330 extend in one direction. ) may further include a back gate plate 325 disposed in a horizontal direction under the substrate 305 while penetrating the substrate 305 . While the back gate plate 325 is formed of the same material as the back gates 323 and 333 , the film stress of the plurality of word lines 310 is relieved to warp the substrate 305 . ) can play a role in preventing In this structure, the back gates 323 and 333 may be formed to extend to the back gate plate 325 .

In both the single substrate structure and the double substrate structure, a wiring 340 for a voltage applied to the back gates 323 and 333 may be formed on the upper surface of the substrate 315 connected to the back gates 323 and 333 . However, it is not limited or limited to the drawings, and the wiring 340 for the voltage applied to the back gates 323 and 333 may be formed on the lower surface of the substrate 315 connected to the back gates 323 and 333 (not shown). city), may be formed on the back gates 323 and 333 .

The back gates 323 and 333 having such a structure change states of charges of the charge storage layers 322 and 332 in the memory operation (eg, a program operation, an erase operation, and a read operation) of the 3D flash memory 300 . and for applications to which a voltage is applied to maintain (eg, trap, store, and maintenance) can be used. Accordingly, the voltage applied to the back gates 323 and 333 is applied to the voltage applied to the plurality of word lines 310 and the voltage applied to the plurality of bit lines (not shown) respectively connected to the plurality of strings 320 and 330 . The three-dimensional flash memory 300 according to an embodiment causes the memory operation of the three-dimensional flash memory 300 together with the voltages that are By further using the back gates 323 and 333 together with the , the memory operation current can be improved to increase the memory operation speed, thereby improving cell characteristics and reliability.

For example, in the back gates 323 and 333 included in each of the plurality of strings 320 and 330 during a program operation of the 3D program memory 300 , the target of the program operation among the plurality of word lines 310 . Based on the program voltage Vpgm applied to the target word line corresponding to the target memory cell and voltages applied to the plurality of bit lines respectively connected to the plurality of strings 320 and 330, only the target memory cell A voltage to be programmed (eg, a pass voltage Vpass) may be applied. A detailed description thereof will be described with reference to FIGS. 4 to 5 and 6 to 7 .

For another example, during a read operation of the 3D program memory 300 , the back gate 323 included in the selected string 320 including a target memory cell to be read from among the plurality of strings 320 . is a verification voltage Vverify applied to a target word line corresponding to a target memory cell among the plurality of word lines 310 , and is applied to at least one remaining memory cell of the plurality of word lines 310 excluding the target memory cell. Based on the read voltage Vread applied to the corresponding at least one word line and the voltage applied to the bit line connected to the selected string 320 , only the target memory cell may be floated to be read.

In the above, the back gates 323 and 333 have been described as having a structure in which the strings 320 and 330 are grouped and electrically separated in units of blocks so that different voltages are applied in units of blocks, but the present invention is not limited thereto. Reference numerals 323 and 333 may have a structure in which each string is electrically separated so that different voltages can be applied in units of strings.

The insulating layers 324 and 334 may be formed of an insulating material to prevent the back gates 323 and 333 from directly contacting the channel layers 321 and 331 , and in particular, to prevent leakage current from the GSL 312 . It may have a structure for For example, a region corresponding to the GSL 312 disposed at the lower end of the plurality of word lines 310 among the insulating layers 324 and 334 is formed to be thicker than the remaining regions in order to prevent leakage current from the GSL. can be

The three-dimensional flash memory 300 may perform a characteristic operation method for improving problems occurring in a program operation based on the structure to which the above-described back gates 323 and 333 are applied.

For example, the three-dimensional flash memory 300 uses a plurality of word lines during a program operation in order to improve a problem that boosting efficiency is reduced in an unselected string 320 that does not include a target memory cell that is a target of a program operation. It is characterized by floating the GSL (312) disposed at the bottom of the (310). A detailed description thereof will be described with reference to FIGS. 4 to 5 below.

As another example, the 3D flash memory 300 corresponds to the target memory cell in order to prevent a fringing field generated in the target memory cell from affecting adjacent memory cells adjacent to upper and lower portions of the target memory cell. and applying a program voltage to the target word line and simultaneously applying a pass voltage to adjacent word lines adjacent to upper and lower portions of the target word line. A detailed description thereof will be described with reference to FIGS. 6 to 7 below.

Hereinafter, it is assumed that the program operation method described with reference to FIGS. 4 to 5 and 6 to 7 is performed by the 3D flash memory having the structure described with reference to FIGS. 3A to 3B.

4 is a flowchart illustrating a program operation method for improving boosting efficiency in an unselected string according to an exemplary embodiment, and FIG. 5 is a program operation method for improving boosting efficiency in the unselected string illustrated in FIG. 4 . It is a Y-Z cross-sectional view of a 3D flash memory for explaining the

4 to 5 , the 3D flash memory 500 may float the GSL disposed below the plurality of word lines 510 in operation S410 .

In step S410, the three-dimensional flash memory 500 floats the GSL to improve boosting efficiency in an unselected string (String 2, a string that does not include a target memory cell) except for the selected string (String 1). At the same time, you can float the Common Source Line (CSL) along with the GSL.

Such GSLs and CSLs can be floated in read operations as well as program operations described.

Subsequently, the 3D flash memory 500 applies the program voltage Vpgm to the target word line 511 corresponding to the target memory cell in step S420 , and applies the target word line (Vpgm) among the plurality of word lines 510 . The remaining word lines 512 except for 511 may be floated. For example, in operation S420 , the 3D flash memory 500 may apply a program voltage to the target word line 511 and float the remaining word lines 512 .

Accordingly, the 3D flash memory 500 may perform a program operation on the target memory cell by applying a voltage for the program operation to the back gates 520 and 521 in operation S430 .

In more detail, in step S430 , the 3D flash memory 500 provides a program voltage applied to the target word line 511 and a plurality of bit lines respectively connected to the plurality of strings String 1 and String 2 . In response to the applied voltages (the ground voltage 0V or the power supply voltage (Vcc)) and the power supply voltage applied to the SSL, only the target memory cell is programmed in the back gates 520 and 521 included in each of the plurality of strings. By applying the pass voltage Vpass, a program operation may be performed on the target memory cell.

For example, with respect to the selected string String 1, the 3D flash memory 500 performs a program voltage applied to the target word line 511 and a ground voltage applied to the bit line (eg, 0V) in step S430 . A pass voltage may be applied to the back gate 520 in response to the power voltage applied to the and SSL.

As another example, for the unselected string (String 2), the 3D flash memory 500 performs the program voltage applied to the target word line 511, the power supply voltage applied to the bit line, and SSL in step S430. A pass voltage may be applied to the back gate 521 in response to the applied power voltage.

As such, the program operation according to an embodiment is based on a method in which a pass voltage is applied to the back gates 520 and 521 rather than to a word line, and is applied to at least one remaining memory cell except for the target memory cell. Since the pass voltage is not applied to the corresponding word line, a disturbance phenomenon caused by the pass voltage being applied to the word line can be prevented. In addition, since the interference phenomenon is prevented, program operation characteristics are improved, cell characteristics and reliability can be improved, and a channel formation speed in the channel layer of the selected string String 1 can be improved.

In particular, since the GSL 520 and the CSL are floated through the step S410 in such a program operation, boosting efficiency in the unselected string String 2 may be improved.

6 is a flowchart illustrating a program operation method for preventing a fringing field of a target memory cell from affecting adjacent memory cells according to an exemplary embodiment, and FIG. 7 is a fringing of the target memory cell shown in FIG. 6 . It is a Y-X cross-sectional view of a 3D flash memory for explaining a program operation method for preventing a field from affecting adjacent memory cells.

6 to 7 , in step S610 , the three-dimensional flash memory 700 is configured to be connected to a target word line 711 corresponding to a target memory cell to be subjected to a program operation among a plurality of word lines 710 . A program voltage Vpgm may be applied.

Subsequently, the three-dimensional flash memory 700 is configured in step S620 to prevent a fringing field generated in the target memory cell from affecting adjacent memory cells adjacent to the upper and lower portions of the target memory cell, A pass voltage Vpass may be applied to adjacent word lines 712 and 713 adjacent to upper and lower portions of the target word line 711 .

Next, in operation S630 , the three-dimensional flash memory 700 includes the remaining word lines 714 excluding the target word line 711 and adjacent word lines 712 and 713 among the plurality of word lines 710 . ) can be plotted.

Accordingly, in operation S640 , the 3D flash memory 700 may apply a voltage for the program operation to the back gates 720 and 721 to perform the program operation on the target memory cell.

In more detail, in step S640 , the 3D flash memory 700 provides a program voltage applied to the target word line 711 and a plurality of bit lines respectively connected to the plurality of strings String 1 and String 2 . In response to the applied voltages (the ground voltage of 0V or the power supply voltage (Vcc)) and the power supply voltage applied to the SSL, only the target memory cell is programmed in the back gates 720 and 721 included in each of the plurality of strings. By applying the pass voltage Vpass, a program operation may be performed on the target memory cell.

For example, with respect to the selected string (String 1), the 3D flash memory 700 performs a program voltage applied to the target word line 711 and a ground voltage applied to the bit line (eg, 0V) in step S640 . A pass voltage may be applied to the back gate 720 in response to the power voltage applied to the and SSL.

As another example, for the unselected string (String 2), the 3D flash memory 700 performs the program voltage applied to the target word line 711, the power supply voltage applied to the bit line, and SSL in step S640. A pass voltage may be applied to the back gate 721 in response to the applied power voltage.

As such, the program operation according to an embodiment is based on a method in which a pass voltage is applied to the back gates 720 and 721 rather than to a word line, and is applied to at least one remaining memory cell except for the target memory cell. Since the pass voltage is not applied to the corresponding word line, a disturbance phenomenon caused by the pass voltage being applied to the word line can be prevented. In addition, since the interference phenomenon is prevented, program operation characteristics are improved, cell characteristics and reliability can be improved, and a channel formation speed in the channel layer of the selected string String 1 can be improved.

In particular, in such a program operation, a pass voltage is applied to the adjacent word lines 712 and 713 adjacent to the upper and lower portions of the target word line 711 through step S620, so that the fringing field generated in the target memory cell is reduced. Affecting adjacent memory cells adjacent to the upper and lower portions of the target memory cell may be prevented.

In the above, it has been described that the program operation method of FIGS. 4 to 5 and the program operation method of FIGS. 6 to 7 are individually performed, but the present invention is not limited thereto and may be performed in combination.

For example, by performing the program operation method through the following steps (steps 1 to 5), boosting efficiency in the unselected string String 2 is improved and the fringing field generated in the target memory cell is Affecting adjacent memory cells adjacent to the upper and lower portions of the target memory cell may be prevented.

Step 1: Float the GSL and CSL disposed at the bottom of the plurality of word lines.

Step 2: A program voltage is applied to the target word line corresponding to the target memory cell.

Step 3: A pass voltage is applied to adjacent word lines adjacent to upper and lower portions of the target word line.

Step 4: Floating the remaining word lines excluding the target word line and adjacent word lines among the plurality of word lines.

Step 5: A program operation is performed on the target memory cell by applying a voltage for the program operation to the back gate.

Operations of the 3D flash memory in steps 1 to 5 may be performed in the same manner as described with reference to FIGS. 4 to 5 and 6 to 7 .

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (12)

A three-dimensional flash memory for improving program operation, comprising:
a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and
a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in one direction to surround the channel layer and the channel layer extending in the one direction and a charge storage layer formed, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer;
including,
The three-dimensional flash memory,
and floating a ground selection line (GSL) disposed below the plurality of word lines during the program operation. According to claim 1,
The three-dimensional flash memory,
Floating the GSL during the program operation to improve boosting efficiency in an unselected string except for a selected string including a target memory cell to be subjected to the program operation among the plurality of strings 3D flash memory. According to claim 1,
The three-dimensional flash memory,
3D flash memory, characterized in that the CSL (Common Source Line) is floated together with the GSL during the program operation. According to claim 1,
The three-dimensional flash memory,
A three-dimensional flash memory characterized in that the GSL is floated during a read operation. a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. A method for programming a three-dimensional flash memory, comprising: a back gate extending in one direction; and an insulating layer extending in the one direction between the back gate and the channel layer;
floating a ground selection line (GSL) disposed below the plurality of word lines;
applying a program voltage to a target word line corresponding to a target memory cell to be subjected to a program operation, and floating word lines other than the target word line among the plurality of word lines; and
performing a program operation on the target memory cell by applying a voltage for the program operation to the back gate
3D flash memory program operation method comprising a. 6. The method of claim 5,
Floating the GSL comprises:
In order to improve boosting efficiency in an unselected string except for the selected string including the target memory cell, the GSL is floated. 6. The method of claim 5,
Floating the GSL comprises:
Plotting a Common Source Line (CSL) with the GSL
3D flash memory program operation method comprising a. A three-dimensional flash memory for improving program operation, comprising:
a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and
a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in one direction to surround the channel layer and the channel layer extending in the one direction and a charge storage layer formed, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. a back gate extending in one direction and an insulating layer extending in the one direction between the back gate and the channel layer;
including,
The three-dimensional flash memory,
In the program operation, a program voltage is applied to a target word line corresponding to a target memory cell to be programmed, and a pass voltage is applied to adjacent word lines adjacent to upper and lower portions of the target word line. 3D flash memory. 9. The method of claim 8,
The three-dimensional flash memory,
In order to prevent a fringing field generated in the target memory cell from affecting adjacent memory cells adjacent to upper and lower portions of the target memory cell, a pass voltage is applied to the adjacent word lines during the program operation. A three-dimensional flash memory, characterized in that. 9. The method of claim 8,
The three-dimensional flash memory,
and floating word lines other than the target word line and the adjacent word lines among the plurality of word lines. a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the channel layer is at least partially surrounded by the channel layer. A method for programming a three-dimensional flash memory, comprising: a back gate extending in one direction; and an insulating layer extending in the one direction between the back gate and the channel layer;
applying a program voltage to a target word line corresponding to a target memory cell to be subjected to a program operation;
applying a pass voltage to adjacent word lines adjacent to upper and lower portions of the target word line;
floating word lines other than the target word line and the adjacent word lines among the plurality of word lines; and
performing a program operation on the target memory cell by applying a voltage for the program operation to the back gate
3D flash memory program operation method comprising a. 12. The method of claim 11,
The step of applying a pass voltage to the adjacent word lines includes:
In order to prevent a fringing field generated in the target memory cell from affecting adjacent memory cells adjacent to upper and lower portions of the target memory cell, a pass voltage is applied to the adjacent word lines. 3D flash memory program operation method.

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