KR102578390B1 - Three dimensional flash memory including air gap - Google Patents

Abstract

A three-dimensional flash memory having a structure including an air gap and a method of manufacturing the same are disclosed. According to one embodiment, a three-dimensional flash memory includes a plurality of word lines extending in the horizontal direction on a substrate and sequentially stacked; and at least one string extending in the vertical direction on the substrate through the plurality of word lines - the at least one string is formed in the form of a hollow tube and surrounds the channel layer and extending in the vertical direction. and a charge storage layer extending in the vertical direction, and an air gap may be formed inside the channel layer extending in the vertical direction.

Description

3D flash memory including air gap and manufacturing method thereof {THREE DIMENSIONAL FLASH MEMORY INCLUDING AIR GAP}

The following embodiments relate to 3D flash memory, and more specifically, technology for 3D flash memory with a structure including an air gap.

Flash memory devices are electrically erasable programmable read only memory (EEPROM), which are used in, for example, computers, digital cameras, MP3 players, gaming systems, and memory sticks. ) can be commonly used, etc. These flash memory devices electrically control input and output of data by Fowler-Nordheim tunneling (F-N tunneling) or hot electron injection.

Specifically, referring to FIG. 1 showing an array of an existing three-dimensional flash memory, the array of three-dimensional flash memory includes a common source line (CSL), a bit line (BL), and a common source line (CSL) and a bit line (BL). ) may include a plurality of cell strings (CSTR) arranged between the cells.

The bit lines are arranged two-dimensionally, and a plurality of cell strings (CSTR) are connected in parallel to each of them. The cell strings (CSTR) may be commonly connected to the common source line (CSL). That is, a plurality of cell strings (CSTR) may be disposed between a plurality of bit lines and one common source line (CSL). At this time, there may be a plurality of common source lines (CSL), and the plurality of common source lines (CSL) may be arranged two-dimensionally. Here, the same electrical voltage may be applied to the plurality of common source lines (CSL), or each of the plurality of common source lines (CSL) may be electrically controlled.

Each of the cell strings (CSTR) has a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), and ground and string select transistors (GST, SST) ) may be composed of a plurality of memory cell transistors (MCT) disposed between. Additionally, the ground select transistor (GST), string select transistor (SST), and memory cell transistors (MCT) may be connected in series.

The common source line (CSL) may be commonly connected to the sources of the ground selection transistors (GST). In addition, a ground selection line (GSL), a plurality of word lines (WL0-WL3), and a plurality of string selection lines (SSL) disposed between the common source line (CSL) and the bit line (BL) select the ground. Can be used as electrode layers of transistors (GST), memory cell transistors (MCT), and string select transistors (SST), respectively. Additionally, each memory cell transistor (MCT) includes a memory element. Hereinafter, the string selection line (SSL) may be expressed as an upper selection line (USL), and the ground selection line (GSL) may be expressed as a lower selection line (Lower Selection Line (LSL)).

Meanwhile, existing 3D flash memory is increasing its integration by vertically stacking cells to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of an existing 3D flash memory, the existing 3D flash memory has interlayer insulating layers 211 and horizontal structures 250 alternately placed on a substrate 200. The repeatedly formed electrode structure 215 is disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide film, and the lowest interlayer insulating layer 211a among the interlayer insulating layers 211 may have a thinner thickness than the remaining interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking insulating films 242 and 243 and an electrode layer 245. A plurality of electrode structures 215 are provided, and the plurality of electrode structures 215 may be arranged to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and y-axis of FIG. 2, respectively. Between the plurality of electrode structures 215, trenches 240 separating them may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 and a common source line (CSL) may be disposed. Although not shown, additional isolation insulating films that fill the trenches 240 may be disposed.

Vertical structures 230 may be disposed penetrating the electrode structure 215. For example, the vertical structures 230 may be arranged in a matrix form by being aligned along the first and second directions from a plan view. As another example, the vertical structures 230 are aligned in the second direction, but may also be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a protective film 224, a charge storage film 225, a tunnel insulating film 226, and a channel layer 227. For example, the channel layer 227 may be disposed in the form of a hollow tube, and in this case, a buried film 228 (formed of oxide) that fills the inside of the channel layer 227 may be further disposed. You can. A drain region D is disposed on the top of the channel layer 227, and a conductive pattern 229 is formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250, for example, in the second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating films 242 and 243 included in the horizontal structures 250 and the charge storage film 225 and tunnel insulating film 226 included in the vertical structures 230 are used in the three-dimensional flash memory. It can be defined as an ONO (Oxide-Nitride-Oxide) layer, which is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230, and others may be included in the horizontal structures 250. For example, among the information storage elements, the charge storage film 225 and the tunnel insulating film 226 are included in the vertical structures 230, and the first and second blocking insulating films 242 and 243 are included in the horizontal structures 250. may be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230. Epitaxial patterns 222 connect the substrate 200 and the vertical structures 230. The epitaxial patterns 222 may contact at least one layer of horizontal structures 250. That is, the epitaxial patterns 222 may be arranged to contact the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be arranged to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are arranged to contact the lowermost horizontal structure 250a, the lowermost horizontal structure 250a may be arranged to be thicker than the remaining horizontal structures 250. The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line (GSL) of the array of the three-dimensional flash memory described with reference to FIG. 1, and the vertical structures 230 The remaining horizontal structures 250 adjacent to may correspond to a plurality of word lines (WL0-WL3).

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed side wall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewall 222a of the epitaxial patterns 222.

In the existing three-dimensional flash memory with such a structure, since the channel layer 227 is in contact with the tunnel insulating film 226 and the buried film 228 inside and out as shown in FIG. 3, the channel layer 227 and the tunnel insulating film ( 226) Surface scattering occurs at the interface 310 between the channel layer 227 and the buried film 228, and surface scattering also occurs at the interface 320 between the channel layer 227 and the buried film 228, thereby reducing the channel current flowing in the channel layer 227. have a problem.

Therefore, in the embodiments below, there is a need to propose a technology to solve the problem of reduced channel current in existing 3D flash memory.

One embodiment is a structure in which an air gap is formed to extend in the vertical direction inside the channel layer to increase channel current by suppressing surface scattering at the interface between channel layers and improving charge mobility. A 3D flash memory and its manufacturing method are proposed.

According to one embodiment, a three-dimensional flash memory includes a plurality of word lines extending in the horizontal direction on a substrate and sequentially stacked; and at least one string extending in the vertical direction on the substrate through the plurality of word lines - the at least one string is formed in the form of a hollow tube and surrounds the channel layer and extending in the vertical direction. and a charge storage layer extending in the vertical direction, and an air gap may be formed inside the channel layer extending in the vertical direction.

According to one aspect, the air gap may be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers.

According to another aspect, a cap for maintaining the air gap may be disposed on the top of the at least one string.

According to another aspect, the cap may be formed of a material different from the channel layer.

According to another aspect, the cap may be made of a material that does not form a channel by a voltage applied through the plurality of word lines.

According to another aspect, the cap may be formed of a material having a lower charge mobility than that of the channel layer.

According to another aspect, the air gap may be formed in a vacuum state or in a gas-injected state.

According to one embodiment, a method of manufacturing a three-dimensional flash memory includes: a plurality of word lines extending in the horizontal direction on a substrate and sequentially stacked; and at least one string extending in the vertical direction on the substrate through the plurality of word lines - the at least one string is formed in the form of a hollow tube and surrounds the channel layer and extending in the vertical direction. Preparing a semiconductor structure including a charge storage layer extending in the vertical direction - the interior of the channel layer including a hole extending in the vertical direction; And it may include forming a cap to seal the top of the hole, thereby creating an air gap inside the channel layer.

According to one aspect, the air gap may be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers.

According to another aspect, the cap may be formed of a material different from the channel layer.

According to another aspect, the step of creating the air gap includes forming the cap on the top of the hole with a material that does not form a channel by a voltage applied through the plurality of word lines. You can do this.

According to another aspect, forming the cap may further include placing the semiconductor structure in a chamber and adjusting the pressure of the space where the semiconductor structure is located.

One embodiment proposes a three-dimensional flash memory with a structure in which an air gap extends vertically inside the channel layer and a manufacturing method thereof, thereby suppressing surface scattering at the interface between channel layers to improve charge mobility. Channel current can be increased by improving mobility.

Figure 1 is a simplified circuit diagram showing an existing three-dimensional flash memory array.
Figure 2 is a perspective view showing the structure of an existing three-dimensional flash memory.
FIG. 3 is a diagram illustrating a decrease in channel current due to surface scattering at the interface between channel layers in a conventional 3D flash memory.
Figure 4 is a YZ cross-sectional view showing a three-dimensional flash memory according to an embodiment.
FIG. 5 is a diagram for explaining increasing channel current in the three-dimensional flash memory shown in FIG. 4.
Figure 6 is a flow chart showing a method of manufacturing a 3D flash memory according to an embodiment.
FIGS. 7A to 7C are YZ cross-sectional views showing a three-dimensional flash memory to explain an embodiment of the manufacturing method shown in FIG. 6.
FIGS. 8A to 8C are YZ cross-sectional views showing a three-dimensional flash memory to explain another embodiment of the manufacturing method shown in FIG. 6.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. However, the present invention is not limited or limited by the examples. Additionally, the same reference numerals in each drawing indicate the same members.

In addition, the terminology used in this specification is a term used to appropriately express preferred embodiments of the present invention, and may vary depending on the intention of the user or operator or the customs of the field to which the present invention belongs. Therefore, definitions of these terms should be made based on the content throughout this specification.

Hereinafter, in the Y-Z cross-sectional view showing the three-dimensional flash memory, components such as the bit line located above the plurality of strings and the source line located below the plurality of strings are omitted for convenience of explanation. Can be shown and explained. However, the 3D flash memory described later is not limited or limited thereto and may further include additional components based on the structure of the existing 3D flash memory shown with reference to FIG. 2.

FIG. 4 is a Y-Z cross-sectional view showing a three-dimensional flash memory according to an embodiment, and FIG. 5 is a diagram for explaining increasing the channel current in the three-dimensional flash memory shown in FIG. 4.

Referring to FIGS. 4 and 5 , a three-dimensional flash memory 400 according to an embodiment includes a plurality of word lines 410 and at least one string 420.

The plurality of word lines 410 are sequentially stacked extending in the horizontal direction (e.g., Y direction) on the substrate 405, and each of W (tungsten), Ti (titanium), Ta (tantalum), and Cu ( It is formed of a conductive material such as copper), Mo (molybdenum), Ru (ruthenium), or Au (gold) (all metal materials capable of forming ALD are included in addition to the metal materials described), and a voltage is applied to the corresponding memory cells. Memory operations (read operations, program operations, and erase operations, etc.) can be performed. A plurality of insulating layers 411 formed of an insulating material may be interposed between the plurality of word lines 410.

A string selection line (SSL) may be placed at the top of the plurality of word lines 410, and a ground selection line (GSL) may be placed at the bottom.

At least one string 420 extends in the vertical direction (e.g., Z direction) on the substrate 405 through the plurality of word lines 410, and each of the strings 420 includes a channel layer 421 and a charge storage layer ( By including 422), a plurality of memory cells corresponding to the plurality of word lines 410 can be configured.

The charge storage layer 422 extends to surround the channel layer 421 and traps charges or holes due to voltage applied through the plurality of word lines 410, or stores the state of charges (e.g., charges As a component that maintains the polarization state of the flash memory 400, it can serve as a data storage in the three-dimensional flash memory 400. For example, an Oxide-Nitride-Oxide (ONO) layer or a ferroelectric layer may be used as the charge storage layer 422.

The channel layer 421 is a component that performs a memory operation by voltage applied through the plurality of word lines 410, SSL, GSL, and bit lines, and may be formed of polycrystalline silicon or polysilicon.

Here, an air gap 423 may be formed to extend in the vertical direction inside the channel layer 421. The air gap 423 may be maintained in a vacuum state or a gas-injected state by a cap 424 disposed on the top of the channel layer 421.

This air gap 423 can be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers 421. More specifically, in the structure including the air gap 423, as shown in FIG. 5, between the channel layer 421 and the charge storage layer 422 (e.g., the external oxide layer included in the charge storage layer 422) Since surface scattering occurs only at the interface 510, the charge mobility is lower than the existing structure in which both surface scattering at the interface between the channel layer and the inner oxide layer and surface scattering at the interface between the channel layer and the outer oxide layer occur. Improvements can be made to increase channel current.

At this time, the cap 424 may be formed of a different material from the channel layer 421 so as to have no or minimal effect on the memory operation of the three-dimensional flash memory 400 due to the formation of a channel in the channel layer 421. That is, the cap 424 is made of a material that does not form a channel by a voltage applied through the plurality of word lines 410, thereby forming a channel in the channel layer 421, thereby forming the three-dimensional flash memory 400. It may not affect the memory operation of . Alternatively, the cap 424 is made of a material with a charge mobility that is at least lower than the charge mobility of the channel layer 421, thereby forming a channel in the channel layer 421, resulting in the memory of the three-dimensional flash memory 400. The impact on operation can be minimized.

FIG. 6 is a flow chart showing a manufacturing method of a three-dimensional flash memory according to an embodiment, and FIGS. 7A to 7C are Y-Z cross-sectional views showing a three-dimensional flash memory to explain an embodiment of the manufacturing method shown in FIG. 6. , FIGS. 8A to 8C are Y-Z cross-sectional views showing a three-dimensional flash memory to explain another embodiment of the manufacturing method shown in FIG. 6.

Hereinafter, the manufacturing method described later is assumed to be performed by an automated and mechanized manufacturing system, and the three-dimensional flash memory manufactured through the manufacturing method may have the structure described with reference to FIGS. 4 and 5.

Referring to FIG. 6 , the manufacturing system according to one embodiment may prepare semiconductor structures 710 and 810 as shown in FIG. 7A or 8A in step S610.

Here, the semiconductor structures 710 and 810 are formed to extend in the horizontal direction on the substrates 705 and 805 and pass through a plurality of sequentially stacked word lines 711 and 811 and a plurality of word lines 711 and 811. Thus, it may include at least one string (720, 820) extending in the vertical direction on the substrates (705, 805). At least one string (720, 820) has a channel layer (721, 821) extending in the vertical direction in the form of an empty tube, and a charge storage layer (721, 821) extending in the vertical direction to surround the channel layers (721, 821). 722 and 822), and since the channel layers 721 and 821 have an empty tube shape, they may include holes 723 and 823 extending in the vertical direction.

Next, in step S620, the manufacturing system forms caps 730 and 830 that seal the tops of the holes 723 and 823 included in the semiconductor structures 710 and 810, thereby forming the channel layer 721. Air gaps 740 and 840 may be created inside 821).

The air gap (740, 840) can be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers (721, 821), and the cap (730, 830) Different from the channel layers 721 and 821, such as a material having a charge mobility lower than that of the channel layer 721 or a material that does not form a channel by the voltage applied through the plurality of word lines 711. It can be formed from materials.

At this time, the manufacturing system may adjust the pressure of the space where the semiconductor structures 710 and 810 are located by placing the semiconductor structures 710 and 810 in a chamber in step S620.

Referring to FIGS. 7B to 7C as an example of step S620, the manufacturing system seals the top of the hole 723 with non-conformality polysilicon as shown in FIG. 7B and then performs a planarization process as shown in FIG. 7C. By forming the cap 730, an air gap 740 can be created inside the channel layer 721.

Referring to FIGS. 8B to 7C as another example of step S620, the manufacturing system deposits a metal material on the top of the hole 823 as shown in FIG. 8B to seal it, and then performs a planarization process as shown in FIG. 8C. By forming the cap 830, an air gap 840 can be created inside the channel layer 821.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (12)

A plurality of word lines extending in the horizontal direction on the substrate and sequentially stacked; and
At least one string passing through the plurality of word lines and extending in a vertical direction on the substrate, wherein the at least one string has a hollow tube shape and surrounds the channel layer and the channel layer extending in the vertical direction. Comprising a charge storage layer extending in the vertical direction -
Including,
Inside the channel layer,
An air gap that directly contacts the inner surface of the channel layer - the air gap is used to improve charge mobility by suppressing surface scattering at the inner interface of the channel layer - Characterized in that it extends in the vertical direction,
A cap disposed at the top of the at least one string to maintain the air gap,
A three-dimensional flash memory characterized in that it is formed of a material different from the channel layer so as to have a charge mobility lower than that of the channel layer without forming a channel by the voltage applied through the plurality of word lines. delete delete delete delete delete According to paragraph 1,
The air gap is,
A three-dimensional flash memory characterized in that it is formed in a vacuum state or a gas-injected state. A plurality of word lines extending in the horizontal direction on the substrate and sequentially stacked; and at least one string extending in the vertical direction on the substrate through the plurality of word lines - the at least one string is formed in the form of a hollow tube and surrounds the channel layer and extending in the vertical direction. Preparing a semiconductor structure including a charge storage layer extending in the vertical direction - the interior of the channel layer including a hole extending in the vertical direction; and
Forming a cap to seal the top of the hole to create an air gap inside the channel layer.
Including,
The air gap in direct contact with the inner surface of the channel layer is,
It is used to improve charge mobility by suppressing surface scattering at the inner interface of the channel layer,
The cap is,
A three-dimensional flash memory characterized in that it is formed of a material different from the channel layer to have a charge mobility lower than that of the channel layer without forming a channel by the voltage applied through the plurality of word lines. Manufacturing method. delete delete delete According to clause 8,
The step of creating the air gap is,
Positioning the semiconductor structure in a chamber to control the pressure of the space where the semiconductor structure is located
A method of manufacturing a three-dimensional flash memory, further comprising: