KR20220028776A - Three dimensional flash memory with back gate - Google Patents

Abstract

Disclosed is a three-dimensional flash memory with a back gate, capable of having a structure for improving a cell property and reliability. According to an embodiment of the present invention, the three-dimensional flash memory with the back gate includes: a plurality of word lines extended in a horizontal direction on a substrate and laminated in order; and a plurality of strings extended in one direction on the substrate by passing through the plurality of word lines. Each of the strings includes: a channel layer extended in the one direction; and a charge storing layer extended in the one direction to enclose the channel layer. The channel layer and the charge storing layer include a plurality of memory cells corresponding to the word lines. The back gate extended in the one direction and an insulating film extended in the one direction to enclose the back gate are arranged in the channel layer. The three-dimensional flash memory has the structure in which the back gate is formed to be extended in the channel layer.

Description

THREE DIMENSIONAL FLASH MEMORY WITH BACK GATE

The following embodiments relate to a three-dimensional flash memory, and more particularly, to a three-dimensional flash memory having a structure for improving cell characteristics and reliability, and a technology for an operating method thereof.

A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, in a computer, digital camera, MP3 player, game system, memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line LSL.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking insulating layers 242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. As an example, the vertical structures 230 may be arranged in a matrix form aligned along the first and second directions in a plan view. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in a hollow tube shape therein, and in this case, a buried film 228 filling the inside of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating layers 242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the three-dimensional flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and some of the information storage elements may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking insulating layers 242 and 243 are the horizontal structures 250 . can be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to contact the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

The conventional three-dimensional flash memory having such a structure has a problem in that cell characteristics and reliability are deteriorated due to an increase in the number of vertical memory cells.

Accordingly, the following embodiments intend to propose a technique for improving cell characteristics and reliability.

In order to improve cell characteristics and reliability, one embodiment proposes a three-dimensional flash memory having a structure in which a back gate is extended inside a channel layer.

More specifically, embodiments propose a three-dimensional flash memory including a back gate to which a pass voltage for forming a channel or boosting a channel layer is applied.

According to an embodiment, a 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; and an insulating layer extending in the one direction to surround the back gate and the back gate.

According to an aspect, a pass voltage for forming a channel in the channel layer or boosting the channel layer may be applied to the back gate during a program operation on a target memory cell.

According to another aspect, in the channel layer included in the selected string corresponding to the target memory cell among the plurality of strings, a ground voltage is applied to a bit line of the selected string, and a ground voltage is applied to the bit line of the plurality of word lines. A program voltage is applied to a word line corresponding to a target memory cell, the pass voltage is applied to the back gate, and at the same time, word lines corresponding to the remaining memory cells except for the target memory cell among the plurality of word lines are floated ( floating), forming a channel for a program operation on the target memory cell.

According to another aspect, in the channel layer included in the unselected string that does not correspond to the target memory cell among the plurality of strings, a power voltage is applied to a bit line of the unselected string, and the A power voltage is applied to a string selection line (SSL) to float the unselected string itself, and at the same time, the pass voltage is applied to the back gate, thereby boosting the unselected string by the program voltage for the target memory cell. It may be characterized in that the included memory cells are prevented from being programmed.

According to another aspect, in the insulating layer, a region corresponding to a ground selection line (GSL) disposed below the plurality of word lines or a region corresponding to the GSL in the channel layer may reduce the leakage current in the GSL. It may be characterized in that it has a structure to prevent it.

According to another aspect, the back gate may be formed to extend over an inner region of the channel layer corresponding to the plurality of word lines.

According to another aspect, the back gate is formed to extend through the substrate on which the plurality of strings are extended and extend to a substrate for the back gate positioned below the substrate on which the plurality of strings are extended, , the substrate for the back gate may be used for heat dissipation of the plurality of strings.

According to another aspect, a wiring for a voltage applied to the back gate may be formed on any one surface of an upper surface or a lower surface of the substrate for the back gate.

According to another aspect, the back gate is formed to extend to a back gate plate disposed in a horizontal direction between the plurality of word lines and the substrate, and the back gate plate includes: It may be characterized in that it serves to prevent warpage of the substrate by alleviating film stress of the plurality of word lines between the substrates.

According to another aspect, in the back gate during the read operation on the plurality of memory cells, a program enhancement voltage for increasing the threshold voltage of the plurality of memory cells to improve the program speed of the plurality of memory cells It may be characterized in that it is authorized.

According to another aspect, an erase voltage for memory cells included in the plurality of strings may be applied to the back gate during an erase operation.

According to another aspect, in the back gate during a program operation on a target memory cell, a program enhancement voltage for forming an inversion in the channel layer in the program operation and improving a program speed of the target memory cell It may be characterized in that it is approved.

According to another aspect, voltages for performing an erase operation on memory cells included in the plurality of strings in two steps may be applied to the back gate during an erase operation.

According to another aspect, in the first step of the erase operation, a ground voltage for generating a hole is applied to the back gate as the plurality of word lines float, and in the second step of the erase operation, the back gate The gate may be floated for hole injection as a ground voltage is applied to the plurality of word lines.

According to an embodiment, in a method of manufacturing a 3D flash memory, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked, a plurality of insulating layers alternately stacked between the plurality of word lines and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. preparing a semiconductor structure including a charge storage layer extending to form a hole, wherein a hole is formed to extend in the one direction in the channel layer in the semiconductor structure; forming an insulating film including an inner hole in the hole to extend in the one direction; and extending the back gate in the one direction using a conductive material in the inner hole of the insulating layer.

According to one aspect, the back gate may be characterized in that a pass voltage for forming a channel in the channel layer or boosting the channel layer is applied.

According to another aspect, the hole in the channel layer extends through the substrate on which the plurality of strings are extended to the substrate for the back gate positioned below the substrate on which the plurality of strings are extended. It may be characterized in that it is extended.

According to another exemplary embodiment, in a method of manufacturing a 3D flash memory, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked, and a plurality of insulating layers alternately stacked between the plurality of word lines and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction and extending in the one direction to surround the channel layer A semiconductor structure including a charge storage layer extending from preparing a first insulating film formed thereon; forming a second insulating film including an inner hole in the hole to extend in the one direction; and extending the back gate in the one direction using a conductive material in the inner hole of the second insulating layer.

According to another exemplary embodiment, in a method of manufacturing a 3D flash memory, a plurality of sacrificial layers are formed extending in a horizontal direction on a substrate and sequentially stacked, and a plurality of insulating layers are alternately stacked between the plurality of sacrificial layers. a plurality of strings extending in one direction on the substrate through the layers and the plurality of sacrificial layers; preparing a semiconductor structure including a charge storage layer extending in a direction, wherein a hole is formed to extend in the one direction within the channel layer in the semiconductor structure; forming an insulating film including an inner hole in the hole to extend in the one direction; removing the plurality of sacrificial layers; and forming a plurality of word lines using a conductive material in a space from which the plurality of sacrificial layers are removed, and extending the back gate using the conductive material in the inner hole of the insulating layer in the one direction, Forming the plurality of word lines with a material and forming the back gate to extend in the one direction may be simultaneously performed.

According to another exemplary embodiment, in a method of manufacturing a 3D flash memory, a plurality of lower word lines extending in a horizontal direction on a substrate and sequentially stacked, a plurality of alternately stacked between the plurality of lower word lines a plurality of lower strings extending in one direction on the substrate through lower insulating layers and the plurality of lower word lines of A lower semiconductor structure including a lower charge storage layer extending in the one direction to surround the lower channel layer, a lower back gate extending in the one direction and the lower back gate being formed inside the lower channel layer preparing a lower insulating film extending in the one direction to surround it; A plurality of upper word lines sequentially stacked, a plurality of upper insulating layers alternately stacked between the plurality of upper word lines, and a plurality of upper portions extending in one direction through the plurality of upper word lines An upper semiconductor structure including strings, each of the plurality of upper strings including an upper channel layer extending in the one direction and an upper charge storage layer extending in the one direction to surround the upper channel layer preparing an upper back gate extending in the one direction and an upper insulating layer extending in the one direction to surround the upper back gate in the upper channel layer; and stacking the upper semiconductor structure on top of the lower semiconductor structure so that the cross section of the lower back gate and the cross section of the upper back gate coincide.

According to an embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; A method of programming a three-dimensional flash memory in which a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed to apply a voltage to form a channel to the back gate, forming a channel in the channel layer or applying a pass voltage to boost the channel layer to a gate; A ground voltage is applied to a bit line of a selected string corresponding to a target memory cell to be subjected to a program operation among the plurality of strings, and a program voltage is applied to a word line corresponding to the target memory cell among the plurality of word lines. is applied, and as the pass voltage is applied to the back gate and word lines corresponding to the remaining memory cells except for the target memory cell among the plurality of word lines are floated, the word lines included in the selected string forming a channel for a program operation on the target memory cell in a channel layer; and a power voltage is applied to a bit line of an unselected string that does not correspond to the target memory cell among the plurality of strings, and a power voltage is applied to the SSL of the unselected string so that the unselected string itself floats and the back and boosting a channel layer included in the unselected string as the pass voltage is applied to a gate to prevent the memory cells included in the unselected string from being programmed by a program voltage for the target memory cell. do.

According to an embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; A read operation method of a three-dimensional flash memory in which a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed to apply a voltage for forming a channel to the back gate, applying a program enhancement voltage for increasing threshold voltages of the plurality of memory cells to a gate to improve a program speed for the plurality of memory cells; and a power voltage is applied to a bit line of a selected string corresponding to a target memory cell to be read operation from among the plurality of strings, and a verification voltage is applied to a word line corresponding to the target memory cell among the plurality of word lines and performing a read operation on the selected string as a pass voltage is applied to word lines corresponding to memory cells other than the target memory cell among the plurality of word lines.

According to an embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; An erase operation method of a three-dimensional flash memory in which a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed to apply a voltage to form a channel to the back gate, and applying an erase voltage to the memory cells included in the plurality of strings to the gate.

According to another embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; A method of programming a three-dimensional flash memory in which a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed to apply a voltage to form a channel to the back gate, applying a program enhancement voltage to the gate to improve a program speed of a target memory cell to be subjected to a program operation; applying a pass voltage to the word lines other than the word line corresponding to the target memory cell among the plurality of word lines; and forming an inversion in a channel layer included in a selected string corresponding to the target memory cell among the plurality of strings as the program enhancement voltage is applied to the back gate.

According to another embodiment, a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in the one direction and extending in the one direction to surround the channel layer and the channel layer. and an extended charge storage layer, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines; An erase operation method of a three-dimensional flash memory in which a back gate extending in the one direction so as to be able to apply a voltage for forming a channel therein and an insulating layer extending in the one direction to surround the back gate are disposed, in a first step of applying a ground voltage for generating a hole to the back gate as the plurality of word lines are floated; and floating the back gate for hole injection as a ground voltage is applied to the plurality of word lines in a second step of the erase operation.

In order to improve cell characteristics and reliability, the exemplary embodiments may propose a 3D flash memory having a structure in which a back gate is extended inside a channel layer.

More specifically, embodiments may propose a 3D flash memory including a back gate to which a pass voltage for forming a channel or boosting a channel layer is applied.

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.
2 is a perspective view showing the structure of a conventional three-dimensional flash memory.
3A is a YZ cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment.
FIG. 3B is an XY plan view illustrating a cross-section taken along line A-A' of the three-dimensional flash memory shown in FIG. 3A.
4A to 4D are YZ cross-sectional views illustrating another implementation example of a 3D flash memory according to an embodiment.
5A to 5B are YZ cross-sectional views illustrating a 3D flash memory according to another exemplary embodiment.
6 is a flowchart illustrating a program operation of a 3D flash memory according to an exemplary embodiment.
7 is a YZ cross-sectional view illustrating a program operation of a 3D flash memory according to an exemplary embodiment.
8 is a flowchart illustrating a program operation of a 3D flash memory according to another exemplary embodiment.
9 is a YZ cross-sectional view illustrating a program operation of a 3D flash memory according to another exemplary embodiment.
10 is a flowchart illustrating a read operation of a 3D flash memory according to an exemplary embodiment.
11 is a flowchart illustrating an erase operation of a 3D flash memory according to an exemplary embodiment.
12 is a flowchart illustrating an erase operation of a 3D flash memory according to another exemplary embodiment.
13 is a YZ cross-sectional view illustrating an erase operation of a 3D flash memory according to another exemplary embodiment.
14 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment.
15A to 15D are YZ cross-sectional views illustrating a first implementation example of the manufacturing method of the 3D flash memory shown in FIG. 14 .
16A to 16B are YZ cross-sectional views illustrating a second implementation example of the method of manufacturing the 3D flash memory shown in FIG. 14 .
17 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment.
18A to 18K are YZ cross-sectional views for explaining an example implementation of the method of manufacturing the 3D flash memory shown in FIG. 17 .
19 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment.
20A to 20D are YZ cross-sectional views for explaining an example implementation of the method of manufacturing the 3D flash memory shown in FIG. 19 .
21 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment.
22A to 22B are YZ cross-sectional views for explaining an implementation example of the manufacturing method of the 3D flash memory shown in FIG. 21 .
23 is an XY plan view illustrating a back gate having an improved structure according to an exemplary embodiment.
24 to 27 are XY plan views for explaining a back gate having an improved structure according to another exemplary embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary according to the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

Hereinafter, in the YZ cross-sectional view showing the three-dimensional flash memory, components such as a bit line positioned above the plurality of strings and a source line positioned below the plurality of strings are omitted for the convenience of description of the three-dimensional flash memory. can be illustrated and described. However, the 3D flash memory to be described later is not limited thereto, and may further include additional components based on the structure of the existing 3D flash memory illustrated with reference to FIG. 2 .

3A is a YZ cross-sectional view illustrating a three-dimensional flash memory according to an embodiment, FIG. 3B is an XY plan view illustrating a cross-section A-A′ of the three-dimensional flash memory shown in FIG. 3A, and FIGS. 4A to 4D are one embodiment It is a YZ cross-sectional view illustrating another implementation example of a three-dimensional flash memory according to an embodiment, and FIGS. 5A to 5B are YZ cross-sectional views illustrating a three-dimensional flash memory according to another embodiment.

3A to 3B , the 3D flash memory 300 according to an embodiment includes a plurality of word lines 310 and a plurality of strings 320 and 330 .

A plurality of word lines 310 are sequentially stacked while extending in a horizontal direction (eg, Y direction) on the substrate 305 , respectively, W (tungsten), Ti (titanium), Ta (tantalum), Cu ( Copper), Mo (molybdenum), Ru (ruthenium), or Au (gold), such as conductive material (all metal materials capable of forming ALD are included in addition to the metal materials described above), and applying a voltage to the corresponding memory cells A memory operation (such as a read operation, a program operation, and an erase operation) may be performed. A plurality of insulating layers 311 formed of an insulating material may be interposed between the plurality of word lines 310 .

A String Selection Line (SSL) may be disposed at the upper end of the plurality of word lines 310 , and a Ground Selection Line (GSL) may be disposed at the lower end of the plurality of word lines 310 .

The plurality of strings 320 and 330 pass through the plurality of word lines 310 to extend in one direction (eg, the Z direction) on the substrate 305 , and each of the channel layers 321 and 331 and By including the charge storage layers 322 and 332 , a plurality of memory cells corresponding to the plurality of word lines 310 may be configured.

The charge storage layers 322 and 332 are formed to extend to surround the channel layers 321 and 331 , and are a component in which charges generated by a voltage applied through the plurality of word lines 310 are stored. 300 may serve as a data store. For example, an oxide-nitride-oxide (ONO) layer may be used as the charge storage layers 322 and 332 .

The channel layers 321 and 331 are components that perform a memory operation by a voltage applied through the plurality of word lines 310, SSL, GSL, and bit lines, and may be formed of crystalline silicon or polysilicon. there is. Also, the channel layers 321 and 331 may perform a memory operation by a voltage applied through the back gates 323 and 333 to be described later. A detailed description thereof will be provided below.

Inside the channel layers 321 and 331, the back gates 323 and 333 extending in one direction (eg, the Z direction) and an insulating layer 324 extending in one direction to surround the back gates 323 and 333; 334) is placed.

Here, the channel layers 321 and 331 may have a structure for preventing leakage current in the GSL. For example, in the channel layers 321 and 331 , the region corresponding to the GSL disposed at the lower end of the plurality of word lines 310 is B (boron) in the region corresponding to the GSL among the channel layers 321 and 331 . It may have a structure to increase the threshold voltage of the corresponding region by adding more.

The back gates 323 and 333 may include W (tungsten), Ti (titanium), Ta (tantalum), Cu (copper), Mo (molybdenum), and Ru (ruthenium) to enable voltage application to the channel layers 321 and 331 . ) or a conductive material such as Au (gold) (all metal materials capable of forming an ALD are included in addition to the described metal materials), or may be formed of doped polysilicon, and a plurality of word lines within the channel layers 321 and 331 It may be formed to extend over an inner region (a region from the GSL to the plurality of word lines 310 ) corresponding to the word lines 310 . However, the present invention is not limited thereto, and as shown in FIG. 4A , the channel layers 321 and 331 may be formed to extend over the corresponding inner region from the GSL to the SSL.

In addition, the back gates 323 and 333 pass through the substrate 305 on which the plurality of strings 320 and 330 are extended, and are substrates for the back gates 323 and 333 positioned below the substrate 305 . It may be formed extending up to 315 . That is, the 3D flash memory 300 including the back gates 323 and 333 may have a double substrate structure.

In the double-substrate structure, the lower substrate 315 may be used for heat dissipation of the plurality of strings 320 and 330 . As the heat dissipation path of the plurality of strings 320 and 330 is located on the substrate 315 that is distinct from the substrate 305 on which the plurality of strings 320 and 330 are extended, the plurality of strings 320 , 330 may be formed on the substrate 305 on which the plurality of strings 320 and 330 are extended, so that the problem that the cell transistor is affected can be solved.

However, the present invention is not limited thereto, and the 3D flash memory 300 including the back gates 323 and 333 may have a single substrate structure as shown in FIGS. 4B to 4D . In this case, the back gates 323 and 333 are connected to the plurality of word lines 310 in the channel layers 321 and 331 on the substrate 305 on which the plurality of strings 320 and 330 are extended as shown in FIG. 4B . The channel layer 321 on the substrate 305 is formed to extend over a corresponding inner region (the region from the GSL to the plurality of word lines 310 ) or where the plurality of strings 320 and 330 are formed to extend as shown in FIG. 4C . , 331) may be formed extending over the corresponding inner region from GSL to SSL.

In addition, the 3D flash memory 300 including the back gates 323 and 333 includes a substrate 305 on which a plurality of word lines 310 are stacked and a plurality of strings 320 and 330 extend in one direction. ) may further include a back gate plate 325 disposed in a horizontal direction between the substrate 305 and the plurality of word lines 310 . While the back gate plate 325 is formed of the same material as the back gates 323 and 333 , the film stress of the plurality of word lines 310 between the plurality of word lines 310 and the substrate 305 is applied. (Film Stress) may serve to prevent warpage of the substrate 305 . In this structure, the back gates 323 and 333 may be formed to extend to the back gate plate 325 .

In both the single-substrate structure and the double-substrate structure, the upper surface of the substrates 305 and 315 connected to the back gates 323 and 333 are for voltages applied to the back gates 323 and 333 as shown in FIGS. 4A, 4B and 4D. A wiring 340 may be formed. However, the drawings are not limited thereto, and the wiring 340 for the voltage applied to the back gates 323 and 333 may be formed on the lower surface of the substrates 305 and 315 connected to the back gates 323 and 333 . (not shown).

A voltage for the operation of the 3D flash memory 300 may be applied to the back gates 323 and 333 . For example, a pass voltage for forming a channel in the channel layers 321 and 331 or boosting the channel layers 321 and 331 may be applied to the back gates 323 and 333 during a program operation. A program enhancement voltage for increasing threshold voltages of memory cells may be applied to improve a program speed in a program operation, and an erase voltage may be applied to the memory cells during an erase operation. For a detailed description related to the application of a pass voltage for forming channels in the channel layers 321 and 331 or boosting the channel layers 321 and 331 during a program operation to the back gates 323 and 333, refer to FIGS. 6 to 7 . Hereinafter, a detailed description related to application of a program enhancement voltage for increasing the threshold voltage of memory cells during a read operation to the back gates 323 and 333 will be described with reference to FIG. 10 , and the back gate 323 . , 333), a detailed description related to the application of the erase voltage to the memory cells during the erase operation will be described with reference to FIG. 11 .

As another example, a program enhancement voltage for forming an inversion in the channel layers 321 and 331 and improving a program speed may be applied to the back gates 323 and 333 during a program operation, and during an erase operation, the back gates 323 and 333 may be applied. A voltage for performing the erase operation in two steps may be applied. 8 to 9 for a detailed description related to forming an inversion in the channel layers 321 and 331 and applying a program enhancement voltage to improve a program speed during a program operation to the back gates 323 and 333 Accordingly, a detailed description related to applying a voltage for performing the erase operation in two steps during the erase operation to the back gates 323 and 333 will be described with reference to FIGS. 12 to 13 .

In addition, the back gates 323 and 333 are utilized in the process of initially adjusting the threshold voltages of memory cells in units of blocks in which the plurality of strings 320 and 330 are grouped, so that read, program, and erase operations are performed in block units. It can be performed without being affected by the structural deviation of the string. For example, the 3D flash memory 300 compensates for the initial threshold voltage of the memory cells for each block by applying a fine adjustment voltage through the back gates 323 and 333 in consideration of the structural deviation of the block unit string, so that all of the memory cells are similar or similar. can be adjusted in the same way. As a more specific example, by applying a voltage of -0.2V to the back gate of the string included in block A and applying a voltage of -0.1V to the back gate of the string included in block B, The initial threshold voltage of the memory cells and the initial threshold voltage of the memory cells of the string included in the block B may be set to be the same. In the above, the back gates 323 and 333 have been described as having a structure in which the strings 320 and 330 are grouped and electrically separated in units of blocks so that different voltages are applied in units of blocks, but the present invention is not limited thereto. Reference numerals 323 and 333 may have a structure in which each string is electrically separated so as to compensate and adjust an initial threshold voltage for each string unit by applying different voltages for each string unit.

The insulating layers 324 and 334 may be formed of an insulating material to prevent the back gates 323 and 333 from directly contacting the channel layers 321 and 331 , and in particular, a structure for preventing leakage current in the GSL. can have For example, among the insulating layers 324 and 334 , the region 312 corresponding to the GSL disposed at the lower end of the plurality of word lines 310 is formed in the remaining region 312 to prevent leakage current in the GSL as shown in FIGS. 5A to 5B . It may be formed to a thickness thicker than the region.

The memory operation to be described below is assumed to be performed by the three-dimensional flash memory having the structure described with reference to FIGS. 3A to 3B, and the three-dimensional flash having the structure described with reference to FIGS. 4A, 4D, and 5A to 5B. The same can be done in memory.

6 is a flowchart illustrating a program operation of a 3D flash memory according to an exemplary embodiment, and FIG. 7 is a Y-Z cross-sectional view illustrating a program operation of the 3D flash memory according to an exemplary embodiment. A program operation to be described below is based on a method in which a pass voltage for forming a channel in a channel layer or boosting a channel is applied to a back gate.

Referring to FIG. 6 , in step S610 , the 3D flash memory applies a pass voltage for forming a channel in the channel layers 731 and 741 or boosting the channel layers 731 and 741 to the back gates 710 and 720 . can be authorized

In more detail, in step S610, the 3D flash memory performs the selected string 730 corresponding to the target memory cell 750 that is the target of the program operation among the plurality of strings, as shown in FIG. 7 . A ground voltage (0V) is applied to the bit line of 730, a power voltage (Vcc; for example, 3.3V) is applied to the SSL, and a ground voltage (0V) is applied to the GSL, and then a target memory cell among the plurality of word lines The program voltage Vpgm is applied to the word line corresponding to 750 and the word lines corresponding to the remaining memory cells excluding the target memory cell 750 among the plurality of word lines are floated, and at the same time, the back gate 710 is applied to the back gate 710 . A pass voltage (eg, 6V) may be applied.

Here, the value of the pass voltage applied to the back gates 710 and 720 may be determined according to the thickness of the insulating layers 711 and 721 surrounding the back gates 710 and 720 . For example, when the thickness of the insulating layers 711 and 721 is 5 nm, the pass voltage applied to the back gates 710 and 720 may be determined to be 3 to 4 V, and when the thickness of the insulating layers 711 and 721 is 10 nm The value of the pass voltage applied to the back gates 710 and 720 may be determined to be 5 to 10 V. When the thickness of the insulating layers 711 and 721 is 10 nm, the value of the pass voltage applied to the back gates 710 and 720 is It may be determined to be 7 to 15V.

At this time, in step S610 , the 3D flash memory performs the bit of the unselected string 740 with respect to the unselected string 740 that does not correspond to the target memory cell 750 among the plurality of strings as shown in FIG. 7 . The SSL of the unselected string 740 is shut off by applying a power supply voltage (Vcc; for example, 3.3V) to the line and a power supply voltage (Vcc; for example, 3.3V) to the SSL of the unselected string 740 . off) to float the unselected string 740 . Similarly, a ground voltage 0V is applied to the GSL of the unselected string 740 , a program voltage Vpgm is applied to a word line corresponding to the target memory cell 750 among a plurality of word lines, and a plurality of word lines Among them, word lines corresponding to the remaining memory cells excluding the target memory cell 750 may be floated. In addition, the back gate 720 of the unselected string 740 and the back gate 710 of the selected string 730 are connected to each other by a common wiring, and the back gate 720 of the unselected string 740 is connected to the selected string. The same pass voltage (eg, 6V) as the back gate 710 of the string 730 may be applied.

Subsequently, in step S620 , in the 3D flash memory, a ground voltage is applied to a bit line of the selected string 730 , and a program voltage is applied to a word line corresponding to the target memory cell 750 among a plurality of word lines. The channel included in the selected string 730 as the pass voltage is applied to the back gate 710 and word lines corresponding to the remaining memory cells excluding the target memory cell 750 are floated among the plurality of word lines. A channel for a program operation on the target memory cell 750 may be formed in the layer 731 .

After that, in step S630 , in the manufacturing system, a power voltage is applied to the bit line of the unselected string 740 and a power voltage is applied to the SSL of the unselected string 740 , so that the unselected string 740 itself floats. At the same time, as the pass voltage is applied to the back gate 720 , the channel layer 741 included in the unselected string 740 is boosted, and the unselected string 740 by the program voltage for the target memory cell 750 is applied. ), it is possible to prevent the memory cells included in the program from being programmed.

As the program operation is performed through these steps S610 and S620 , a pass voltage may not be applied to word lines corresponding to the remaining memory cells except for the target memory cell 750 , which is the target memory cell 750 . ), it is possible to prevent a disturbance phenomenon due to the pass voltage being applied to the word lines corresponding to the remaining memory cells. Accordingly, the program operation characteristics are improved, so that the cell characteristics and reliability can also be improved, and the channel layer 731 of the selected string 730 forms a channel can be improved.

In addition, since the program operation is performed through steps S610 and S630 , the pass voltage is not applied to the word lines corresponding to the remaining memory cells except for the target memory cell 750 , so that the remaining memory in the target memory cell 750 is not applied. A disturbance phenomenon due to the application of a pass voltage to word lines corresponding to cells may be prevented, and a boosting speed of the channel layer 741 of the unselected string 740 may be improved.

In this case, leakage current in the GSL of the unselected string 740 may be suppressed by forming the insulating layer 721 of the unselected string 740 to be thicker than other regions. Alternatively, in the channel layer 741 of the unselected string 740 , a structure in which B (boron) is further added to the region corresponding to the GSL to increase the threshold voltage of the region is applied, so that the GSL of the unselected string 740 is The leakage current in

Also, since the pass voltage is applied to the word lines that do not correspond to the target memory cell in the conventional unselected string, channel boosting of word lines not corresponding to the target memory cell and channel boosting of the word line corresponding to the target memory cell are conventionally applied. Although there is a problem in that the step difference between them sharply increases, the program operation through the described steps S610 and S630 can boost the entire channel layer 741 of the unselected string 740 at the same time. By improving the channel potential of the layer 741, the field-profile in the channel may have a gentle slope around the position of the word line corresponding to the target memory cell.

As described above, the program operation is performed based on a method in which the pass voltage for forming or boosting channels in the channel layers 731 and 741 is applied through the back gates 710 and 720 instead of being applied through the word line. However, the present invention is not limited thereto, and the program operation is performed on the premise that a pass voltage for forming or boosting channels in the channel layers 731 and 741 is applied through a word line, and a separate voltage is applied to the back gates 710 and 720 . This can be performed further using the approved method. A detailed description thereof will be described with reference to FIGS. 8 and 9 below.

8 is a flowchart illustrating a program operation of a 3D flash memory according to another exemplary embodiment, and FIG. 9 is a Y-Z cross-sectional view illustrating a program operation of a 3D flash memory according to another exemplary embodiment. A program operation to be described below is based on a method in which a program enhancement voltage for forming an inversion in a channel layer and improving a program speed of a target memory cell is applied to the back gate in the program operation.

Referring to FIG. 8 , in step S810 , the 3D flash memory applies a program enhancement voltage for improving the program speed of the target memory cell 930 that is the target of the program operation to the back gates 910 and 920 . can

In more detail, in step S810 , the 3D flash memory applies a program enhancement voltage to the back gate 910 of the selected string 940 corresponding to the target memory cell 930 among the plurality of strings as shown in FIG. 9 . can do. Since the back gate 920 of the unselected string 950 and the back gate 910 of the selected string 940 are connected to each other by a common wiring, the back gate 920 of the unselected string 950 is also connected to the selected string ( The same program enhancement voltage as that of the back gate 910 of the 940 may be applied.

Here, the value of the program enhancement voltage applied to the back gates 910 and 920 may be determined according to the thickness of the insulating layers 911 and 921 surrounding the back gates 910 and 920 .

Subsequently, in operation S820 , the 3D flash memory may apply a pass voltage to the remaining word lines except for the word line corresponding to the target memory cell 930 among the plurality of word lines.

Specifically, in operation S820 , the 3D flash memory performs the selected string 940 corresponding to the target memory cell 930 that is the target of the program operation among the plurality of strings, as shown in FIG. 9 . ), a ground voltage (0V) is applied to the bit line, a power supply voltage (Vcc; for example, 3.3V) is applied to the SSL, and a ground voltage (0V) is applied to the GSL, and then the target memory among the plurality of word lines A program voltage Vpgm is applied to a word line corresponding to the cell 930 , and a pass voltage (eg, 5V) is applied to the word lines corresponding to the remaining memory cells except for the target memory cell 930 among the plurality of word lines. can be authorized.

At this time, in step S820 , the 3D flash memory performs the bit of the unselected string 950 as shown in FIG. 9 with respect to the unselected string 950 that does not correspond to the target memory cell 930 among the plurality of strings. A power supply voltage (Vcc; for example, 3.3V) may be applied to the line. Similarly, a power voltage (Vcc; for example, 3.3V) is applied to the SSL of the unselected string 950 , and a ground voltage (0V) is applied to the GSL, and corresponds to the target memory cell 930 among the plurality of word lines. A program voltage Vpgm may be applied to a word line to be used, and a pass voltage (eg, 5V) may be applied to word lines corresponding to the remaining memory cells except for the target memory cell 930 among the plurality of word lines.

Thereafter, in operation S830 , as the program enhancement voltage is applied to the back gates 910 and 920 , the manufacturing system may form an inversion in the channel layer 941 included in the selected string 940 .

As the program operation is performed through these steps S810 and S830, a program enhancement voltage is applied to the back gates 910 and 920 to form an inversion in the channel layer 911, based on this, the target memory Since the pass voltage applied to the word lines corresponding to the remaining memory cells excluding the cell 930 may be lowered, a disturbance phenomenon in the target memory cell 930 may be prevented. Accordingly, the program operation characteristic is improved, so that the cell characteristic and reliability can also be improved, and the speed at which the channel layer 941 of the selected string 940 forms a channel can be improved.

10 is a flowchart illustrating a read operation of a 3D flash memory according to an exemplary embodiment.

Referring to FIG. 10 , in operation S1010 , the 3D flash memory may apply a program enhancement voltage to the back gate. Here, the program enhancement voltage is a voltage for improving the speed of a program operation performed subsequent to the read operation, and may be a voltage having a negative value for increasing the threshold voltages of the plurality of memory cells.

That is, step S1010 is a step for the subsequent program operation. After applying the program enhancement voltage to the back gate ( S1010 ), a general read operation may be performed as in step S1020 .

In addition, in step S1010, the 3D flash memory may apply a voltage for a general read operation.

More specifically, the 3D flash memory applies a power voltage to a bit line of a selected string corresponding to a target memory cell to be read operation among a plurality of strings, and corresponds to a target memory cell from among the plurality of word lines The verification voltage Vverify may be applied to a word line to be used, and a pass voltage program operation enhancement voltage may be applied to word lines corresponding to the remaining memory cells except for the target memory cell among the plurality of word lines.

Thereafter, in operation S1020 , in the 3D flash memory, a power voltage is applied to a bit line of the selected string, a verification voltage is applied to a word line corresponding to a target memory cell among a plurality of word lines, and a plurality of word lines are generated. As the pass voltage is applied to the word lines corresponding to the remaining memory cells except for the target memory cell, a read operation may be performed on the selected string.

As described above, as the step S1010 for improving the speed of the program operation subsequent to the read operation is performed, the threshold voltage of the memory cells is increased, so that the program operation speed may be improved.

In addition, as a read operation is performed through steps S1010 and S1020 , the 3D flash memory controls the back gate in units of blocks in which a plurality of strings are grouped, while performing a back gate for an unselected block including unselected strings. A word line corresponding to the remaining memory cells in a target memory cell of the selected string by improving channel boosting by using a gate and improving channel boosting by using a back gate for unselected strings in a selected block including selected strings It is possible to prevent a disturbance phenomenon due to the pass voltage being applied to them. Accordingly, cell characteristics and reliability may be improved.

In addition, as the program enhancement voltage is applied to the back gate in step S1010, the voltage field from the word line to the back gate is evenly distributed, so that unintentional lateral diffusion of electrons can be prevented. For example, in a three-dimensional flash memory having a conventional structure in which a back gate does not exist, lateral diffusion of electrons is generated by a field of a pass voltage applied to a corresponding word line and a field of a pass voltage applied to adjacent word lines. There is a problem that the characteristics are deteriorated. However, in the 3D flash memory according to an embodiment, by applying the program enhancement voltage to the back gate in the above-described step S1010, the voltage field from the word line to the back gate is evenly distributed, so that the electrons are unintentionally lateral diffusion. , and it is possible to solve the problem of deterioration of cell characteristics.

11 is a flowchart illustrating an erase operation of a 3D flash memory according to an exemplary embodiment.

Referring to FIG. 11 , the 3D flash memory may perform a bulk erase method based on the back gate by applying an erase voltage to the memory cells included in a plurality of strings to the back gate in operation S1110. .

Such a back gate-based erase method may facilitate hole movement compared to the bulk erase method, thereby improving the erase operation speed.

12 is a flowchart illustrating an erase operation of a 3D flash memory according to another exemplary embodiment, and FIG. 13 is a Y-Z cross-sectional view illustrating an erase operation of a 3D flash memory according to another exemplary embodiment. An erase operation to be described below is characterized in that voltages for performing an erase operation on the memory cells in two steps (a first step and a second step) are applied to the back gate. For convenience of description, a specific memory cell to be erased in the 3D flash memory is enlarged in FIG. 13 .

Referring to FIG. 12 , in the 3D flash memory in step S1210 , in the first step of the erase operation as shown in 1310 of FIG. 13 , a plurality of word lines are floated and an erase voltage (eg, 10V) is applied to the channel bulk. Accordingly, a ground voltage (eg, 0V) for hole generation may be applied to the back gate. Accordingly, a hole may be generated and the channel layer may form a channel.

Thereafter, in the 3D flash memory in step S1220 , in the second step of the erase operation as shown in 1320 of FIG. 13 , a ground voltage is applied to the plurality of word lines and an erase voltage (eg, 10V) is applied to the channel bulk. As applied, the back gate may float for hole injection. Accordingly, holes may be injected into the charge storage layer.

Hereinafter, a method of manufacturing a 3D flash memory to be described is assuming that it is performed by an automated and mechanized manufacturing system, and refers to a method for manufacturing a 3D flash memory described above with reference to FIGS. 3A to 3B, but is limited or limited thereto. It is also applicable to a method of manufacturing a three-dimensional flash memory having the structure described with reference to FIGS. 4A to 4D and 5A to 5B.

In addition, in the drawings for a method of manufacturing a 3D flash memory to be described below, a plurality of strings are shown as one string for convenience of description.

14 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment, and FIGS. 15A to 15D are YZ cross-sectional views illustrating a first implementation example of the manufacturing method of the 3D flash memory shown in FIG. 14 . , and FIGS. 16A to 16B are YZ cross-sectional views for explaining a second implementation example of the manufacturing method of the 3D flash memory shown in FIG. 14 .

Referring to FIG. 14 , in operation S1410 , the manufacturing system may prepare a semiconductor structure.

For example, in the manufacturing system, as shown in FIG. 15A , a plurality of word lines 1520 are formed extending in a horizontal direction on a substrate 1510 and sequentially stacked, and a plurality of word lines 1520 alternately stacked between the plurality of word lines 1520 . A plurality of strings 1540 extending in one direction (eg, Z direction) on the substrate 1510 through the insulating layers 1530 , the plurality of insulating layers 1530 , and the plurality of word lines 1520 . ) It is possible to prepare a semiconductor structure comprising a.

At this time, in the semiconductor structure, each of the plurality of strings 1540 extends in one direction (eg, Z direction) and surrounds the channel layer 1541 and the channel layer 1541 in one direction (eg, Z direction). It may include a charge storage layer 1542 that is formed to extend to, and a hole 1543 may be formed to extend in one direction (eg, Z direction) inside the channel layer 1541 .

In addition, the semiconductor structure may further include a substrate 1515 for a back gate 1560 positioned below the substrate 1510 on which the plurality of strings 1540 are formed to extend. Accordingly, the hole 1543 in the channel layer 1541 is formed to extend to the substrate 1515 for the back gate 1560 while passing through the substrate 1510 on which the plurality of strings 1540 are formed to extend. there may be

Subsequently, in operation S1420 , the manufacturing system may extend the insulating layer 1550 including the inner hole 1551 in the hole 1543 in one direction as shown in FIG. 15B .

Next, in operation S1430 , the manufacturing system may extend the back gate 1560 in one direction using a conductive material or doped polysilicon in the inner hole 1551 of the insulating layer 1550 . Here, the back gate 1560 may be a component for forming a channel in the channel layer 1541 or applying a pass voltage for boosting the channel layer 1541 .

In step S1430, the back gate 1560 may be formed to extend from the inside of the channel layer 1541 to the area of the plurality of word lines 1520 under the SSL as shown in FIG. 15C, but is not limited thereto. As shown in FIG. 15D , it may be formed to extend from the inside of the channel layer 1541 to the SSL region.

Although not shown as a separate step in FIG. 14 , the manufacturing system may form a drain region on the plurality of strings 1540 after step S1430 .

As described above, the method of manufacturing a three-dimensional flash memory according to an embodiment uses a semiconductor structure in which a hole 1543 is formed to extend inside the channel layer 1541, and the semiconductor structure used is previously prepared as shown in FIGS. can be manufactured. For example, the manufacturing system may prepare the semiconductor structure in the above-described step ( S1410 ) by sequentially stacking the prepared lower semiconductor structure and the upper semiconductor structure as shown in FIG. 16A as shown in FIG. 16B .

17 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment, and FIGS. 18A to 18K are YZ cross-sectional views illustrating an example implementation of the method of manufacturing the 3D flash memory shown in FIG. 17 . .

Referring to FIG. 17 , in operation S1710 , the manufacturing system may prepare a semiconductor structure.

For example, in the manufacturing system, as shown in FIG. 18A , a plurality of word lines 1820 are formed extending in a horizontal direction on a substrate 1810 and sequentially stacked, and a plurality of word lines 1820 alternately stacked between the plurality of word lines 1820 . A plurality of strings 1840 extending in one direction (eg, Z direction) on the substrate 1810 through the insulating layers 1830 , the plurality of insulating layers 1830 , and the plurality of word lines 1820 of the ) It is possible to prepare a semiconductor structure comprising a.

In this case, in the semiconductor structure, each of the plurality of strings 1840 extends in one direction (eg, Z direction) and surrounds the channel layer 1841 and the channel layer 1841 in one direction (eg, Z direction). It may include a charge storage layer 1842 that is formed to extend to , and a hole 1843 may be formed to extend in one direction (eg, Z direction) in the channel layer 1841 .

In particular, a first insulating film 1844 may be formed in the region 1843 - 1 corresponding to the GSL among the inner walls of the hole 1843 , and further, the region corresponding to the GSL among the region of the channel layer 1841 is shown in FIG. 18b, it may have a larger cross-section than the rest of the region. Hereinafter, the manufacturing method of the 3D flash memory will be described as manufacturing the 3D flash memory having a structure in which the region corresponding to the GSL among the regions of the channel layer 1841 has a larger cross-section than the remaining regions.

Such a semiconductor structure may be prepared through the process shown in FIGS. 18C to 18I .

In addition, the semiconductor structure may further include a substrate 1815 for a back gate 1860 positioned under the substrate 1810 on which the plurality of strings 1840 are extended. Accordingly, the hole 1843 in the channel layer 1841 is formed to extend to the substrate 1815 for the back gate 1860 while passing through the substrate 1810 on which the plurality of strings 1840 are extended. there may be

Subsequently, in operation S1720 , the manufacturing system may extend the second insulating layer 1850 including the inner hole 1851 in the hole 1843 in one direction as shown in FIG. 18J .

After that, in step S1730, the manufacturing system may extend the back gate 1860 in one direction with a conductive material or doped polysilicon in the inner hole 1851 of the second insulating layer 1850 as shown in FIG. 18K. can Here, the back gate 1860 may be a component for forming a channel in the channel layer 1841 or to which a pass voltage for boosting the channel layer 1841 is applied.

Although it has been described that the back gate 1860 extends from the inside of the channel layer 1841 to the area of the plurality of word lines 1820 under the SSL in the step S1730 above, it is not limited thereto and is not limited thereto. As shown, it may be formed to extend from the inside of the channel layer 1841 to the area of SSL.

In addition, a drain region may be formed on the plurality of strings 1840 in operation S1730 .

As such, the method of manufacturing a 3D flash memory according to another embodiment is a method for manufacturing a structure in which a region corresponding to GSL among regions of an insulating film has a thicker thickness than other regions, and a semiconductor structure (more than Precisely, the semiconductor structure in step S1710) may be prepared through the same process as in FIGS. 18C to 18J .

19 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment, and FIGS. 20A to 20D are YZ cross-sectional views illustrating an example implementation of the method of manufacturing the 3D flash memory shown in FIG. 19 . am.

Referring to FIG. 19 , in operation S1910 , the manufacturing system may prepare a semiconductor structure.

For example, in the manufacturing system, as shown in FIG. 20A , a plurality of sacrificial layers 2020 are formed extending in a horizontal direction on the substrate 2010 and sequentially stacked, and a plurality of sacrificial layers 2020 are alternately stacked between the plurality of sacrificial layers 2020 . A plurality of strings 2040 extending in one direction (eg, Z direction) on the substrate 2010 through the insulating layers 2030 , the plurality of insulating layers 2030 , and the plurality of sacrificial layers 2020 of ) It is possible to prepare a semiconductor structure comprising a.

At this time, in the semiconductor structure, each of the plurality of strings 2040 extends in one direction (eg, Z direction) and surrounds the channel layer 2041 and the channel layer 2041 in one direction (eg, Z direction). It may include a charge storage layer 2042 that is formed to extend to, and a hole 2043 may be formed to extend in one direction (eg, Z direction) in the channel layer 2041 .

Also, the semiconductor structure may further include a substrate 2015 for the back gate 2060 positioned below the substrate 2010 on which the plurality of strings 2040 are formed to extend. Accordingly, the hole 2043 in the channel layer 2041 is formed to extend to the substrate 2015 for the back gate 2060 while penetrating the substrate 2010 on which the plurality of strings 2040 are formed to extend. there may be

Subsequently, in step S1920 , the manufacturing system may form an insulating layer 2050 including an inner hole 2051 in a hole 2043 extending in one direction as shown in FIG. 20B .

Next, in step S1930 , the manufacturing system may remove the plurality of sacrificial layers 2020 as shown in FIG. 20C .

After that, in step S1940, the manufacturing system forms a plurality of word lines 2022 with a conductive material in the space 2021 from which the plurality of sacrificial layers 2020 are removed, as shown in FIG. 20D, and the insulating film 2050 ), the back gate 2060 may be formed to extend in one direction using a conductive material in the inner hole 2051 . In particular, forming a plurality of word lines 2022 using a conductive material in the space 2021 from which the plurality of sacrificial layers 2020 has been removed in step S1940 and conducting the internal hole 2051 of the insulating layer 2050 Forming the back gate 2060 to extend in one direction with a material is characterized in that it is performed simultaneously.

Here, the back gate 2060 may be a component for forming a channel in the channel layer 2041 or applying a pass voltage for boosting the channel layer 2041 .

Although it has been described that the back gate 2060 extends from the inside of the channel layer 2041 to the region of the plurality of word lines 2022 at the bottom of the SSL in step S1940, it is not limited thereto and is not limited thereto. As shown, it may be formed to extend from the inside of the channel layer 2041 to the SSL region.

In addition, a drain region may be formed on the plurality of strings 2040 in operation S1940 .

As such, in the method of manufacturing a 3D flash memory according to another exemplary embodiment, a plurality of word lines 2022 and a back gate 2060 are simultaneously formed, and other processes are described above with reference to FIG. 14 . It may be the same as the manufacturing method of the dimensional flash memory.

21 is a flowchart illustrating a method of manufacturing a 3D flash memory according to another exemplary embodiment, and FIGS. 22A to 22B are YZ cross-sectional views illustrating an example implementation of the method of manufacturing the 3D flash memory shown in FIG. 21 . am.

Referring to FIG. 21 , in operation S2110 , the manufacturing system may prepare a lower semiconductor structure.

For example, in the manufacturing system, as shown in FIG. 22A , the plurality of lower word lines 2220 and the plurality of lower word lines 2220 are alternately stacked and formed to extend in the horizontal direction on the substrate 2210 and sequentially stacked. The plurality of lower insulating layers 2230 , the plurality of lower insulating layers 2230 , and the plurality of lower word lines 2220 are formed to extend in one direction (eg, the Z direction) on the substrate 2210 . A semiconductor structure including the lower strings 2240 of may be prepared.

At this time, in the semiconductor structure, each of the plurality of lower strings 2240 extends in one direction (eg, in the Z direction) and surrounds the lower channel layer 2241 and the lower channel layer 2241 in one direction (eg, in the Z direction). a lower charge storage layer 2242 extending in the Z direction) A lower insulating layer 2244 extending in one direction (eg, Z direction) may be disposed to surround the lower back gate 2243 .

Also, the lower semiconductor structure may further include a substrate 2215 for a lower back gate 2243 positioned under the substrate 2210 on which the plurality of lower strings 2240 are formed to extend. Accordingly, the lower back gate 2243 and the lower insulating layer 2244 inside the lower channel layer 2241 pass through the substrate 2210 on which the plurality of strings 2240 are formed to extend through the lower back gate 2243 . It may be formed to extend to the substrate 2215 for

Subsequently, in operation S2120 , the manufacturing system may prepare an upper semiconductor structure.

For example, in the manufacturing system, as shown in FIG. 22A , a plurality of upper word lines 2250 are sequentially stacked and formed to extend in the horizontal direction, and a plurality of upper insulating layers are alternately stacked between the plurality of upper word lines 2250 . A plurality of upper strings 2270 extending in one direction (eg, Z direction) through the layers 2260 , the plurality of upper insulating layers 2260 , and the plurality of upper word lines 2250 . A semiconductor structure may be prepared.

At this time, in the semiconductor structure, each of the plurality of upper strings 2270 extends in one direction (eg, in the Z direction) and surrounds the upper channel layer 2271 and the upper channel layer 2271 in one direction (eg, in the Z direction). It may include an upper charge storage layer 2272 extending in the Z direction), and particularly, an upper back gate 2273 extending in one direction (eg, Z direction) inside the upper Hannel layer 2271 and An upper insulating layer 2274 extending in one direction (eg, Z direction) may be disposed to surround the upper back gate 2273 .

Thereafter, in step S2130 , the manufacturing system may stack the upper semiconductor structure on top of the lower semiconductor structure so that the cross section of the lower back gate 2243 and the cross section of the upper back gate 2273 match as shown in FIG. 22B . .

As such, the method of manufacturing a 3D flash memory according to another exemplary embodiment may be a method of using semiconductor structures (a lower semiconductor structure and an upper semiconductor structure) in which all of the back gates 2243 and 2273 are formed.

23 is an X-Y plan view illustrating a back gate having an improved structure according to an exemplary embodiment.

Referring to FIG. 23 , the existing structure of the back gate has a disadvantage in that it is difficult to fill the back gate in the internal hole at the current hole size (100 nm) due to the channel layer extending to a high stage.

Accordingly, the back gate according to an exemplary embodiment may be implemented in a form in which the inside of the hole is formed into a slit line in a semicircular or quarter-circle structure, and the back gate is filled therein. In this case, when the inside of the hole has a semi-circular structure, the number of memory cells is doubled, and when the inside of the hole has a quarter-circle structure, the number of memory cells increases to 4 qoi, so that the degree of integration can be improved.

Since it is possible to fill the back gate in such a divided structure, the back gate can have the improved structure described.

24 to 27 are X-Y plan views illustrating a back gate having an improved structure according to another exemplary embodiment.

24 to 27 , the back gate may be implemented in the form of a line crossing the cross section of the channel layer.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (1)

a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and
a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings extending in one direction to surround the channel layer and the channel layer extending in the one direction a charge storage layer formed, wherein the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines;
including,
Inside the channel layer,
and a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate.

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