KR102353421B1 - Three dimensional flash memory for mitigating cell-to cell interference during read operation - Google Patents

Abstract

Disclosed are a three-dimensional flash memory for mitigating inter-cell interference during a read operation, and a method of operating the same. According to an embodiment, a three-dimensional flash memory may include at least one channel layer extending in one direction on a substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and a plurality of memory cells are implemented in regions in contact with the plurality of electrode layers. at least one charge storage layer used as a storage layer, wherein when a read operation is performed on a selected memory cell from among the plurality of memory cells, adjacent to upper and lower portions of the selected memory cell from among unselected memory cells from among the plurality of memory cells Asymmetric pass voltages are respectively applied to unselected adjacent memory cells.

Description

THREE DIMENSIONAL FLASH MEMORY FOR MITIGATING CELL-TO CELL INTERFERENCE DURING READ OPERATION

The following embodiments relate to a three-dimensional flash memory, and more particularly, a technology for a three-dimensional flash memory for mitigating inter-cell interference during a read operation.

A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking insulating layers 242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. For example, in a plan view, the vertical structures 230 may be arranged in a matrix form along the first and second directions. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in a hollow tube shape therein, and in this case, a buried film 228 filling the inside of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating layers 242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the 3D flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and others may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking insulating layers 242 and 243 are the horizontal structures 250 . can be included in However, the present invention is not limited thereto, and the charge storage layer 225 and the tunnel insulating layer 226 defined as the ONO layer may be implemented to be included only in the vertical structures 230 .

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

In the conventional 3D flash memory having such a structure, the threshold voltage of the selected memory cell is an interference phenomenon due _{to the pass voltage V read} applied to the upper and lower non-selected adjacent memory cells during a read operation on the selected memory cell. (V _th ) may be affected.

Accordingly, there is a need for a technique for solving a problem caused by inter-cell interference.

In some embodiments, in order to mitigate inter-cell interference caused by a pass voltage applied to an unselected adjacent memory cell adjacent to upper and lower portions during a read operation for a selected memory cell, a read operation may be performed on a selected memory cell among a plurality of memory cells. At this time, pass voltages different from the pass voltages applied to the remaining unselected memory cells except for the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell among the unselected memory cells of the plurality of memory cells are applied to the unselected adjacent memory cells, respectively. A three-dimensional flash memory to be applied and an operating method thereof are proposed.

According to one side, when a read operation is performed on a selected memory cell among the plurality of memory cells, asymmetric pass voltages are applied to the unselected adjacent memory cells adjacent to upper and lower portions of the selected one of the unselected memory cells from the plurality of memory cells, respectively. A three-dimensional flash memory to be applied and a method for operating the same are proposed.

According to another aspect, when a read operation is performed on a selected memory cell from among the plurality of memory cells, the remaining unselected memory excluding unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell from among the unselected memory cells from among the plurality of memory cells A three-dimensional flash memory and an operating method thereof are proposed in which a pass voltage having a value different from a pass voltage applied to the cells is symmetrically applied to unselected adjacent memory cells, respectively.

According to an embodiment, a three-dimensional flash memory may include at least one channel layer extending in one direction on a substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and a plurality of memory cells are implemented in regions in contact with the plurality of electrode layers. at least one charge storage layer used as a storage layer, wherein when a read operation is performed on a selected memory cell from among the plurality of memory cells, adjacent to upper and lower portions of the selected memory cell from among unselected memory cells from among the plurality of memory cells Asymmetric pass voltages are respectively applied to unselected adjacent memory cells.

According to one side, the 3D flash memory may apply a pass voltage having a higher value than a pass voltage applied to the remaining unselected memory cells excluding the unselected adjacent memory cells among the unselected adjacent memory cells. It may be characterized in that it is applied to one unselected adjacent memory cell, and a pass voltage lower than the pass voltage applied to the remaining unselected memory cells is applied to the other unselected adjacent memory cells among the unselected adjacent memory cells. have.

According to another aspect, the three-dimensional flash memory is configured to reduce an electric field in the one unselected adjacent memory cell or to alleviate a decrease in mobility in the one unselected adjacent memory cell, A pass voltage having a higher value than a pass voltage applied to the remaining memory cells may be applied to any one of the unselected adjacent memory cells.

According to another aspect, in the 3D flash memory, when a pass voltage of a higher value than a pass voltage applied to the remaining unselected memory cells is applied to the one unselected adjacent memory cell, the surface of the channel layer In order to compensate for the increase in electron concentration, a pass voltage lower than a pass voltage applied to the remaining unselected memory cells may be applied to the remaining unselected adjacent memory cells.

According to another aspect, the values of the pass voltage applied to the one unselected adjacent memory cell and the pass voltage applied to the other unselected adjacent memory cell are the values of each of the selected memory cell and the unselected adjacent memory cells. It may be determined based on a threshold voltage of the selected memory cell according to a program state.

According to another embodiment, a three-dimensional flash memory may include at least one channel layer extending in one direction on a substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and a plurality of memory cells are implemented in regions in contact with the plurality of electrode layers. at least one charge storage layer used as a storage layer, wherein when a read operation is performed on a selected memory cell from among the plurality of memory cells, adjacent to upper and lower portions of the selected memory cell from among unselected memory cells from among the plurality of memory cells A pass voltage different from a pass voltage applied to the remaining unselected memory cells except for the unselected adjacent memory cells is symmetrically applied to the unselected adjacent memory cells, respectively.

According to one side, in the 3D flash memory, an electric field in any one of the unselected adjacent memory cells is lowered while mobility in the other unselected adjacent memory cells among the unselected adjacent memory cells is lowered. In order to alleviate this, a pass voltage having a higher value than a pass voltage applied to the remaining unselected memory cells may be symmetrically applied to the unselected adjacent memory cells, respectively.

According to another embodiment, the pass voltage values symmetrically applied to the unselected adjacent memory cells are based on a threshold voltage of the selected memory cell according to a program state of the selected memory cell and each of the unselected adjacent memory cells. It may be characterized in that it is determined.

According to an embodiment, at least one channel layer extending in one direction on the substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and a plurality of memory cells are implemented in regions in contact with the plurality of electrode layers. In the read operation method of a three-dimensional flash memory including at least one charge storage layer used as a storage, when a read operation is performed on a selected memory cell among the plurality of memory cells, the memory cells unselected from the plurality of memory cells are applying asymmetric pass voltages to non-selected adjacent memory cells adjacent to upper and lower portions of the selected memory cell, respectively; and applying a verification voltage to the selected memory cell.

According to one side, the applying each of the asymmetric pass voltages may include applying a pass voltage having a higher value than a pass voltage applied to the remaining unselected memory cells excluding the unselected adjacent memory cells among the unselected memory cells. applying to an unselected adjacent memory cell among adjacent memory cells; and applying a pass voltage lower than the pass voltage applied to the remaining unselected memory cells to the remaining unselected adjacent memory cells among the unselected adjacent memory cells.

According to another aspect, the step of applying a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells to the one unselected adjacent memory cell may include an electric field in the one unselected adjacent memory cell. In order to decrease the value of the memory cell or to alleviate a decrease in mobility in the one unselected adjacent memory cell, a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells is applied to the one unselected adjacent memory cell. It may be characterized in that it is a step of applying to.

According to another aspect, the applying a pass voltage lower than a pass voltage applied to the remaining unselected memory cells to the remaining unselected adjacent memory cells may include a pass voltage applied to the remaining unselected memory cells. In order to compensate for an increase in electron concentration on the surface of the channel layer as the pass voltage of a value is applied to the one unselected adjacent memory cell, a pass voltage having a lower value than the pass voltage applied to the remaining unselected memory cells is applied. It may be characterized in that the step of applying to the remaining non-selected adjacent memory cells.

According to another aspect, the values of the pass voltage applied to the one unselected adjacent memory cell and the pass voltage applied to the other unselected adjacent memory cell are the values of each of the selected memory cell and the unselected adjacent memory cells. It may be determined based on a threshold voltage of the selected memory cell according to a program state.

According to another embodiment, at least one channel layer extending in one direction on the substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and a plurality of memory cells are implemented in regions in contact with the plurality of electrode layers. In the read operation method of a three-dimensional flash memory including at least one charge storage layer used as a storage, when a read operation is performed on a selected memory cell among the plurality of memory cells, the memory cells unselected from the plurality of memory cells are symmetrically applying a pass voltage different from a pass voltage applied to the remaining unselected memory cells excluding the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell to the unselected adjacent memory cells, respectively; and applying a verification voltage to the selected memory cell.

According to one side, the step of symmetrically applying a pass voltage having a value different from the pass voltage applied to the remaining unselected memory cells to the unselected adjacent memory cells may include: In order to reduce the electric field in the adjacent memory cells and at the same time alleviate the deterioration of mobility in the remaining unselected adjacent memory cells among the unselected adjacent memory cells, a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells is applied. It may be characterized in that the step of symmetrically applying each of the non-selected adjacent memory cells.

According to example embodiments, when a read operation is performed on a selected memory cell among the plurality of memory cells, the remaining unselected memory cells excluding the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell from among the unselected memory cells are selected from among the plurality of memory cells. Inter-cell interference caused by the pass voltage applied to the upper and lower adjacent unselected adjacent memory cells during a read operation on the selected memory cell is alleviated by applying pass voltages different from the pass voltage applied to each of the unselected adjacent memory cells. A three-dimensional flash memory and an operating method thereof can be proposed.

According to one side, when a read operation is performed on a selected memory cell among the plurality of memory cells, asymmetric pass voltages are applied to the unselected adjacent memory cells adjacent to upper and lower portions of the selected one of the unselected memory cells from the plurality of memory cells, respectively. A three-dimensional flash memory to be applied and a method of operating the same may be proposed.

According to another aspect, when a read operation is performed on a selected memory cell from among the plurality of memory cells, the remaining unselected memory excluding unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell from among the unselected memory cells from among the plurality of memory cells A three-dimensional flash memory and an operating method thereof for symmetrically applying a pass voltage different from a pass voltage applied to the cells to unselected adjacent memory cells, respectively, may be proposed.

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.
2 is a perspective view showing the structure of a conventional three-dimensional flash memory.
3 is a YZ cross-sectional view illustrating a read operation of a 3D flash memory according to an exemplary embodiment.
4A to 4C are graphs for explaining a read operation of a 3D flash memory according to an exemplary embodiment.
5 is a flowchart illustrating a method of reading a 3D flash memory according to an exemplary embodiment.
6 is a flowchart illustrating a method of reading a 3D flash memory according to another exemplary embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

3 is a Y-Z cross-sectional view illustrating a read operation of a 3D flash memory according to an exemplary embodiment, and FIGS. 4A to 4C are graphs illustrating a read operation of the 3D flash memory according to an exemplary embodiment.

3 and 4A to 4C , the 3D flash memory 300 according to an embodiment includes at least one channel layer 310 , a plurality of electrode layers 320 , and at least one charge storage layer 330 . may include

At least one channel layer 310 is formed to extend in one direction (eg, the Z-axis direction in FIG. 2 ) on a substrate (not shown). In this case, the at least one channel layer 310 may be formed of single crystal silicon or poly-silicon, and a selective epitaxial growth process or phase change using a substrate (not shown) as a seed. It may be formed by an epitaxial process or the like. In addition, the at least one channel layer 310 may be formed in the form of an empty tube inside and further include a buried film (not shown) therein.

Also, although not shown in the drawings, a drain line (not shown) may be connected to the upper portion of the at least one channel layer 310 .

The plurality of electrode layers 320 are stacked in a direction perpendicular to the at least one channel layer 310 and are formed to extend in another direction (eg, the Y-axis direction in FIG. 2 ) orthogonal to one direction. The plurality of electrode layers 320 are conductive materials such as tungsten, titanium, tantalum, etc. to apply a voltage to the plurality of memory cells 331 , 332 , 333 , 334 , 335 implemented by the at least one charge storage layer 330 . It may be formed of a material.

Here, a plurality of insulating layers (not shown) may be interposed between the plurality of electrode layers 320 . Each of the plurality of insulating layers is formed of an insulating material (eg, Al ₂ O ₃ , HfO ₂ , TiO ₂ , La ₂ O ₅ , BaZrO ₃ , Ta ₂ O ₅ , ZrO ₂ , Gd ₂ O ₃ or Y ₂ O ₃ and the same insulating material).

The at least one charge storage layer 330 surrounds the at least one channel layer #10 and is disposed between the at least one channel layer 310 and the plurality of electrode layers 320 in one direction (eg, Z in FIG. 2 ). axial direction), the plurality of memory cells 331 , 332 , 333 , 334 , and 335 are implemented as regions in contact with the plurality of electrode layers 320 to be used as data storage. Hereinafter, to be used as a data storage means that each of the regions of the at least one charge storage layer 330 constituting the plurality of memory cells 331 , 332 , 333 , 334 , and 335 respectively collects and stores charges. It represents the value of data.

For example, the at least one charge storage layer 330 may be formed in an oxide-nitride-oxide (ONO) structure, and the at least one charge storage layer 330 will be described below as including only a vertical element, The present invention is not limited thereto and may further include a horizontal element covering upper and lower portions of the plurality of electrode layers 320 .

In the three-dimensional flash memory 300 having such a structure, during a read operation on the selected memory cell 333 , a ratio adjacent to the upper and lower portions of the selected memory cell 333 among the unselected memory cells 331 , 332 , 334 , and 335 is performed. _{The threshold voltage V th} of the selected memory cell may be affected _{due to interference caused by the pass voltages V read1} and V _read2 applied to the selected adjacent memory cells 332 and 334 , respectively. Hereinafter, the application of the pass voltages V _read1 and V _read2 to the unselected adjacent memory cells 332 and 334 respectively corresponds to the unselected adjacent memory cells 332 and 334 among the plurality of electrode layers 320 . It means that pass voltages V _read1 and V _read2 are applied to the electrode layers, respectively.

Accordingly, the 3D flash memory 300 according to an embodiment solves the interference phenomenon caused by the pass voltages applied to the unselected adjacent memory cells 332 and 334, respectively, in order to solve this problem, It is characterized in that values of pass voltages respectively applied to the selected adjacent memory cells 332 and 334 are adjusted.

In more detail, the 3D flash memory 300 according to an exemplary embodiment performs a read operation on the selected memory cell 333 among the plurality of memory cells 331 , 332 , 333 , 334 , and 335 , when the unselected A selected memory cell is obtained by applying pass voltages _{V read1} and V _read2 having different values from the pass voltage _{V read3} applied to the remaining memory cells 331 and 335 to the unselected adjacent memory cells 332 and 334, respectively. By lowering the electric field in the non-selected adjacent memory cell 332 positioned below the 333 , or by alleviating the decrease in mobility in the unselected adjacent memory cell 333 positioned below the selected memory cell 333 , , it is possible to solve the interference phenomenon from the unselected adjacent memory cells 332 and 334 .

_{In this case, the pass voltages V read1} and V _read2 respectively applied to the unselected adjacent memory cells 332 and 334 may be asymmetrical or symmetrical. Hereinafter, that the pass voltages V _read1 and V _{read2 are asymmetric means the pass voltage V read1} applied to the unselected adjacent memory cell 332 positioned below the selected memory cell 333 and the selected memory cell. _{It means that the pass voltages V read2} applied to the unselected adjacent memory cells 334 positioned above the 333 have different values, and that the pass voltages V _read1 and V _read2 are symmetrical means that _{, the pass voltage V read1} applied to the unselected adjacent memory cell 332 positioned below the selected memory cell 333 and the unselected adjacent memory cell 334 positioned above the selected memory cell 333 It means that the applied pass voltage V _read2 has the same value.

_{First, when pass voltages V read1} and V _read2 applied to the unselected adjacent memory cells 332 and 334, respectively, are asymmetric (when a read operation on the selected memory cell 333 is performed, the unselected adjacent memory _{When asymmetric pass voltages (V read1} , V _read2 ) are respectively applied to the cells 332 and 334 ), the 3D flash memory 300 is applied to the remaining unselected memory cells 331 and 335 . _{A pass voltage V read1} , V _read2 having a higher value than the pass voltage V _read3 is applied to any one of the unselected adjacent memory cells 332 and 334 , and the remaining unselected memory cells ( A pass voltage lower than the pass voltage applied to the 332 and 334 may be applied to the remaining unselected adjacent memory cells among the unselected adjacent memory cells 332 and 334 .

In this case, the pass voltages V _read1 and V _read2 applied to the unselected adjacent memory cells 332 and 334, respectively, are in the program state of the selected memory cell 333 and the unselected adjacent memory cells 332 and 334, respectively. It may be determined based on the threshold voltage of the selected memory cell 333 according to .

For example, as shown in Table 1 below, when the unselected upper adjacent memory cell 334 is in the erase state and the unselected lower adjacent memory cell 332 is in the program state (patterns B and F), the unselected lower adjacent memory cell Since interference due to the electric field in 332 may be largely generated in the selected memory cell 333 , the value of _{the pass voltage V read1} applied to the unselected lower adjacent memory cell 332 is determined by the unselected lower adjacent memory cell 332 . In order to decrease the electric field in the cell 332 , as shown in FIG. 4A , a value 410 higher than _{the pass voltage V read3 applied to the remaining unselected memory cells 331 and 335 may be determined.} In addition, as an example, the channel layer surface according to _{the pass voltage V read1} having a higher value than _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 is applied to the unselected lower adjacent memory cell 332 . In order to compensate for the increase in the electron concentration in , the pass voltage V _read2 applied to the unselected upper adjacent memory cell 334 is the pass voltage V applied to the remaining unselected memory cells 331 and 335 as shown in FIG. 4A . _read3 ) may be determined as a value 420 lower than the value 420 .

division unselected top adjacent memory cell selected memory cell unselected lower adjacent memory cell pattern A erased state erased state erased state pattern B erased state erased state program status pattern C program status erased state erased state pattern D program status erased state program status pattern E erased state program status erased state pattern F erased state program status program status pattern G program status program status erased state pattern H program status program status program status

As another example, as shown in Table 1 above, when the unselected upper adjacent memory cell 334 is in the program state and the unselected lower adjacent memory cell 332 is in the erased state (patterns C and G), the unselected upper adjacent memory cell 332 is in the erase state. Since interference due to reduced mobility in the cell 334 may be greatly generated in the selected memory cell 333 , the value of _{the pass voltage V read2 applied to the unselected upper adjacent memory cell 334 is} In order to alleviate a decrease in mobility in the adjacent memory cell 334 , the pass voltage V _read3 applied to the remaining unselected memory cells 331 and 335 may be determined as a value 430 , as shown in FIG. 4B . In addition, as an example, the channel layer surface as the _{pass voltage V read2} having a higher value than _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 is applied to the unselected upper adjacent memory cell 334 . In order to compensate for the increase in the electron concentration in , the pass voltage V _read1 applied to the unselected lower adjacent memory cell 332 is the pass voltage V applied to the remaining unselected memory cells 331 and 335 as shown in FIG. 4B . _read3 ) may be determined as a lower value 440 .

In the examples described above, any one of the unselected adjacent memory cells 332 and 334 is _{a pass voltage V read1} , V _read2 having a higher value than _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 . is applied to the unselected adjacent memory cells of , and a pass voltage having a lower value than the pass voltage applied to the remaining unselected memory cells 332 and 334 is applied to the remaining unselected adjacent memory cells among the unselected adjacent memory cells 332 and 334. By generalizing to the application method (asymmetric application method), it can be applied to the cases of patterns A and E in Table 1 above, and eventually, the asymmetric application method is the pattern A, B, C, E, G, F may be applicable to all of them.

_{In addition, in the described examples, the difference between the high value of the pass voltage and the pass voltage V read3} applied to any one of the unselected adjacent memory cells 332 and 334 and the unselected adjacent memory cells ( The difference between the _{pass voltage V read3} and the pass voltage V read3 applied to the remaining unselected adjacent memory cells 332 and 334 , ΔV, may be experimentally determined to be 1.5V compared to the _{pass voltage V read3 .} Accordingly, considering that the normal pass voltage V _{read3 is 6V, the value of the pass voltage V read1} applied to the unselected lower adjacent memory cell 332 in FIG. 4A is 7.5V, and the value of the unselected upper adjacent memory is 7.5V. _{The pass voltage V read2} applied to the cell 334 may have a value of 4.5V. Similarly, the value of the pass voltage (V _read1) applied to the lower adjacent memory cell 332 is selected in the non-4b is 4.5V, and the value of the pass voltage (V _read2) is applied to the unselected memory cell adjacent to the upper 334 can be 7.5V

_{Next, when the pass voltages V read1} and V _read2 respectively applied to the unselected adjacent memory cells 332 and 334 are symmetric (when the read operation on the selected memory cell 333 is performed, the unselected remainder _{When the pass voltage V read3} applied to the memory cells 331 and 335 and the pass voltage V _read1 =V _read2 are symmetrically applied to the unselected adjacent memory cells 332 and 334, respectively) In detail, the 3D flash memory 300 applies a pass voltage _{V read1} higher than _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 to the unselected adjacent memory cells 332 , _{334), the pass voltage V read2} is applied to the unselected lower adjacent memory cell 332 , and a pass voltage V read2 having a higher value than _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 is similarly applied to the unselected upper part may be applied to the adjacent memory cell 334 .

Here, the pass voltages V _read1 , V _read2 symmetrically applied to the unselected adjacent memory cells 332 and 334 are program states of the selected memory cell 333 and the unselected adjacent memory cells 332 and 334 , respectively. It may be determined based on the threshold voltage of the selected memory cell 333 according to .

For example, as shown in Table 1 above, when both the unselected upper adjacent memory cell 334 and the unselected lower adjacent memory cell 332 are in the program state, the electric field in the unselected lower adjacent memory cell 332 is Since interference due to reduced mobility in the unselected upper adjacent memory cell 334 can be significantly generated in the selected memory cell 333 while the interference is greatly generated in the selected memory cell 333, the unselected lower adjacent memory cell 332 all values of the pass voltage (V _read2) applied to the value and the unselected upper adjacent memory cell 334 of the pass voltage (V _read1) applied to, the non-electric field at a selected lower adjacent memory cell 332 In order to decrease the value 450 of _{the pass voltage V read3} applied to the remaining unselected memory cells 331 and 335 as shown in FIG. 4C , in order to reduce the reduction in mobility and at the same time alleviate the decrease in mobility in the unselected upper adjacent memory cell 334 , as shown in FIG. 4C . ) can be determined respectively.

Accordingly, the described example may be applicable to the patterns D and H in Table 1 above, and the pass voltages V _read1 and V _read2 and pass voltages respectively applied to the unselected adjacent memory cells 332 and 334 , respectively. _{The difference, ΔV} , of (V _read3 ) may be experimentally determined to be a value of 1.5V compared to the pass voltage (V read3 ). Accordingly, considering that the normal pass voltage V _{read3 is 6V, in FIG. 4C , the value of the pass voltage V read1} applied to the unselected lower adjacent memory cell 332 and the unselected upper adjacent memory cell 334 . A value of the pass voltage V _read2 applied to may be equal to 7.5V.

5 is a flowchart illustrating a method of reading a 3D flash memory according to an exemplary embodiment. Hereinafter, a subject performing the method of reading a 3D flash memory according to an exemplary embodiment may be a 3D flash memory having the structure described with reference to FIGS. 3 to 4C .

In operation S510 , when the 3D flash memory performs a read operation on the selected memory cell among the plurality of memory cells, the unselected adjacent memory cells adjacent to the upper and lower portions of the selected one of the unselected memory cells from the plurality of memory cells Asymmetric pass voltages may be applied to the .

More specifically, in operation S510 , the 3D flash memory applies a pass voltage higher than the pass voltage applied to the remaining unselected memory cells excluding the unselected adjacent memory cells among the unselected adjacent memory cells. After being applied to any one of the unselected adjacent memory cells, a pass voltage lower than the pass voltage applied to the remaining unselected memory cells may be applied to the remaining adjacent memory cells among the unselected adjacent memory cells.

Here, applying a pass voltage higher than the pass voltage applied to the remaining unselected memory cells to any one of the unselected adjacent memory cells may reduce the electric field in any one of the unselected adjacent memory cells or cause any one of them. This may be to mitigate mobility degradation in unselected adjacent memory cells. In addition, when a pass voltage having a lower value than a pass voltage applied to the remaining unselected memory cells is applied to the remaining adjacent memory cells, a pass voltage having a higher value than a pass voltage applied to the remaining unselected memory cells is determined by any one of the unselected memory cells. This may be for compensating for an increase in the electron concentration on the surface of the channel layer that is applied to the adjacent memory cell.

As described above, the values of the pass voltage applied to any one unselected adjacent memory cell and the pass voltage applied to the other unselected adjacent memory cells are the values of the selected memory cell according to the program state of each of the selected memory cell and the unselected adjacent memory cells. It may be determined based on the threshold voltage.

Thereafter, in operation S520 , the 3D flash memory may apply a verification voltage V _verify to the selected memory cell.

6 is a flowchart illustrating a method of reading a 3D flash memory according to another exemplary embodiment. Hereinafter, a subject performing a method of reading a 3D flash memory according to another exemplary embodiment may be a 3D flash memory having the structure described with reference to FIGS. 3 to 4C .

In operation S610 , when the 3D flash memory performs a read operation on the selected memory cell among the plurality of memory cells, the unselected adjacent memory cell adjacent to the upper and lower portions of the selected one of the unselected memory cells from the plurality of memory cells A pass voltage having a value different from a pass voltage applied to the remaining unselected memory cells excluding ? may be symmetrically applied to each of the unselected adjacent memory cells.

In more detail, in operation S610, the 3D flash memory lowers the electric field in any one of the unselected adjacent memory cells while reducing the electric field in the other unselected adjacent memory cells among the unselected adjacent memory cells. In order to alleviate the deterioration of mobility, a pass voltage higher than the pass voltage applied to the remaining unselected memory cells may be symmetrically applied to each of the unselected adjacent memory cells.

As described above, the pass voltage values respectively applied to one unselected adjacent memory cell and the other unselected adjacent memory cells are based on the threshold voltage of the selected memory cell according to the program state of each of the selected memory cell and the unselected adjacent memory cells. can be determined by

Thereafter, in operation S620 , the 3D flash memory may apply a verification voltage V _verify to the selected memory cell.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (15)

at least one channel layer extending in one direction on the substrate;
a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and
A plurality of memory cells are implemented in regions in contact with the plurality of electrode layers while surrounding the at least one channel layer and interposed between the at least one channel layer and the plurality of electrode layers in the one direction to store a data storage at least one charge storage film used as
including,
When a read operation is performed on a selected memory cell among the plurality of memory cells, in order to alleviate an inter-cell interference phenomenon due to a voltage applied to an unselected adjacent memory cell adjacent to upper and lower portions of the selected memory cell, in the plurality of memory cells A three-dimensional flash memory, characterized in that each of the asymmetric pass voltages is applied only to the unselected adjacent memory cells among the unselected memory cells. at least one channel layer extending in one direction on the substrate;
a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and
A plurality of memory cells are implemented in regions in contact with the plurality of electrode layers while surrounding the at least one channel layer and interposed between the at least one channel layer and the plurality of electrode layers in the one direction to store a data storage at least one charge storage film used as
including,
When a read operation is performed on a selected memory cell among the plurality of memory cells, the remaining unselected memory cells excluding the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell among the unselected memory cells of the plurality of memory cells A pass voltage having a higher value than the applied pass voltage is applied to any one of the unselected adjacent memory cells, and a pass voltage lower than the pass voltage applied to the remaining unselected memory cells is applied to the ratio 3D flash memory, characterized in that the application is applied to the remaining non-selected adjacent memory cells among the selected adjacent memory cells. 3. The method of claim 2,
The three-dimensional flash memory,
In order to reduce an electric field in the one unselected adjacent memory cell or to alleviate a decrease in mobility in the one unselected adjacent memory cell, a pass voltage higher than the pass voltage applied to the remaining unselected memory cells is applied. A three-dimensional flash memory, characterized in that the pass voltage is applied to any one of the non-selected adjacent memory cells. 3. The method of claim 2,
The three-dimensional flash memory,
In order to compensate for an increase in electron concentration on the surface of the channel layer when a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells is applied to the one unselected adjacent memory cell, the remaining unselected memory and applying a pass voltage lower than a pass voltage applied to the cells to the remaining unselected adjacent memory cells. 3. The method of claim 2,
Values of the pass voltage applied to the one unselected adjacent memory cell and the pass voltage applied to the remaining unselected adjacent memory cell are:
and the 3D flash memory is determined based on a threshold voltage of the selected memory cell according to a program state of each of the selected memory cell and the non-selected adjacent memory cells. delete at least one channel layer extending in one direction on the substrate;
a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and
A plurality of memory cells are implemented in regions in contact with the plurality of electrode layers while surrounding the at least one channel layer and interposed between the at least one channel layer and the plurality of electrode layers in the one direction to store a data storage at least one charge storage film used as
including,
When a read operation is performed on a selected memory cell among the plurality of memory cells, an electric field in any one of the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell in the plurality of memory cells is applied. In order to reduce the degradation of the memory cells and to alleviate mobility deterioration in the remaining unselected adjacent memory cells among the unselected adjacent memory cells, a pass voltage having a higher value than the pass voltage applied to the remaining unselected adjacent memory cells is applied to the unselected adjacent memory cells. A three-dimensional flash memory, characterized in that each is applied symmetrically. 8. The method of claim 7,
A value of a pass voltage applied symmetrically to each of the unselected adjacent memory cells is,
and the 3D flash memory is determined based on a threshold voltage of the selected memory cell according to a program state of each of the selected memory cell and the non-selected adjacent memory cells. at least one channel layer extending in one direction on the substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and in regions in contact with the plurality of electrode layers to implement data A read operation method of a three-dimensional flash memory including at least one charge storage film used as a storage, the method comprising:
When a read operation is performed on a selected memory cell among the plurality of memory cells, in order to alleviate an inter-cell interference phenomenon due to a voltage applied to an unselected adjacent memory cell adjacent to upper and lower portions of the selected memory cell, in the plurality of memory cells applying asymmetric pass voltages to only the unselected adjacent memory cells among the unselected memory cells, respectively; and
applying a verification voltage to the selected memory cell;
A 3D flash memory read operation method comprising a. at least one channel layer extending in one direction on the substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and in regions in contact with the plurality of electrode layers to implement data A read operation method of a three-dimensional flash memory including at least one charge storage film used as a storage, the method comprising:
When a read operation is performed on a selected memory cell among the plurality of memory cells, asymmetric pass voltages are respectively applied to the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell among the unselected memory cells of the plurality of memory cells to do; and
applying a verification voltage to the selected memory cell;
including,
Applying each of the asymmetric pass voltages comprises:
applying a pass voltage higher than a pass voltage applied to the remaining unselected memory cells excluding the unselected adjacent memory cells among the unselected memory cells to one of the unselected adjacent memory cells ; and
applying a pass voltage lower than the pass voltage applied to the remaining unselected memory cells to the remaining unselected adjacent memory cells among the unselected adjacent memory cells;
A 3D flash memory read operation method comprising a. 11. The method of claim 10,
The step of applying a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells to the one unselected adjacent memory cell includes:
In order to reduce an electric field in the one unselected adjacent memory cell or to alleviate a decrease in mobility in the one unselected adjacent memory cell, a pass voltage higher than the pass voltage applied to the remaining unselected memory cells is applied. and applying a pass voltage to the one unselected adjacent memory cell. 11. The method of claim 10,
The step of applying a pass voltage lower than the pass voltage applied to the remaining unselected memory cells to the remaining unselected adjacent memory cells may include:
In order to compensate for an increase in electron concentration on the surface of the channel layer when a pass voltage having a higher value than the pass voltage applied to the remaining unselected memory cells is applied to the one unselected adjacent memory cell, the remaining unselected memory and applying a pass voltage lower than the pass voltage applied to the cells to the remaining unselected adjacent memory cells. 11. The method of claim 10,
Values of the pass voltage applied to the one unselected adjacent memory cell and the pass voltage applied to the remaining unselected adjacent memory cell are:
The read operation method of the three-dimensional flash memory, characterized in that it is determined based on a threshold voltage of the selected memory cell according to the program state of each of the selected memory cell and the non-selected adjacent memory cells. delete at least one channel layer extending in one direction on the substrate; a plurality of electrode layers stacked in a vertical direction with respect to the at least one channel layer; and a plurality of memory cells surrounding the at least one channel layer and interposed in the one direction between the at least one channel layer and the plurality of electrode layers, and in regions in contact with the plurality of electrode layers to implement data A read operation method of a three-dimensional flash memory including at least one charge storage film used as a storage, the method comprising:
When a read operation is performed on a selected memory cell among the plurality of memory cells, the remaining unselected memory cells excluding the unselected adjacent memory cells adjacent to upper and lower portions of the selected memory cell among the unselected memory cells of the plurality of memory cells symmetrically applying a pass voltage having a value different from the applied pass voltage to the unselected adjacent memory cells, respectively; and
applying a verification voltage to the selected memory cell;
including,
The step of symmetrically applying a pass voltage different from the pass voltage applied to the remaining unselected memory cells to the unselected adjacent memory cells, respectively, includes:
In order to reduce an electric field in any one of the unselected adjacent memory cells and at the same time alleviate a decrease in mobility in the remaining unselected adjacent memory cells of the unselected adjacent memory cells, the remaining unselected memory cells are and symmetrically applying a pass voltage higher than the pass voltage applied to the 3D flash memory to the non-selected adjacent memory cells, respectively.

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