KR20220002218A - Display panel, forming method of pattern thereof and manufacturing appartus for the forming method of pattern thereof - Google Patents

Abstract

A display panel provided in an embodiment of the present invention includes: a circuit board having a transparent support member and a thin film transistor unit on the transparent support member; a plurality of first pads and a plurality of second pads disposed on the upper surface of the circuit board and electrically connected to the thin film transistor unit; and a plurality of LED chips having first electrodes on the first pads and second electrodes on the second pads. Each of the plurality of LED chips is individually driven by the thin film transistor unit to form a subpixel. The circuit board includes: a plurality of upper pads electrically connected to the LED chips on the outside of the upper surface; a plurality of lower pads on the outside of the lower surface; and a plurality of wiring connection units connecting the upper pads to the lower pads, respectively. The wiring connection unit includes: an upper pattern extending from the upper pad to an upper end of a lateral surface of the support member; a lower pattern extending from the lower pad to a lower end of a lateral surface of the supporting member; and a connection pattern formed from the lateral surface of the upper pattern to the lateral surface of the lower pattern. The present invention can minimize a pattern width.

Description

DISPLAY PANEL, FORMING METHOD OF PATTERN THEREOF AND MANUFACTURING APPARTUS FOR THE FORMING METHOD OF PATTERN THEREOF

An embodiment of the invention relates to a light source module having a micro LED, a display panel, and a display device.

An embodiment of the present invention relates to a display panel and a pattern forming method thereof.

An embodiment of the invention relates to a method of forming a flat and three-dimensional (3D) pattern of a wafer or substrate having a thin film transistor unit.

Conventional display devices are mainly composed of a display panel composed of a liquid crystal display (LCD) and a backlight, but recently, a semiconductor device such as a light emitting diode (LED) is used as a pixel as it is. A display device using such an LED is being developed in a form that does not require a separate backlight. In addition, a display device using such an LED can be made compact, and a high-brightness display with superior light efficiency compared to a conventional LCD can be realized. In addition, since the aspect ratio of the display screen can be freely changed and implemented in a large area, various types of large displays can be provided.

In advertisements or screen displays in public places, the demand for large screens is increasing, and LEDs are used as display means for large screens. This is because it is easy to enlarge, consumes less electrical energy, and has a long lifespan with low maintenance cost compared to the conventional display means using a liquid crystal light emitting panel. Recently, large display means using LEDs are used in various places such as TVs, monitors, electric signs for stadiums, outdoor advertisements, indoor advertisements, public signs, and information display boards, and the configuration methods are also various.

An embodiment of the present invention may provide a panel having a connection pattern connecting an upper surface and a lower surface in an outer portion (or an edge) of a wafer or a circuit board, or a method for forming the pattern thereof.

An embodiment of the present invention may provide a panel having a connection pattern for connecting upper and lower pads to each other in an outer portion of a wafer or circuit board having a plurality of light emitting diode chips or a method for forming the pattern thereof.

An embodiment of the present invention may provide a pattern forming method in which a pattern connecting upper and lower pads of a wafer or a circuit board having a plurality of light emitting diode chips to each other is formed by irradiating a laser beam to a metal powder.

An embodiment of the present invention may provide a display panel having a connection pattern between upper and lower edge pads in a wafer or circuit board having a plurality of light emitting diode chips and a thin film transistor unit, and a method for forming the pattern.

A display panel according to an embodiment of the present invention includes: a transparent support member and a circuit board having a thin film transistor on the transparent support member; a plurality of first pads and a plurality of second pads disposed on the upper surface of the circuit board and electrically connected to the thin film transistor; and a plurality of LED chips having a first electrode on the first pad and a second electrode on the second pad, wherein each of the plurality of LED chips is individually driven by the thin film transistor unit to form a subpixel, The circuit board includes a plurality of upper pads electrically connected to the LED chip on the outer side of the upper surface, a plurality of lower pads on the outer side of the lower surface, and a plurality of wiring connections connecting each of the upper pads and each of the lower pads, The wiring connection portion includes an upper pattern extending from the upper pad to an upper end of a side surface of the support member, a lower pattern extending from the lower pad to a lower end of the side surface of the support member, a plane formed from a side surface of the upper pattern to a side surface of the lower pattern; It may include a three-dimensional (3D) connection pattern.

According to an embodiment of the present invention, the upper pattern is formed of the same material as the multi-layer structure of the upper pad, the lower pattern is formed of the same material as the multi-layer structure of the lower pad, and the connection pattern has a single-layer structure. can be formed with

According to an embodiment of the present invention, the connection pattern may be formed of a single or composite metal different from the upper and lower pads.

According to an embodiment of the present invention, the connection pattern may include at least one of a first part extending to an upper surface of the upper pattern and a second part extending to a lower surface of the lower pattern.

According to an embodiment of the invention, at least one of a first step portion and a second step portion on the outer side of the lower surface of the support member are included on the outer side of the support member, and the connection pattern is on at least one of the first and second steps can be formed.

According to an embodiment of the present invention, the width of the connection pattern may be formed to be less than or equal to the width of the upper pattern and the lower pattern, and the thickness of the connection pattern may be formed in a range of 1 μm to 30 μm from the side surface of the support member. .

According to an embodiment of the present invention, a method for forming a pattern for a display panel includes: emitting activated metal powder to a side surface of a circuit board through a metal powder supply unit; and irradiating a laser beam with a laser module toward the metal powder disposed on the side surface of the circuit board, wherein the metal powder irradiated with the laser beam is melted and fused to the side surface of the circuit board to form a connection pattern, , the connection pattern may be adhered to a side surface of the support member, and surfaces of the upper pattern and the lower pattern.

In an embodiment of the present invention, the pads of the upper and lower surfaces of a wafer or circuit board may be connected to each other in a connection pattern using a laser and metallic powder.

In an embodiment of the present invention, a pattern width can be minimized by forming a connection pattern using metal or metallic powder.

In an embodiment of the present invention, a heat treatment process can be reduced by reacting metal or metallic powder with a laser to form a connection pattern on the surface of the wafer or substrate.

The connection pattern according to the embodiment of the present invention may be clearer than the surface wiring, and the adhesion to the circuit board may be improved.

In an embodiment of the present invention, an additional cleaning process may not be required by reacting metal or metallic powder with a laser to form a connection pattern on the surface of the wafer or circuit board.

In an embodiment of the present invention, various metal raw materials can be used by reacting metal or metallic powder with a laser to form a wiring pattern on the surface of the wafer or circuit board.

In addition, an embodiment of the present invention provides an effect of controlling the thickness of the connection pattern and controlling the process time by mixing the metal or metallic powder with the carrier gas.

In addition, in the embodiment of the present invention, it is easy to control the tolerance of the fine line width of the connection pattern, and since a dry raw material is used, the process can be simplified.

In addition, according to the embodiment of the present invention, by using the metal powder, the oxide film on the connection pattern can be removed and the metal purity can be improved. In addition, it is possible to improve the sheet resistance value according to the purity of the metal, there is a dispersion effect by the powder when the connection pattern is formed, and it is possible to prevent crystallization between metals.

In addition, an embodiment of the present invention can transparently deposit a connection pattern that is a wiring formed on a substrate or wafer.

In addition, according to an embodiment of the present invention, the reliability of the display panel can be improved by forming the connection pattern as described above on a substrate or wafer having a plurality of light emitting diode chips and a thin film transistor unit.

1 is a view showing a display device coupled to a display panel having a plurality of LED chips according to an embodiment of the present invention.
2 is a front view illustrating an example of a display panel according to an embodiment of the present invention.
FIG. 3 is an example of a bottom view of the display panel of FIG. 2 .
4 is a view showing an example of a side cross-section of the display panel of FIG. 2 .
5 is a view for explaining an example of the LED chip and the TFT of the circuit board in FIG. 4 .
6 is an example of a partial plan view before the display panel of FIG. 2 is cut.
7 is a diagram illustrating an example of LED chips and an upper pad of the display panel of FIG. 2 .
8A and 8B are an example of an upper pad and connection pattern of the display panel of FIG. 7 and a cross-sectional side view thereof.
9(A)(B)(C) are views for explaining a process of forming a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
10 is a view showing an example in which an insulating layer is formed on the connection pattern on the edge portion of the circuit board in FIGS. 7 and 9 .
11A and 11B are side cross-sectional and plan views illustrating a first modified example of a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
12 is a side cross-sectional view and a plan view illustrating a second modified example of a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
13A and 13B are a plan view and a side cross-sectional view illustrating a third modified example of a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
14 is a plan view illustrating a fourth modified example of a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
15 is a plan view illustrating a fifth modified example of a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
16 is a view for explaining a process of forming a connection pattern on a surface of a wafer or a circuit board according to an embodiment of the present invention.
17 is a view for explaining a process of spraying metal powder when a connection pattern is formed on a surface of a wafer or a circuit board according to an embodiment of the present invention.
18 is a view for explaining a process of forming a connection pattern of a wafer or a circuit board according to an embodiment of the present invention.
19 is a view showing a form of pure graphene extraction through microwave activation in an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated. In interpreting the components, it is construed as including an error range even if there is no separate explicit description. In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used. Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a display device in which a display panel having a plurality of LED chips is combined according to an embodiment of the present invention, and FIG. 2 is a front view showing an example of the display panel of FIG. 1 . 3 is an example of a bottom view of the display panel of FIG. 2, FIG. 4 is a view showing an example of a side cross-section of the display panel of FIG. 2, and FIG. 5 is an example of the TFT of the LED chip and the circuit board in FIG. Figure 6 is an example of a plan view before cutting the display panel of Figure 2, Figure 7 is a view showing an example of the LED chips and upper pad of the display panel of Figure 2, Figure 8 (A) (B) ) is an example of an upper pad and connection pattern of the display panel of FIG. 7 and a cross-sectional side view thereof, and (A) (B) (C) of FIG. 9 is a process of forming a connection pattern of a wafer or circuit board according to an embodiment of the present invention FIG. 10 is a view showing an example in which an insulating layer is formed on the connection pattern on the edge portion of the circuit board in FIGS. 7 and 9 .

1 to 7 , the display device may include one or a plurality of display panels 11 , 12 , 13 , and 14 . The display panels 11 , 12 , 13 , and 14 may be arranged on the same plane, or at least one of the panels 11 , 12 , 13 , and 14 may be arranged on a different plane or tilted. In the display panel 11 , 12 , 13 , and 14 , unit pixels having a plurality of LED chips 2A, 2B, and 2C may be arranged in a matrix form. LED chips 2A, 2B, and 2C may be disposed in each sub-pixel of the unit pixels. The unit pixel may be implemented with LED chips 2A, 2B, and 2C emitting different colors, for example, at least three colors, or a combination of LED chips emitting the same color and sheets such as quantum dots or phosphors. have. The unit pixel may emit red, green, and blue light. For example, the LED chips 2A, 2B, and 2C may include red (R), green (G), and blue (B) LED chips. . For example, the LED chips 2A, 2B, and 2C may include LED chips emitting light of the same color. The size (X3ХY3) of each of the display panels 11, 12, 13, 14 is implemented in a size suitable for various application fields such as a wrist watch, a mobile phone terminal, or a tiling type monitor or TV, or a large TV, a single panel of a billboard, etc. can be For example, the size X3ХY3 of each of the display panels 11, 12, 13, and 14 may be 2 inches or more, but is not limited thereto. The LED chips 2A, 2B, and 2C are chips having a micro size for sub-pixels, and for example, the length of one side may be in the range of 10 μm to 100 μm. The size of the LED chips 2A, 2B, and 2C may be in the range of a micro-size (≤1 μm, or 1 μm-50 μm) with one side length depending on the micro-manufacturing technology of the LED chip. For example, the size of the LED chips 2A, 2B, and 2C may be in the range of 1 μm to 50 μm Х 1 μm to 50 μm, but is not limited thereto.

A boundary portion to which the display panels 2A, 2B, and 2C are coupled may be closely coupled so that they are not separated from the outside. That is, the display panels 2A, 2B, and 2C may have an arrangement structure or a coupling structure in which dark lines are not generated at boundary portions. The size of the display device including the display panels 2A, 2B, and 2C may vary according to the number of combinations of the display panels 2A, 2B, and 2C and the size of each panel. In addition, in the display device, each panel has a structure that can be combined, separated, or removed.

4 and 5, the circuit board 20 of the display panel uses a TFT array substrate capable of driving a plurality of LED chips 2A, 2B, and 2C. That is, the circuit board 20 is formed with a thin film transistor (TFT) unit 50 and various wirings for driving the plurality of LED chips 2A, 2B, and 2C. When the thin film transistor is turned on, the wiring A driving signal input from the outside is applied to the LED chips 2A, 2B, and 2C, and each LED chip emits light to realize an image. The circuit board 20 may include a circuit, for example, a thin film transistor, configured to independently drive sub-pixels, for example, the LED chips 2A, 2B, and 2C, disposed in each pixel region 2 .

In each pixel area 2 of the circuit board 20, at least three LED chips 2A, 2B, and 2C emitting monochromatic light of red, green, and blue are arranged, and the LED is illuminated by a signal applied from the outside. Lights of red, green and blue colors are emitted from the chip to display an image.

The plurality of LED chips 2A, 2B, and 2C may be mounted in a process separate from the TFT array process of the circuit board 20 . That is, the thin film transistor and various wirings disposed on the circuit board 20 are formed by a photo process, but the LED chips 2A, 2B, and 2C may be mounted through a separate bonding process or a reflow process.

Here, the configuration of the circuit board 20 having a thin film transistor and the plurality of LED chips 2A, 2B, and 2C disposed on the circuit board 20 may be defined as a light source module. The circuit board 20 may include a thin film transistor unit 50 connected to the LED chips 2A, 2B, and 2C. The circuit board 20 may be formed of a transparent support member 1 such as glass, and the thin film transistor unit 50 may be disposed on the front surface of the support member 1 . The LED chips 2A, 2B, and 2C may include a light emitting structure that generates light, and first and second electrodes 105 and 106 . The LED chips 2A, 2B, and 2C may include a transparent substrate or a semiconductor substrate. The support member 1 may include at least one of a plastic material, a glass material, a ceramic material, and a metal. The support member 1 may be formed of an insulating film made of a transparent or non-transparent material. The support member 1 and the circuit board 20 may be a flexible substrate or a non-flexible substrate.

5, a light-transmitting cover 7 may be disposed on the circuit board 20 on which the LED chips 2A, 2B, and 2C are disposed, and the light-transmitting cover 7 includes the LED chips 2A, The light emitted from 2B, 2C) may be emitted. The permeable cover 7 may be a glass material or a soft or rigid plastic material, and may be a protective layer or a protective cover. A transparent layer 7A may be disposed between the LED chips 2A, 2B, and 2C and the light-transmitting cover 7, and the transparent layer 7A may include a transparent resin material such as silicone or epoxy, or air It can be a gap.

In the circuit board 20 , the thin film transistor unit 50 includes a gate electrode 51 , a semiconductor layer 53 , a source electrode 55 , and a drain electrode 57 . A gate electrode 51 is formed on the circuit board 20 , a gate insulating layer 49 is formed over the entire area of the circuit board 110 to cover the gate electrode 51 , and a semiconductor layer 53 is formed with the gate It is formed on the insulating layer 49 , and a source electrode 55 and a drain electrode 57 are formed on the semiconductor layer 53 .

The gate electrode 51 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy or an alloy thereof, and the gate insulating layer 49 is made of an inorganic insulating material such as SiOx or SiNx. It may be made of a single layer made of or a plurality of layers made of SiOx and SiNx. The semiconductor layer 53 may be formed of an amorphous semiconductor such as amorphous silicon, or an oxide semiconductor such as _{Indium Gallium Zinc Oxide (IGZO), TiO2, ZnO, WO 3} or SnO _{2 .} When the semiconductor layer 53 is formed of an oxide semiconductor, the size of the thin film transistor (TFT) may be reduced, driving power may be reduced, and electric mobility may be improved. Of course, in the present invention, the semiconductor layer of the thin film transistor is not limited to a specific material, and all kinds of semiconductor materials currently used in the thin film transistor may be used.

The source electrode 55 and the drain electrode 57 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, Al alloy, or an alloy thereof. In this case, the drain electrode 57 may be used as a first connection electrode for applying a signal to the LED chips 2A, 2B, and 2C. On the other hand, in the drawing, the thin film transistor unit 50 is a bottom gate type thin film transistor, but the present invention is not limited to a thin film transistor having such a specific structure, but various structures such as a top gate type thin film transistor. A thin film transistor may be applied.

5 , the second connection electrode 59 is formed on the first insulating layer 41 of the display area A1 . At this time, the second connection electrode 59 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al or Al alloy or an alloy thereof, and the second connection electrode 59 (ie, a thin film transistor ( It can be formed by the same process as the drain electrode 57) of the TFT).

A first insulating layer 41 is formed on the circuit board 20 on which the thin film transistor unit 50 is formed, and LED chips 2A, 2B, and 2C are disposed on the first insulating layer 41 of the display area. In this case, in the drawing, a portion of the first insulating layer 114 is removed and the LED chips 2A, 2B, and 2C may be arranged on the removed area. The first insulating layer 41 may be formed of an organic layer such as a polyimide (PI) film or photoacrylic, or may have a multilayer structure such as an inorganic layer/organic layer or an inorganic layer/organic layer/inorganic layer.

First and second pads 61 and 63 may be disposed in the area where the first insulating layer 41 is opened. The first pad 61 may be disposed on the first connection electrode 57 or may be a part of the material of the first connection electrode 57 . The second pad 63 may be disposed on the second connection electrode 59 , or may be a part of the second connection electrode 59 .

The first electrode 105 of the LED chips 2A, 2B, and 2C is disposed on the first pad 61 of the circuit board 20 , and the second electrode 106 is the second pad 63 . may be placed on the The first and second pads 61 and 63 are electrically connected to the thin film transistor through the first and second connection electrodes 57 and 59, and the first and second pads of the LED chips 2A, 2B and 2C It may be electrically connected to the second electrodes 105 and 106 . Here, the first and second pads 61 and 63 may not include a non-metallic material. The first and second pads 61 and 63 may include at least two or more of Ti, Ni, Pt, TiN, Mo, Al, W, Cu, Ag, and Au. The first and second pads 61 and 63 may be formed in multiple layers.

3 and 4 , a driver IC 19 and a lower pad 32 connected thereto may be disposed on the lower surface of the circuit board 20 . The circuit board 20 includes a wiring connection part 30 in edge areas or non-display areas A2 and A3 of the upper and lower surfaces of the circuit board 20 , and the wiring connection part 30 is electrically connected from the upper surface to the lower surface of the circuit board 20 . can be connected to The wiring connection part 30 may be arranged along at least one side Sc or adjacent regions of two different side surfaces of the circuit board 20 or the support member 1 . The wiring connection part 30 may vary according to the number of pixels, and hundreds or more of wirings may be arranged, for example, at least 100 or 200 or more may be arranged on each side Sc. The wiring connection part 30 may connect the upper pad 31 disposed on the upper surface Sa of the circuit board 20 and the lower pad 32 disposed on the lower surface of the circuit board 20 to each other. 6 and 7 , the upper pads 31 may be electrically connected to the plurality of LED chips 2A, 2B, and 2C through a wiring La, or may be disposed at an end of the wiring La. have. The lower pad 32 may be disposed at a position corresponding to the upper pad 31 on the lower surface Sb of the circuit board 20 . The upper pads 31 and the lower pads 32 may be respectively connected to the plurality of wiring connection units 30 . The upper pad 31 and the lower pad 32 may be single-layered or multi-layered, and in the case of a multi-layered structure, at least two or more layers or three or more layers may be used. The upper pad 31 and the lower pad 32 may include at least two or more of Ti, Ni, Pt, TiN, Mo, Al, W, Cu, Ag, and Au.

An edge region of the circuit board 20 on which the wiring connection part 30 is disposed may be protected by the protective layer 33 . By connecting each of the upper pads 31 and the lower pads 32 to each other through a wiring connection part 30 made of a conductive material on the outer periphery of the circuit board 20, holes passing through the circuit board 20 are formed. do not have to form. The protective layer 33 is formed on the surface of the wiring connection part 30, and may block interference between adjacent connection parts, an electrical short problem, or moisture penetration. The protective layer 33 may be formed up to the surfaces of the upper pad 31 and the lower pad 32 to protect the edge regions of the upper surface Sa and the lower surface Sb. The protective layer 33 may _{include at least one of TiO 2} , SiO ₂ , SiON, and Al ₂ O ₃ , or may be formed of an oxide film, a nitride film, or a dielectric constant film.

2 and 5 , in the pixel region 2, respective LED chips 2A, 2B, and 2C may be disposed on the first and second pads 61 and 63, respectively. The LED chips 2A, 2B, and 2C constituting the pixel region 2 may be arranged in a line shape, a triangular shape, for example, a right triangle shape or an equilateral triangle shape. In this case, each of the first pads 61 may be electrically connected to the common electrode 2D (refer to FIG. 2 ) through a pattern. The first and second pads 61 and 63 are provided with sizes larger than the sizes of the first and second electrodes 105 and 106 of each of the LED chips 2A, 2B, and 2C, so that the LED chips can be easily mounted. can

In an embodiment of the present invention, the material of the pads 61 and 63 electrically connected to the LED chips 2A, 2B, 2C under the LED chips 2A, 2B, and 2C is made of a metal material or a material having a low sheet resistance. can provide The material of the pads 61 and 63 bonded to the respective electrodes 105 and 106 of the LED chips 2A, 2B, and 2C provides a metal bond, so that the surface in the layer connected to the LED chips 2A, 2B, and 2C. It can reduce the resistance value and improve the heat problem.

6 and 4 , some patterns of the upper pad 31 and the lower pad 32 may extend to edges on the upper surface Sa and the lower surface Sb of the circuit board 20 . The partial pattern may extend further outward than the cutting line C1. By extending some of these patterns to the outside of the panel, the edge of the circuit board 20 or the support member 1 may be exposed when cutting through the cutting line C1 . In this case, the unit panel cut by the cutting line C1 requires a member capable of connecting the upper pad 31 and the lower pad 32 to each other. The present invention may include a wiring connection part 30 having some patterns and side patterns of the upper pad 31 and the lower pad 32 on the support member 1 or the circuit board 20 . That is, by forming separate patterns on the side Sc of the cut circuit board 20 , each of the plurality of upper pads 31 and the plurality of lower pads 32 may be connected to each other. The upper pad 31 and the lower pad 32 may be power terminals or signal terminals. The wiring connection part 30 includes an upper pattern P1 disposed on the upper periphery of the support member 1 , a lower pattern P2 disposed on the lower periphery of the support member 1 , the upper pattern P1 and the lower pattern P2 . It may include a connection pattern P3 connecting the . Here, the pattern may be a wiring made of a conductive material having a predetermined width.

Conventionally, when a pattern is formed on the side surface Sc of the circuit board 20 and the upper pad 31 and the lower pad 32 are connected, the pattern is formed using a dispensing process. In addition, in a panel having a thin film transistor unit, when a side pattern is formed using a plating method, electrical damage may occur to the thin film transistor unit during a plating process, so that the plating process cannot be used. Therefore, when the side pattern of the circuit board 20 or the support member 1 is formed using a conventional dispensing process, it is difficult to form a fine pattern. That is, in order to secure a gap between adjacent side patterns, a pattern width of 100 μm or less, for example, 20 μm to 60 μm, is required for the fine pattern. This can be difficult.

In addition, by forming a side pattern by the conventional dispensing process, there is a problem in that the purity of the pattern material is low and the sheet resistance value is increased. In addition, when the side pattern is deposited on the side surface Sc of the circuit board 20 or the support member 1 by dispensing, the adhesive force is low, and a curing process can be performed after deposition.

7 and 8 , the circuit board 20 may include the wiring connection part 30 in at least one or two or more of the plurality of edge regions. The wiring connection part 30 may include an upper pattern P1 , a lower pattern P2 , and a connection pattern P3 . The upper pattern P1 may be a part of the upper pad 31 or may extend from the upper pad 31 to the upper end of the side surface. The lower pattern P2 may be a part of the lower pad 32 or may extend from the lower pad 32 to the lower end of the side surface. The connection pattern P3 may be disposed on the side surface Sc of the circuit board 20 or the support member 1 . The connection pattern P3 may connect outer ends of the upper pad 31 and the lower pad 32 facing each other to each other. For example, the connection pattern P3 may be connected to the upper pattern P1 and the lower pattern P2 . The connection pattern P3 may connect the upper pattern P1 and the lower pattern P2 to each other. Here, the upper pattern P1 and the lower pattern P2 may be formed of the same material as the upper pad 31 and the lower pad 32 .

Here, the materials of the upper pad 31 and the lower pad 32 may be the same or different from each other. When the upper and lower pads 31 and 32 are multi-layered, the lowermost first layer is an adhesive layer and may include at least one of Ti, Ni, TiN, Mo, and Pt or an alloy having the metal. The second layer disposed on the first layer may be formed of a material for heat conduction and electricity conduction, for example, may be formed of an alloy having at least one of Al, Cu, and W or a selected metal. The third layer disposed on the second layer may be made of the same material as the first layer or may be formed of at least one of Ti, Ni, TiN, Mo, and Pt. The fourth layer disposed on the third layer may be a transparent layer or may be formed of a metal bonding layer, for example, may be selected from at least one of ITO, Ag, or Au, or an alloy having the metal. The fourth layer may be a layer for preventing oxidation.

The upper pattern P1 and the lower pattern P2 of the wiring connection part 30 may have the same multi-layer structure as the upper and lower pads 31 and 32 . The connection pattern P3 may be formed from the upper pattern P1 to the lower pattern P2 and may be formed of a conductive material. The connection pattern P3 has a layer structure different from that of the upper pattern P1 and the lower pattern P2 and may be formed of a single metal or a composite metal (eg, an alloy). The connection pattern P3 may include a planar pattern and a three-dimensional (3D) pattern. The connection pattern P3 may have a single-layer structure. The connection pattern P3 may be formed of a material different from that of the upper pad 31 and the lower pad 32 . The connection pattern P3 may have a thickness Ta different from the thicknesses of the lower pad 32 and the lower pad 32 . The thickness Ta of the upper and lower patterns P1 and P2 may be formed to be 1 μm or more, for example, in the range of 1 μm to 100 μm. The thickness Tb of the connection pattern P3 is a distance from the side surface Sc to the outer surface, and may be 1 µm or more, for example, in the range of 1 µm to 40 µm or in the range of 1 µm to 30 µm. The thickness Tb of the connection pattern P3 may vary depending on the sheet resistance value and the size of the metal powder.

As described below, the connection pattern P3 may be formed by irradiating the metal powder with a laser, so that the metal in the form of a flat pattern or/and a three-dimensional pattern may be fused or deposited on the surface on which the metal powder is distributed. At this time, the metal to be deposited or fused is formed by dissolving the metal powder with a laser, so that when the metal powder is dissolved in the oxygen component contained in the metal powder, the adhesion with the surface of the support member 1 or the circuit board 20 is improved. can do it The surface on which the metal pattern is formed may be the surface of the support member 1 of the circuit board 20 and/or the surface of the pad.

The connection pattern P3 may be formed of a conductive material or metal, for example, Ti, Ta, W, Al, Cu, In, Ir, Pd, Co, Gr, CNT, Cr, Mg, Mo, Zn, At least one of Ni, Si, Ge, Ag, Au, Hf, Pt, Ru, Rh, TiN, and TaN or at least one of two or more alloys thereof. For example, the metal of the connection pattern P3 may include Cu having high thermal and electrical conductivity or CuGr, but is not limited thereto.

The height T2 of the connection pattern P3 may be greater than or equal to the thickness T1 of the support member 1 . The height T2 of the connection pattern P3 may be the minimum height, and may be equal to the distance between the upper surface Sa and the lower surface Sb. The minimum height of the connection pattern P3 may be equal to the distance between the upper pattern P1 and the lower pattern P2 .

A width W2 of the connection pattern P3 is a fine line width, and may be greater than a thickness Tb of the connection pattern P3. The width W2 of the connection pattern P3 may be 150 μm or less, for example, in the range of 5 μm to 150 μm, or in the range of 20 μm to 60 μm. The width W2 of the connection pattern P3 may vary depending on the size of the terminal that is the upper pad 31 connected to the LED chip or the size of the terminal connected to the driver below.

The width W2 of the connection pattern P3 may be formed to have a constant width from the upper end to the lower end of the circuit board 20 . As another example, the width W2 of the connection pattern P3 may have a wide upper part and a narrow lower part, or a narrow upper part and a wide lower part may be formed. That is, the plurality of connection patterns P3 may be arranged with the same width at the lower end of the side surface Sc of the support member 1 , or may be arranged with the upper width and lower width different from each other.

The width W2 of the connection pattern P3 may be equal to or smaller than the width W1 of the upper pattern P1. The width W2 of the connection pattern P3 may be equal to or smaller than the width of the lower pattern P2 . Here, when the width W2 of the connection pattern P3 is greater than the widths of the lower pattern P2 and the lower pattern P2 , interference with other adjacent connection patterns P3 may occur, so that the upper and less than the width W1 of the lower pattern P2.

The connection pattern P3 is in contact with the side surface of the upper pattern P1 and the side surface of the lower pattern P2, is spaced apart from the upper surface of the upper pattern P1, and is spaced apart from the lower surface of the lower pattern P2. can An alloy of two different metals may be formed at a contact portion of a side surface of the connection pattern P3 and the upper pattern P1 . An alloy of two different metals may be formed at a contact portion between the side surfaces of the connection pattern P3 and the lower pattern P2 .

In an embodiment of the present invention, the connection pattern P3 of the side surface Sc of the panel, the circuit board 20 or the support member 1 is formed using metal powder, without performing a plating process or a dispensing process. The upper pad 31 and the lower pad 32 may be electrically connected. In addition, by forming the connection pattern P3 having a thin width W2 and a thin thickness Tb, sheet resistance may be lowered, and thus electrical efficiency may be improved. In addition, since the adjustment of the line width of the connection patterns P3 may vary depending on the number of times the laser passes and the size of the powder, it may be easy to control the tolerance between the connection patterns P3 .

A process of forming the connection pattern P3 is as follows.

9(A) (B), after aligning the side surface Sc of the support member 1 of the circuit board 20 to correspond to the laser module 203, the side surface of the upper pattern P1 and The activated metal powder Pm is emitted through the powder supply unit 201 along the side surface Sc of the support member 1 . At this time, the side surface Sc of the support member 1 is a part of the region where the connection pattern P3 is formed, and the metal powder Pm is the side surface of the upper pattern P1 and the side surface Sc of the support member 1 . can be applied accordingly. At this time, while the metal powder Pm is applied, the laser beam L1 is irradiated to the metal powder Pm. Since the laser is irradiated with the metal powder Pm at a temperature of tens of thousands (10000) degrees or more, the metal powder Pm is dissolved and deposited or fused to the side Sc of the support member 1 . . At this time, by forming the metal powder Pm by using the laser beam L1, when the oxygen component contained in the metal powder Pm is dissolved in the metal powder, the adhesive force between the side Sc of the support member 1 and the metal can improve As shown in (B) (C) of Figure 9, when the above-described process is performed, by moving the circuit board 20, the emission of the metal powder Pm and the irradiation process of the laser beam L1 are sequentially performed. can A connection pattern P3 may be formed on the side surface Sc, and the connection pattern P3 may be connected to the upper pattern P1 and the lower pattern P2. By irradiating the laser beam L1 to the region from which the metal powder Pm is emitted, a connection pattern P3 may be formed, so that the metal powder Pm from the upper pattern P1 to the lower pattern P2. may be provided to form the connection pattern P3 . During the pattern forming process, the laser module 203 and the powder supply unit 201 may be moved in one direction, or the circuit board 20 may be moved in the other direction. The width of one laser beam L1 may be 150 μm or less.

By the method of forming the connection pattern P3 described above, the connection pattern P3 may be formed on the upper surface Sa, the side surface Sc, or the lower surface Sb of the support member 1, and the upper pad ( 31) or/and may be formed on the upper pattern P1, or may be formed on the lower pad 32 and/or the lower pattern P2. Accordingly, the connection pattern P3 may be formed on the upper surface of the upper pattern P1 and/or the lower surface of the lower pattern P2 by using the metal powder. Or as another example, when the upper pattern P1 and/or the lower pattern P2 does not extend to the side surface Sc of the support member 1 and is spaced apart from the side edge, the connection pattern P3 is The upper surface Sa of the support member 1 may be formed from the upper surface of the upper pattern P1 and/or the upper pad 31 to the lower surface of the lower pad 32 and/or the lower pattern P2. Accordingly, the connection pattern P3 may be formed on an area in which a pattern or a pad is formed on the upper surface Sa of the support member 1 , or may be formed on an area in which a pattern is not formed. The connection pattern P3 may be formed under an area in which a pattern or a pad is formed on the lower surface Sb of the support member 1 or may be formed under an area in which a pattern is not formed.

10 and 11 (A) , a protective layer 33 may be formed on the surface of the connection pattern P3 and the surfaces of the upper and lower patterns P2 . The protective layer 33 may protect the surface of the wiring connection part 30 and may extend to a region capable of covering the upper and lower pads 31 and 32 if necessary.

11A and 11B , the connection pattern P3 may include at least one or both of the first portion P3a and the second portion P3b. The first portion P3a may extend up to an upper surface of the upper pattern P1 , and the second portion P3b may extend below a lower surface of the lower pattern P2 . The first portion P3a of the connection pattern P3 may be spaced apart from the upper pad 31 (refer to FIG. 7 ) and cover a portion of the upper pattern P1 . When the width of the first portion P3a of the connection pattern P3 is smaller than the width of the upper pattern P1, the first portion P3a of the connection pattern P3 and the upper pattern P1 are partially vertical. direction can be overlapped. Here, at least a portion of the first portion P3a may be in contact with the upper surface Sa of the support member 1 .

The second portion P3b of the connection pattern P3 may be spaced apart from the upper pad 31 and may cover a portion of the lower pattern P2 . When the width of the second portion P3b of the connection pattern P3 is smaller than the width of the lower pattern P2, the second portion P3b and the lower pattern P2 of the connection pattern P3 are partially vertical. direction can be overlapped. Here, at least a portion of the second portion P3b may be in contact with the lower surface Sb of the support member 1 .

Referring to FIG. 12 , the upper pattern P1 of the circuit board 20 is spaced apart from the side surface Sc of the circuit board 20 by a predetermined distance, for example, 10 μm or more. The lower pattern P2 of the circuit board 20 is spaced apart from the side surface Sc of the circuit board 20 by a predetermined distance, for example, 10 μm or more. In this structure, the first portion P3a of the connection pattern P3 may extend from the side surface Sc of the support member 1 to the upper surface Sa, and may be in contact with the side surface of the upper pattern P1 . Alternatively, the first portion P3a may further extend from the side surface Sc of the support member 1 to the upper surface Sa and the upper surface of the upper pattern P1 . The second portion P3b of the connection pattern P3 may extend from the side surface Sc of the support member 1 to the lower surface Sb and may be in contact with the side surface of the upper pattern P1 . Alternatively, the second portion P3b may further extend from the side surface Sc of the support member 1 to the lower surface Sb and the lower surface of the lower pattern P2 . Even if the upper pattern P1 or/and the lower pattern P2 are spaced apart from the side surface Sc of the circuit board 20, the connection pattern P3 is connected to the upper pattern P1 and the lower pattern P2 with the upper pattern P1 and the lower pattern P2. It can be connected through a fusion process using metal powder.

At this time, after the connection pattern P3 is fused to the side surface Sc of the circuit board 20, the fusion process of the first part P3a and the second part P3b is performed on the upper surface Sa or the lower surface Sb. may be performed, and the process sequence may be changed.

Referring to (A) (B) of FIG. 13 , at least one or a plurality of first step portions ST1 may be formed on the upper edge of the circuit board 20 , and/or at least one or plurality of lower edges of the circuit board 20 . of the second step portion ST2 may be formed. Each of the first and second step portions ST1 and ST2 may be concavely formed in a direction extending from the upper pad and the lower pad, respectively.

The depths of the first and second step portions ST1 and ST2 may be 20 times or less, for example, 0.5 to 5 times or less the thickness of the upper and lower patterns P2 . The first and second step portions ST1 and ST2 may be formed in a stepped shape or an inclined surface. An upper pattern P1 may extend to the first stepped portion ST1 , and a lower pattern P2 may extend to the second stepped portion ST2 . The connection pattern P3 may be formed from the side surface of the upper pattern P1 to the side surface of the lower pattern P2 . Alternatively, the first portion P3a of the connection pattern P3 may extend to the upper surface of the upper pattern P1 and overlap the first stepped portion ST1 in a vertical direction. Alternatively, the second portion P3b of the connection pattern P3 may extend to a lower surface of the lower pattern P2 and overlap the second stepped portion ST2 in a vertical direction. By forming the connection pattern P3 on at least one of the first and second step portions ST1 and ST2, the adhesive force of the connection pattern P3 may be improved.

14 , a plurality of connection patterns P3 may be disposed on the side surface Sc of the circuit board 20 to be connected to the upper pattern P1 and the lower pattern P2 . By connecting each side of the upper patterns P1 and the lower patterns P2 with a plurality of connection patterns P3 , electrical reliability may be improved.

15 , a plurality of connection patterns P3 may be disposed on the side surface Sc and the top surface Sa of the circuit board 20 to be connected to the upper pattern P1 and the lower pattern P2 . By connecting the upper pattern P1 and the lower pattern P2 to the side and upper surfaces of each of the plurality of connection patterns P3 , adhesion between the patterns and electrical reliability may be improved. Here, the plurality of connection patterns P3 may be two or more. As another example, in the connection pattern P3 , a single pattern connected to the upper pattern P1 may be formed, and a plurality of patterns connected to the lower pattern P2 may be formed. As another example, in the connection pattern P3 , a plurality of patterns connected to the upper pattern P1 may be plural, and a single pattern connected to the lower pattern P2 may be formed.

As another example of the present invention, a plurality of recesses concave inward than the side surface Sc are disposed on the side surface Sc of the circuit board 20, and the connection pattern P3 is formed in the plurality of recesses. can be In this case, when a via hole is formed in a cutting line and then cut, the recess may be provided, and the connection pattern P3 may be formed in the recess using at least one of the structures described above.

As shown in FIG. 16 , an activated material having metal powder Pm is supplied to the surface of the circuit board 20 through the powder supply unit 201, and at this time, the activated material may be emitted along a preset path or area. have. When the activated material is emitted to the surface of the circuit board 20 , a laser beam L1 from the laser module 203 may be irradiated toward the activated material. In this case, the activated material may be dissolved by the laser and may be fused or deposited on the surface of the circuit board 20 . This process may be performed in a chemical vapor deposition (CVD) equipment, for example, atmospheric pressure chemical vapor deposition (AP-CVD) equipment. By forming the connection pattern P3 on the circuit board 20 through this fusion process, the heat treatment process may be omitted, and may be formed with the same minimum line width as the size of the laser beam L1 . In this case, the width of the connection pattern P3 may be increased by one or more times, for example, one to three times the size of the laser beam by repeating the fusion process using a laser beam. In addition, as the activated metal powder (Pm) is fused, pure metal can be deposited, so that the sheet resistance can be lowered to 50 mΩ or less. P3) can be provided transparently. The laser module 203 may be a module that irradiates a laser beam in three dimensions.

An apparatus and method for forming a pattern according to an embodiment of the present invention will be described with reference to FIGS. 17 and 18 .

Referring to FIG. 17 , the metal powder is supplied by supplying the gas supplied from the gas synthesizing unit 211 and the conductive material powder from the metal powder supplying unit 213 ( S11 ). Such gas and metal powder may be stored in the material storage tank 215 . The gas may include at least one or both of an inert gas and a fluorine gas, for example, N ₂ , Ar, He, CF ₄ , SF ₆ , NH ₃ , CF ₄ /H ₂ , CHF ₃ , C ₂ F ₆ , It may include at least one of H ₂ , C ₂ H ₄ , and CH _{4 and O 2 .} Here, the oxygen content in the gas may be provided in a range of 0.1% or more, for example, 0.1% to 10%. In addition, the selection or content of gas in the gas synthesis unit 211 may be adjusted.

The conductive material powder is a metallic material, for example, Ti, Ta, W, Al, Cu, In, Ir, Pd, Co, CNT, Cr, Mg, Mo, Zn, Ni, Si, Ge, Ag, Au, Hf , Pt, Ru, Rh, TiN, and at least one of TaN or a mixture of two or more may be provided. The size of the powder may be a nano size, such as 1 nm or more, or a range of 1 nm to 5000 nm, a range of 1 nm to 2000 nm, or 100 nm to 500 nm, and may vary depending on the size of the metal particles. The metallic powder may be a pulverized product of a metal oxide, a pulverized product of a metal carbide or a metal nitride, a pulverized product of a metal, or a pulverized product of a mixture having a metal oxide and other additives. Such a pulverized product may be pulverized by a mechanical pulverization method. The content of the powder or the injection material in the metal powder supply unit 213 may be adjusted.

The material storage tank 215 stores the gas and metal powder, and supplies the material having the metal powder to the activator 216 (S12). The activator 216 may receive and store the material having the powder in the activation tank 217 , and may activate the material having the stored metal powder by the microwave device 218 . By activating the metal powder using the microwave device 218 , the activated metal material may be supplied through the powder supply unit 201 ( S13 ). The powder supply unit 201 may emit light on the surface of a predetermined circuit board 20 , and when the activated metal powder Pm is emitted, the laser module 203 sends a laser beam L1 to the corresponding area. is investigated (S14). In this case, the metal powder Pm may be formed into a connection pattern P3 having a predetermined length and width through continuous irradiation of the laser beam L1 .

At this time, the activated metal is provided in a powder form, dissolved by a laser beam, and fused to the surface of the circuit board 20, so that, in the case of a pure metal material, that is, an oxide, nitride, or carbide, a material other than the metal is removed. Metal particles may be dissolved and deposited. That is, the activator 216 may remove the oxide film, the carbonized film, or the nitride film included in the metal powder. Accordingly, the purity of the metal powder may be improved. For example, in the case of a tungsten material, when the oxide is removed, adhesion to the substrate surface may be higher. In addition, in the case of graphene oxide or copper oxide material, when the oxide is removed, graphene or copper material may be fused. For example, as shown in FIG. 19 , a material such as graphene oxide (A) may be provided as reduced graphene (B) using microwaves.

Since the embodiment of the invention is emitted to the surface of the substrate in the form of powder, it can be dispersed in a wider area and there is an effect of reducing the cost. Accordingly, the connection pattern P3 of the metal material deposited on the surface of the substrate has a low sheet resistance of 50 mΩ or less, and surface adhesion may be increased by deposition using a laser. In addition, since the moving speed of the laser beam proceeds at a high temperature (10000 degrees or more) at a speed of 1 meter or more per second, it is possible to form a fine connection pattern by minimizing the raw material particles and the laser beam width. In addition, since the edge portion of the wiring is formed in a pattern of powder by a laser beam, it is clear, and straightness and fixability can be improved. In addition, when the metal powder is emitted and the laser beam is irradiated, the powder that is not fused may be adsorbed by adsorbing it using an adsorption device, so that a separate cleaning process may not be performed. In addition, since the dry powder is fused using a laser, a separate heat treatment process is not required. In addition, it is possible to diversify gas and metal materials, so that the range of material selection can be widened. The thickness or height of the connection pattern P3 may be easily controlled. In addition, it may be easy to adjust the tolerance of the fine connection pattern. In addition, since no coating ink or liquid paste is used, the process can be quickly simplified.

As described above, although described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

In addition, the reference numbers described in the claims of the present invention are provided only for clarity and convenience of explanation, and are not limited thereto, and in the process of describing the embodiment, the thickness of the lines shown in the drawings or the size of components, etc. may be exaggerated for clarity and convenience of explanation, and the above-mentioned terms are terms defined in consideration of functions in the present invention, which may vary depending on the intention or custom of the user or operator, so the interpretation of these terms should be made based on the content throughout this specification.

1: support member
2: Pixel area
2A, 2B, 2C: LED chip
11,12,13,14: display panel
20: circuit board
41: first insulating layer
50: thin film transistor unit
61,63: pad
30: wiring connection
31: upper pad
32: upper pad
33: protective layer
P1: upper pattern
P2: lower pattern
P3: connection pattern

Claims (1)

a circuit board having a transparent support member and a thin film transistor on the transparent support member;
a plurality of first pads and a plurality of second pads disposed on the upper surface of the circuit board and electrically connected to the thin film transistor; and
a plurality of LED chips having the first electrode and the second electrode and electrically connected to the first pad and the second pad;
Each of the plurality of LED chips is individually driven by the thin film transistor unit to form a sub-pixel,
The circuit board is
A plurality of upper pads electrically connected to the LED chip on the outer side of the upper surface, a plurality of lower pads on the outer side of the lower surface, and a plurality of wiring connecting portions connecting each of the upper pads and the lower pad, display panel.

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