KR20210085066A - Display device and driving method thereof - Google Patents

Abstract

A display device and a driving method thereof are disclosed. The display device includes: a first controller for receiving first image information to be displayed on a first screen; a second controller for receiving second image information to be displayed on a second screen; an integrated circuit which is controlled by the controller having a control right among the first and second controllers to generate power and signals necessary for driving the first and second screens; and a communication interface connecting the first controller, the second controller, and the integrated circuit. Therefore, when there is a temporary failure or error in all controllers, a master controller can be restored by resetting the controller set with the master controller and restarting the controllers.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device including a plurality of controller chips and a driving method thereof.

A driving circuit of a flat panel display (FPD) reproduces an input image on a pixel array by writing pixel data of an input image to pixels of a display panel. The driving circuit includes a data driving circuit that supplies a pixel data signal to data lines, a gate driving circuit that supplies a gate signal (or scan signal) to gate lines (or scan lines), and a data driving circuit and a gate driving circuit. and a controller (Timing controller) for controlling operation timing.

The electroluminescent display is roughly classified into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. An active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed and high luminous efficiency, luminance, and viewing angle. There are advantages. In the organic light emitting display device, a light emitting diode element (referred to as "Organic Light Emitting Diode," OLED) is formed in each pixel. The organic light emitting display device has a fast response speed, excellent luminous efficiency, luminance, and viewing angle, as well as a black Since the grayscale can be expressed as complete black, the contrast ratio and color reproduction ratio are excellent.

The organic light emitting display device does not require a backlight unit and can be implemented on a plastic substrate, a thin glass substrate, or a metal substrate, which are flexible materials, which is advantageous for implementing a flexible display.

With the advancement of luxury vehicles, connected cars, and autonomous vehicles, the automotive display market is growing. In-vehicle displays are developing with an increase in screen size and high resolution. To this end, the adoption of a multi-chip including a plurality of controllers in a driving circuit of a vehicle display is being considered.

In-vehicle display manufacturers are facing enhanced fail-safe requirements so that important safety-related information can be displayed in harsh environments such as high temperature and high vibration inside the vehicle.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a display device with enhanced fail-safe function and a driving method thereof.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention converts pixel data of first image information to be displayed on a first screen into a first data voltage using a gamma reference voltage and supplies the converted pixel data to data lines of the first screen. 1 data driver; a second data driver converting pixel data of second image information to be displayed on a second screen into a second data voltage using the gamma reference voltage and supplying it to data lines of the second screen; a first controller that generates a first operation result and transmits the first image information to the first data driver; a second controller that generates a second operation result and transmits the second image information to the second data driver; a first power supply unit for receiving an operation result of the first operation result or the second operation result from any one of the first controller and the second controller having a control right and outputting the gamma reference voltage; and a communication interface connecting the first controller, the second controller, and the first power supply and transmitting the first or second operation result.

When an error occurs in the first operation result received from the communication interface, the control right of the first power unit is transferred to the second controller.

A display device according to another embodiment of the present invention includes: a first controller for receiving first image information to be displayed on a first screen; a second controller for receiving second image information to be displayed on a second screen; an integrated circuit controlled by a controller having a control right among the first and second controllers to generate power and signals necessary for driving the first and second screens; and a communication interface connecting the first controller, the second controller, and the integrated circuit.

The first and second controllers determine whether there is an error in the signal received from the communication interface, and when there is an error in the signal generated from the counterpart controller, the control right of the integrated circuit is transferred from the counterpart controller.

The method of driving the display device may include transmitting first image information to be displayed on a first screen to a first controller, and transmitting second image information to be displayed on a second screen to a second controller; generating, by an integrated circuit controlled by a controller having a control right among the first and second controllers, power and signals necessary for driving the first and second screens; determining, by the first and second controllers, whether there is an error in a signal transmitted through a communication interface connecting the first controller, the second controller, and the integrated circuit; and transferring control right of an integrated circuit of a controller that has transmitted a signal through the communication interface among the first and second controllers to another controller.

The present invention can convert the control right of the integrated circuit of the master controller to the slave controller by using a communication interface connecting the master controller, the slave controller, and the integrated circuit in a situation in which the master controller cannot operate normally.

The present invention can restore the master controller by resetting and restarting the controller set as the master controller when there is a temporary failure or error in all controllers.

According to the present invention, when an abnormal operation is detected in the gate driver, the control right of the gate driver is transferred to the slave controller to restore the gate driver.

According to the present invention, when an error occurs in the master controller that controls the integrated circuit, the control right of the integrated circuit is transferred to the slave controller so that the input image and important information can be displayed on the display panel in any situation.

Accordingly, according to the present invention, a display device having a reinforced fail-safe function can be implemented to automatically recover errors even in a harsh use environment.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.
2 is a diagram schematically showing a pixel circuit of the present invention.
3 and 4 are circuit diagrams illustrating the pixel circuit shown in FIG. 2 in detail.
5 is a view showing transfer of control right to a peripheral integrated circuit according to the first embodiment of the present invention.
6 is a flowchart showing step by step a control procedure of a method for transferring control right to a peripheral integrated circuit according to an embodiment of the present invention.
7 is a view showing transfer of control right to a peripheral integrated circuit according to a second embodiment of the present invention.
8 is a diagram showing transfer of control right to a peripheral integrated circuit according to a third embodiment of the present invention.
9 is a diagram schematically showing a circuit configuration of a shift register in a gate driver.
FIG. 10 is a view showing transistors connected to the first signal transfer unit shown in FIG. 9 .
11 is a waveform diagram illustrating a first control node voltage, a second control node voltage, and an output voltage of the first signal transfer unit illustrated in FIG. 10 .
12 is a waveform diagram showing a shift of a gate signal output from a gate driver.
13 is a flowchart showing step by step a control procedure of the method for controlling important information according to the first embodiment of the present invention.
14A and 14B are diagrams illustrating examples in which a display area of important information is changed due to an error occurring in a controller or a peripheral integrated circuit.
15 is a flowchart showing step by step a control procedure of a method for controlling important information according to a second embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the embodiment description, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The features of the various embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driver may include a plurality of transistors. The transistors may be implemented as an oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPS TFT including a Low Temperature Poly Silicon (LTPS), or the like. Each of the transistors may be implemented as a transistor having a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) or an n-channel MOSFET structure. In the embodiment, the description will be focused on an example in which the transistors of the pixel circuit are implemented as p-channel transistors, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from source to drain. In the case of the n-channel transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-channel transistor, the direction of current flows from drain to source. In the case of a p-channel transistor (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the p-channel transistor, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

It should be noted that in the following embodiments, the display device is mainly described with respect to the organic light emitting display device, but is not limited thereto. For example, the embodiment of the present invention can be applied to a control method of a driving circuit required for driving the liquid crystal display device (LGD) without major change.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 and a display panel driver.

The display panel driver writes the pixel data of the input image into pixels of the screen to display the image on the screen. The display panel driver converts the pixel data into a data signal voltage (hereinafter referred to as a “data voltage”), the gate drivers 122 and 124 supplying gate signals to the gate lines GL of the display panel 100 . The data drivers 112 and 114 supplied to the data lines DL, the controllers 302 and 304 for controlling the operation timing of the data drivers 112 and 114 and the gate drivers 122 and 124, the power supply 200, etc. includes

The screens AA1 and AA2 of the display panel 100 are pixel arrays in which data lines DL, gate lines GL crossing the data lines DL, and pixels P are arranged in a matrix form. includes The pixels P are arranged in a pixel array in a matrix form defined by the data lines DL1 to DL6 and the gate lines GL1 and GL2. The pixels P display an image by applying pixel data (hereinafter, referred to as a “data voltage”).

The screens AA1 and AA2 may be divided and driven into at least two or more. Here, the division driving of the screens AA1 and AA2 means that the images are divided by different controllers 302 and 304, and the display panel 100 does not need to be physically separated.

Each of the pixels P includes sub-pixels having different colors for color implementation. The sub-pixels may be divided into red, green, and blue colors. Although not shown, the pixel P may further include a white sub-pixel. Hereinafter, a pixel may be interpreted as a sub-pixel.

Each of the sub-pixels may include an internal compensation circuit for compensating the gate voltage of the driving device by sensing an electrical characteristic of the driving device, for example, a threshold voltage, but is not limited thereto.

When the resolution of the pixel array is m*n, the pixel array includes m pixel columns and n pixel lines intersecting the pixel columns. The pixel column includes pixels arranged along the Y-axis direction. The pixel lines L1 to Ln include pixels arranged along the X-axis direction. One horizontal period (1H) is a time obtained by dividing one frame period by the number of n pixel lines. The gate drivers 122 and 124 may sequentially output the gate signal from the first pixel line to the mth pixel line to progressively scan the pixels line by line.

The pixel array of the display panel 100 may be formed on a glass substrate, a metal substrate, or a plastic substrate. In the case of a plastic OLED panel, a pixel array may be formed on a plastic substrate and implemented as a flexible panel. A plastic OLED panel includes an array of pixels on an organic thin film adhered on a back plate. A touch sensor array may be formed over the pixel array.

The back plate may be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the back plate. A pixel array and a touch sensor array may be formed on the organic thin film. The back plate blocks the moisture permeation towards the organic thin film so that the pixel array is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layered buffer film may be formed of an insulating material (not shown) on the organic thin film. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic thin film.

The data drivers 112 and 114 receive pixel data of input images received from the controllers 302 and 304 through a digital-to-analog converter (hereinafter referred to as “DAC”) to which the gamma reference voltage and pixel data are input. (digital signal) is converted into a gamma compensation voltage to output a data voltage (Vdata). The data voltage Vdata output from the data drivers 112 and 114 is supplied to the data lines DL.

The first controller 302 transmits pixel data to be written in the pixels P of the first screen AA1 to the first data driver 112 . The first data driver 112 receives the first image information to be written in the pixels of the first screen AA1 and the gamma reference voltage, and converts the first image information into a first data voltage to display the first image information of the first screen AA1. A first data voltage may be supplied to the data lines DL. The second controller 304 transmits pixel data to be written in the pixels P of the second screen AA2 to the second data driver 114 . The second data driver 114 receives the second image information to be written in the pixels of the second screen AA2 and the gamma reference voltage, and converts the second image information into a second data voltage to display the second image information on the second screen AA2. A second data voltage may be supplied to the data lines.

The gate drivers 122 and 124 together with the pixel array may be disposed on the substrate of the display panel 100 . The gate drivers 122 and 124 formed directly on the substrate of the display panel 100 are known as gate in panel (GIP) circuits.

The gate drivers 122 and 124 may be disposed on one of the left and right bezels of the display panel 100 to supply gate signals to the gate lines GL1 and GL2 in a single feeding method.

In the single feeding method, one of the two gate drivers 122 and 124 in FIG. 1 may be omitted. The gate drivers 122 and 124 may be disposed on each of the left and right bezels of the display panel 100 to supply gate signals to the gate lines GL in a double feeding method. In the double feeding method, gate signals may be simultaneously applied to both ends of the gate line GL. In the double-feeding method, the gate line GL is shared by pixels of one pixel line across the first and second screens AA1 and AA2 without being interrupted between the first and second screens AA1 and AA2. can be

The first and second gate drivers 122 and 124 may output a gate signal under the control of any one of the first and second controllers 302 and 304 . In the example of FIG. 1 , the first and second gate drivers 122 and 124 output gate signals under the control of the first controller 302 . In another embodiment, the first gate driver GL2 outputs a gate signal under the control of the first controllers 302 , and the second gate driver GL01 applies the gate signal under the control of the second controllers 304 . can be printed out.

The first gate driver GL2 supplies a gate signal to the gate lines GL under the control of the first controller 302 using a shift register. The second gate driver GL2 supplies a gate signal to the gate lines GL under the control of the first controller 302 using a shift register. The shift register may sequentially supply the gate signal to the gate lines GL by shifting the gate signal.

The shift register may sequentially supply the gate signal to the gate lines GL by shifting the gate signal. The gate signal may include scan signals [SCAN1, SCAN2, SCAN(N-1), SCAN(N)], emission control signals [EM, EM(N)], etc. shown in FIGS. 3 and 4 . Hereinafter, the "light emission control signal" is referred to as an EM signal.

The first and second controllers 302 and 304 generate an operation result defining the output voltage level of the power supply unit 200 when an input image is input and provide the result to peripheral integrated circuits including the power supply unit 200 to provide the power supply unit 200 control For example, the first and second controllers 302 and 304 may include the power supply unit 200 according to an attribute of the input image, for example, a brightness value (Digital 　 Brightness 　 Value, DBV) received from the host system 200 . It may include an interface and an operation unit for performing an operation for defining the output voltage level of . The properties of the spiritual image may include an image genre, a brightness mode, a power consumption mode, etc. in addition to the brightness value of the input image. The interface and operation unit may further include an interface unit for transmitting and receiving data with a peripheral integrated circuit, a data restoration unit for decoding and restoring compressed pixel data, an optical compensation unit for adding a preset optical compensation value to the pixel data, etc. have. The optical compensation value may be set as a value for correcting the luminance of each pixel data based on the luminance of the screen measured based on the camera image captured in the manufacturing process. When the property of the input image signal is changed, the first and second controllers 302 and 304 may change the output voltage level of the power supply unit 200 when the property of the input image signal is changed.

The controllers 302 and 304 provide pixel data of an input image received from the host system 200 to the data drivers 112 and 114 . The controllers 302 and 304 provide pixel data of an input image received from the host system 200 to the data drivers 112 and 114 . The first controller 302 transmits the pixel data of the input image received from the host system 200 to the first data driver 112 , and uses a timing signal received in synchronization with the input image to the first data driver 112 . ) and the timing control signals CSIG and GSIG for synchronizing the gate drivers 122 and 124 may be output. The second controller 304 transmits the pixel data of the input image received from the host system 200 to the second data driver 114 , and uses a timing signal received in synchronization with the input image to the second data driver 114 . ) may output a timing control signal CSIG for controlling the operation timing.

The display panel driver may further include a level shifter omitted from the drawing. The level shifter converts a low level voltage of the gate timing signal GSIG received from the first controller 302 into a gate low voltage VGL, and a high level voltage of the gate timing signal. to the gate high voltage (VGH). The level shifter may output the gate timing signal GSIG and the gate voltages VGH and VGL and supply them to the gate drivers 122 and 124 . The gate timing signal GSIC may include a start pulse (VST), a shift clock (GCLK), and the like. The start pulse VST and the shift clock GCLK swing between the gate-on voltage VGL and the gate-off voltage VGH.

The host system 200 includes a main processor of any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a home theater system, a mobile system, a wearable system, a graphic processing circuit, a main power supply, etc. may include. The host system 200 transmits pixel data to be displayed on the first screen AA1 to the first controller 302 through a first port, and transmits pixel data to be displayed on the second screen AA2 through a second port. Pixel data may be transmitted to the second controller 304 .

One of the first and second controllers 302 and 304 may be a master controller and the other may be a slave controller. In the example of FIG. 1 , the first controller 302 is a master controller, and the second controller 304 is a slave controller, but is not limited thereto. The master controller generates an operation result by performing gamma curve operation of pixel data according to the properties of the input image, and transmits the operation result to the power supply 200 and the slave through a ^{communication interface, for example, the I 2 C communication wiring 312 .} It transmits to the controller and has the control right to control the peripheral integrated circuit. Here, an example of the peripheral integrated circuit may be the power supply unit 200, but is not limited thereto. For example, the peripheral integrated circuit may further include a circuit that generates an output under the control of the master controller, for example, one or more of a data driver, a gate driver, and a power supply.

The present invention can convert the control right of the peripheral integrated circuit of the master controller to the slave controller by using a communication interface connecting the master controller, the slave controller, and the peripheral integrated circuit in a situation in which the master controller cannot operate normally. In the embodiment, two controllers are illustrated, but the present invention is not limited thereto. When the screen becomes larger and the resolution increases, two or more controllers may divide and control the display panel drivers. In this case, one of the controllers has the control right of the peripheral integrated circuit as the master controller, and the other controllers may serve as the slave controllers.

The power supply unit 200 may generate DC power required for driving the pixel array of the display panel 100 and the display panel driver by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 200 adjusts the DC input voltage from the host system 200 to obtain a gamma reference voltage, a gate high voltage (VGL). DC power such as the gate low voltage VGH, the pixel driving voltage ELVDD, the low potential power voltage ELVSS, and the initialization voltages Vini and Vref may be generated.

The gamma reference voltage is supplied to the first and second data drivers 112 and 114 . The data drivers 112 and 114 divide the gamma reference voltage to generate a gamma compensation voltage and supply it to the DAC. The gate low voltage VGL and the gate high voltage VGH are supplied to the level shifter and the gate drivers 122 and 124 . Pixel power, such as the pixel driving voltage ELVDD, the low potential power voltage ELVSS, and the initialization voltages Vin and Vref, is commonly supplied to the pixels P.

The initialization voltages Vini and Vref are voltages for initializing main nodes of the pixel circuit. The gate voltage may be set to VGH = 8V, VGL = -7V, the pixel power may be set to ELVDD = 4.6V, ELVSS = -2V to -3V, and Vini (or Vref) = -3V to -4V, but is not limited thereto. The data voltage Vdata may be set to Vdata = 2V to 6V, but is not limited thereto.

2 is a diagram schematically showing a pixel circuit of the present invention.

Referring to FIG. 2 , the pixel circuit may include first to third circuit parts 10 , 20 , and 30 , and first to third connection parts 12 , 23 , and 13 . One or more components may be omitted or added in this pixel circuit.

The first circuit unit 10 supplies the pixel driving voltage ELVDD to the driving element DT. The driving device DT may be implemented as a transistor including a gate DRG, a source DRS, and a drain DRD. The second circuit unit 20 charges the capacitor Cst connected to the gate DRG of the driving element DT and maintains the voltage of the capacitor Cst for one frame period. The third circuit unit 30 converts the current into light by providing the current supplied from the pixel driving voltage ELVDD to the light emitting device EL through the driving device DT. The first connection part 12 connects the first circuit part 10 and the second circuit part 20 . The second connection part 23 connects the second circuit part 20 and the third circuit part 30 . The third connection part 13 connects the third circuit part 30 and the first circuit part 10 . Each of the first connection part 12 , the second connection part 23 , and the third connection part 13 may include one or more transistors and wirings. The pixel circuit may be implemented as a circuit including an internal compensation circuit as shown in FIGS. 3 and 4 .

The pixel circuits shown in FIGS. 3 and 4 are arbitrary sub-pixel circuits belonging to the Nth pixel line. The pixel circuits include an internal compensation circuit that senses the threshold voltage Vth of the driving device DT and compensates the gate voltage of the driving device DT by the threshold voltage Vth.

As shown in FIGS. 3 and 4 , the display panel 100 applies a first power line 61 for supplying the pixel driving voltage ELVDD to the pixels P and a low potential power voltage ELVSS to the pixels. It may further include a second power line 62 for supplying the pixels P, and a third power line 63 for supplying the pixels P with initialization voltages Vref and Vini for initializing the pixel circuit. can

Referring to FIG. 3 , the pixel circuit includes a light emitting element EL, a plurality of transistors T1 to T5 and DT, a capacitor Cst, and the like. The transistors T1 to T5 and DT may be implemented as p-channel transistors. The transistors T1 to T5 and DT include switch elements T1 and T5 and a driving element DT.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and fifth switch elements T4 and T5 through the fourth node n4. The cathode of the OLED is connected to the second power line 62 to which the low potential power voltage ELVSS is applied. The driving device DT drives the light emitting device EL by controlling the amount of current flowing through the light emitting device EL according to the gate-source voltage Vgs. The current flowing to the light emitting element EL may be switched by the fourth switch element T4 .

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to the second electrode of the first switch element T1 , the first electrode of the third switch element T3 , and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving device DT, and the first electrode of the second switch device T2. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT sensed in the capacitor Cst is charged.

The first switch element T1 supplies the data voltage Vdata to the first node n1 in response to the second scan signal SCAN2 . The first switch element T1 includes a gate connected to the second gate line GL2 , a first electrode connected to the data line 131 , and a second electrode connected to the first node n1 .

The second scan signal SCAN2 is supplied to the pixels P through the second gate line GL2 . The second scan signal SCAN2 is generated as a pulse of the gate-on voltage VGL. A pulse of the second scan signal SCAN2 defines a sensing time Ts. A pulse width of the second scan signal SCAN2 may be set to approximately one horizontal period 1H. The second scan signal SCAN2 changes to the gate-on voltage VGL later than the first scan signal SCAN1 and changes to the gate-off voltage VGH at the same time as the first scan signal SCAN1. A pulse width of the second scan signal SCAN2 may be set to be smaller than that of the first scan signal SCAN1 . During the initialization time Ti and the light emission time Tem, the voltage of the second scan signal SCAN2 maintains the gate-off voltage VGH.

The second switch element T2 connects the gate of the driving element DT and the second electrode of the driving element DT in response to the first scan signal SCAN1 to operate the driving element DT as a diode. make it The second switch element T2 includes a gate connected to the first gate line GL1 , a first electrode connected to the second node n2 , and a second electrode connected to the third node n3 .

The first scan signal SCAN1 is supplied to the pixels P through the first gate line GL1 . The first scan signal SCAN1 may be generated as a pulse of the gate-on voltage VGL. A pulse of the first scan signal SCAN1 defines an initialization time Ti and a sensing time Ts. During the emission time Tem, the voltage of the first scan signal SCAN1 maintains the gate-off voltage VGH.

The third switch element T3 supplies a predetermined initialization voltage Vref to the first node n1 in response to the EM signal EM(N). The initialization voltage Vref is supplied to the pixels P through the third power line 63 . The third switch element T3 includes a gate connected to the third gate line GL3 , a first electrode connected to the first node n1 , and a second electrode connected to the third power line 63 . The EM signal EM(N) is supplied to the pixels P through the third gate line GL3 to define an on/off time of the light emitting device EL.

The pulse of the EM signal [EM(N)] blocks a current path between the first node n1 and the third power line 63 during the sensing time Ts, and the current of the light emitting element EL It may be generated as a gate-off voltage VGH in order to block a pass. The EM signal EM(N) is inverted to the gate-off voltage VGH when the second scan signal SCAN2 is inverted to the gate-on voltage VGL, and the first and second scan signals SCAN1 and SCAN2 are After being inverted to the gate-off voltage VGH, it may be inverted to the gate-on voltage VGL. In order to accurately express the luminance of the low gray scale, the EM signal [EM(N)] is transmitted between the gate-on voltage VGL and the gate-off voltage VGH at a predetermined duty ratio during the emission time Tem. can swing.

The fourth switch element T4 switches the current path of the light emitting element EL in response to the EM signal EM(N). The gate of the fourth switch element T4 is connected to the third gate line GL3 . The first electrode of the fourth switch element T4 is connected to the third node n3 , and the second electrode of the fourth switch element T4 is connected to the fourth node n4 .

The fifth switch element T5 is turned on according to the gate-on voltage VGL of the first scan signal SCAN1 and is applied to the fourth node n4 during the initialization time Ti and the sensing time Ts. Vref) is supplied. During the initialization time Ti and the sensing time Ts, the anode voltage of the light emitting element EL is discharged to the initialization voltage Vref. At this time, the light emitting element EL does not emit light because the voltage between the anode and the cathode is smaller than its threshold voltage. The fifth switch element T5 includes a gate connected to the first gate line GL1 , a first electrode connected to the third power line 63 , and a second electrode connected to the fourth node n4 .

The driving device DT controls the current flowing through the light emitting device EL according to the gate-source voltage Vgs to drive the light emitting device EL. The driving element DT includes a gate connected to the second node n2 , a first electrode connected to the first power line 61 , and a second electrode connected to the third node n3 . The pixel driving voltage ELVDD is supplied to the pixels P through the first power line 61 .

Referring to FIG. 4 , the pixel circuit includes a light emitting element EL, a plurality of transistors T11 to T16 and DT, a capacitor Cst, and the like.

The transistors T11 to T16 and DT may be implemented as p-channel transistors. The transistors T11 to T16 and DT include switch elements T1 and T5 and a driving element DT.

The gate signal applied to the pixel circuit includes an N-1 th scan signal SCAN(N-1), an N-th scan signal SCAN(N), and an EM signal EM(N). The pulse of the N-1 th scan signal SCAN(N-1) is synchronized with the data voltage Vdata of the N-1 th pixel line. A pulse of the Nth scan signal SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel line. The pulse of the N-th scan signal [SCAN(N)] is generated with the same pulse width as the N-1th scan signal SCAN(N-1), and the pulse of the N-1th scan signal [SCAN(N-1)] Occurs later than the pulse. A pulse width of the scan signals SCAN(N-1), SCAN(N) may be set to one horizontal period (1H).

The capacitor Cst is connected between the first node n11 and the second node n12. The pixel driving voltage ELVDD is supplied to the pixels P through the first power line 61 . The first node n11 is connected to the first power line 61 , the first electrode of the third switch element T13 , and the first electrode of the capacitor Cst.

The second node n12 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the first switch element T11, and the first electrode of the fifth switch element T15. do.

The first switch element T11 is turned on according to the gate-on voltage VGL of the N-th scan signal SCAN(N) to connect the gate and the second electrode of the driving element DT. The first switch element T11 includes a gate connected to the second gate line GL02 , a first electrode connected to the second node n12 , and a second electrode connected to the third node n13 . The Nth scan signal SCAN(N) is supplied to the pixels P through the second gate line GL02. The third node n13 is connected to the gate of the driving element DT, the second electrode of the first switch element T11 , and the first electrode of the fourth switch element T14 .

The second switch element T12 is turned on according to the gate-on voltage VGL of the N-th scan signal SCAN(N) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switch element T12 includes a gate connected to the second gate line GL02 , a first electrode connected to the fifth node n15 , and a second electrode connected to the data line 131 . The fifth node n15 is connected to the first electrode of the driving element DT, the first electrode of the second switch element T12 , and the second electrode of the third switch element T13 .

The third switch element T13 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(N). The third switch element T13 includes a gate connected to the third gate line GL03 , a first electrode connected to the first power line 61 , and a second electrode connected to the fifth node n15 . The EM signal EM(N) is supplied to the pixels P through the third gate line GL03.

The fourth switch element T14 is turned on according to the gate-on voltage VGL of the EM signal EM(N) to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The gate of the fourth switch element T14 is connected to the third gate line GL03. The first electrode of the fourth switch element T14 is connected to the third node n13 , and the second electrode of the fourth switch element T14 is connected to the fourth node n14 . The fourth node n14 is connected to the anode of the light emitting element EL, the second electrode of the fourth switch element T14, and the second electrode of the sixth switch element T16.

The fifth switch element T15 is turned on according to the gate-on voltage VGL of the N-1 th scan signal SCAN(N-1) to connect the second node n12 to the third power line 63 . connected to initialize the gates of the capacitor Cst and the driving element DT during the initialization time Ti. The fifth switch element T15 includes a gate connected to the first gate line GL01 , a first electrode connected to the second node n12 , and a second electrode connected to the third power line 63 .

The N-1th scan signal SCAN(N-1) is supplied to the pixels P through the first gate line GL01. The initialization voltage Vini is supplied to the pixels P through the third power line 63 .

The sixth switch element T16 is turned on according to the gate-on voltage VGL of the N-1 th scan signal SCAN(N-1) to emit light from the third power line 63 for the initialization time Ti. It is connected to the anode of the element EL. During the initialization time Ti, the anode voltage of the light emitting element EL is discharged to the initialization voltage Vini through the sixth switch element T16. At this time, the light emitting element EL does not emit light because the voltage between the anode and the cathode is smaller than its threshold voltage. The sixth switch element T16 includes a gate connected to the first gate line GL01 , a first electrode connected to the third power line 63 , and a second electrode connected to the fourth node n14 .

The driving device DT controls the current flowing through the light emitting device EL according to the gate-source voltage Vgs to drive the light emitting device EL. The driving element DT includes a gate connected to the second node n12 , a first electrode connected to the fifth node n15 , and a second electrode connected to the third node n13 .

5 is a diagram schematically illustrating transfer of control right to a peripheral integrated circuit according to the first embodiment of the present invention.

Referring to FIG. 5 , each of the first and second data drivers 112 and 114 may be implemented as one or more source drive ICs (SICs). A chip on film (COF) on which a source drive IC (SIC) is mounted is connected between a printed circuit board (hereinafter, referred to as “PCB”) and the display panel 100 . The input pads of the COF are connected to the output terminals of the PCB. Output pads of the COF are connected to input pads of the display panel 100 . The output pads of the COF may be adhered to the input pads of the display panel 100 through an anisotropic conductive film (ACF). The host system 200 may be connected to the PCB through a flexible printed circuit, for example, a flexible printed circuit (FPC) and a connector (CNT).

The power supply unit 200 includes a first power supply unit 202 for outputting a gamma reference voltage (GMA) whose voltage level is determined according to an operation result of the controllers 302 and 304 and a voltage according to the operation result of the controllers 302 and 304 . The second power supply unit 204 outputting the pixel driving voltage ELVDD whose level is determined may be included. A voltage level of each of the gamma reference voltage GMA and the pixel driving voltage ELVDD is determined according to a resistor setting value. The register setting value is selected according to the operation result of the controllers 302 and 304 . When the operation result of the controllers 302 and 304 is changed according to the property of the input image, the voltage level of at least one of the gamma reference voltage ELVDD and the pixel driving voltage ELVDD is changed.

The first controller 302 , the second controller 304 , the first power supply unit 202 , and the second power supply unit 204 may be implemented as separate integrated circuit chips (Integrated Circuit Chip). The first controller 302 , the second controller 304 , the first power supply unit 202 , and the second power supply unit 204 are connected to each other through a ^{common communication interface, for example, a common I 2 C channel 312 .}

The first and second controllers 302 and 302 may be connected through a multi-chip interface wiring 314 to be synchronized with each other. Error confirmation information and control transfer information of each of the controllers 302 and 304 may be transmitted/received between the controllers 302 and 304 through the multi-chip interface wiring 314 .

A malfunction of the master controller among the first and second controllers 302 and 304 may occur. For example, an error may occur in an interface and an operation unit interworking with a peripheral integrated circuit. In this case, the quality of the input image on the screens AA1 and AA2 is deteriorated or the input image is not normally displayed because the peripheral integrated circuits, for example, the first and second power supply units 202 and 204 cannot operate normally. . In the case of a vehicle display, if important information related to driving is not displayed even for a moment, it may cause serious safety problems for the driver and passengers. The present invention transfers the control right of the peripheral integrated circuit of the master controller to the slave controller using the ^{common I 2} C channel 312 connecting the master controller, the slave controller, and one or more peripheral integrated circuits. Accordingly, even if an error of the master controller occurs, the peripheral integrated circuits operate normally, so that the input image and important information can be normally displayed on the screens AA1 and AA2 without interruption.

Each of the first and second controllers 302 and 304 may generate an operation result when an input image is input from the host system 400 . When the first controller 302 is a master controller having control of the power supply units 202 and 204 , the power supply units 202 and 204 are connected to the first controller 302 while the first controller 302 outputs a normal operation result. ) and outputs the power in response to the operation result inputted from it. The second controller 304 has an error in the operation result of the first controller 302 transmitted to the ^{common I 2} C channel 312 while the first controller 302 has control of the power supply units 202 and 204 . When it is done, the control right is transferred from the first controller. The second controller 304 receives the control right of the power supply units 202 and 204 from the first controller 302 and transmits the internally generated operation result to the power supply units 202 and 204 through the ^{common I 2 C wiring 312 .} to control the power supply units 202 and 204 .

6 is a flowchart showing step by step a control procedure of a method for transferring control right to a peripheral integrated circuit according to an embodiment of the present invention. In FIG. 6 , it is assumed that “Master IC” is the first controller 302 and “Slave IC” is the second controller 304 .

5 and 6 , each of the controllers 302 and 304 sets the output voltage of the peripheral integrated circuit, for example, the power supply units 202 and 204 when the property of the input image from the host system 400 is changed. The first operation result obtained by performing the operation for is stored in the internal memory (S121, S122). When the property of the input image is changed, the calculation result calculated by the timing controllers 302 and 304 may be changed, so that the output of the peripheral integrated circuit may be changed.

The first controller 302 set as the Master IC transmits the first operation result for controlling the peripheral integrated circuit to the power supply units 202 and 204 and the second through the ^{peripheral integrated circuit, for example, the common I 2 C wiring 312 .} It is simultaneously transmitted to the controller 304 (S123). The power supply units 202 and 204 output power at a voltage level defined by the first operation result received through the ^{common I 2 C line 312 .} Meanwhile, the first operation result is transmitted to other peripheral integrated circuits through the common I2C wiring 312 to control the outputs of the peripheral integrated circuits, for example, the data drivers 112 and 114 and the gate drivers 122 and 124. may be

The second controller 304 ^{monitors the common I 2} C wire 312 and outputs the first operation result received from the first controller 302 through the common I2C wire 312 in the second controller 304 . It compares with the second operation result generated in ( S124 ). The second controller 304 checks whether there is an error based on the comparison result of the first and second calculation results, and transmits error confirmation information indicating whether there is an error to the first controller 302 ( S125 ). The error check information may indicate whether the first controller 302 has an error and whether the second controller 302 has an error. The error check information may be transmitted through the multi-chip interface wiring 314 between the controllers 302 and 304 .

The second controller 304 compares the operation result generated inside its own and the data received through the common IC wiring 312 to determine whether there is an error between the first controller 302 and the second controller 304 . can For example, if the second controller 304 compares the second operation result generated inside its own and the first operation result received from the first controller 302 and is inconsistent, the second operation result and the power supply units 202 , 204) can be compared to check whether there is an error. Based on a checksum comparison of the value received from the power supply units 202 and 204 and the internal operation result, it is possible to determine the operation error of the controllers 302 and 304 . Also, it is possible to determine an operation error of the controllers 302 and 304 through the acknowledgment information ACK received from the power supply units 202 and 204 .

The first controller 302 checks the error confirmation information received through the common I2C wiring 312 to determine whether it is its own error or that of the second controller 304 (S126, S127, and S128). If the first controller 302 is determined to be its own error based on the error check information, the first controller 302 compares the checksum between the internally generated first operation result and the register setting values of the power supply units 202 and 204 to determine their error. can check whether

The first controller 302 transfers the control right of the peripheral integrated circuit to the second controller 304 when it is determined that it is an error of the first controller 302 . When the control transfer code of the peripheral integrated circuit is received, the second controller 304 transmits the result of the second operation generated within itself to the power supply units 202 and 204 through the ^{common I 2 C wiring 312 and the first controller (} 302) (S129). The power supply units 202 and 204 output power at a voltage level defined by the second operation result received through the ^{common I 2 C line 312 .} At this time, the first controller 302 operates as a slave controller and monitors the second operation result by performing steps S121, S122, S124, and S125 based on the data received through ^{the common I 2 C wiring 312 (} monitor). As a result of monitoring the second operation result, when an error occurs in the second operation result, the control right of the first and second power supplies 202 and 204 may be over again.

When it is determined that both the first and second controllers 302 and 304 are errors in steps S126 to S128, the first controller 302 resets according to a preset reset sequence and reboots (S131) ). The controllers 302 and 304 may operate normally when reset when a temporary failure or error occurs.

The I2C communication between the controllers 302, 304 and the peripheral integrated circuit may be performed at a time when pixel data to be displayed on the controllers 302, 304 is not received, for example, every horizontal blank period, every vertical blank period. .

Accordingly, in the present invention, when an error occurs in the master controller that controls the peripheral integrated circuit, the control right of the peripheral integrated circuit is transferred to the slave controller to enhance fail-safe, so that the input image and important information are displayed on the display panel in any situation. can be made visible.

7 is a view showing transfer of control right to a peripheral integrated circuit according to a second embodiment of the present invention.

Referring to FIG. 7 , the display device of the present invention may further include spare peripheral integrated circuits controlled by the controllers 302 and 304 . For example, the power supply unit 200 may include the 1-1 and 1-2 power supply units 2021 and 2022 outputting a gamma reference voltage (GMA) whose voltage level is determined according to the operation result of the controllers 302 and 304 . and second power supply units 2041 and 2042 for outputting a pixel driving voltage ELVDD whose voltage level is determined according to an operation result of the controllers 302 and 304 .

The display device of the present invention selects any one of the outputs of the 1-1 and 1-2 power supply units 2021 and 2022 under the control of any one of the first and second controllers 302 or 304 having a control right. The first multiplexer (hereinafter referred to as "MUX", 502), and the 2-1 and 2-2 power supply units 2041 under the control of any one of the first and second controllers 302 or 304 having a control right A second MUX 504 that selects any one of the outputs of 2042 may be further included.

The first and second controllers 302 and 304 may generate a selection signal CMUX for controlling the first and second MUXs 502 and 504 . Among the first and second controllers 302 and 304 , a controller having control of a peripheral integrated circuit may control the MUXs 502 and 504 .

In this embodiment, the method of transferring the control right of the peripheral integrated circuit based on data transmitted through the ^{common I 2 C wiring 312 is substantially the same as in the above-described embodiment.} This embodiment compares the data of the controllers 302 and 304 and the peripheral integrated circuits 2021, 2022, 2041, 2042 using the ^{common I 2 C wiring 312 to determine the peripheral integrated circuits 2021, 2022,} When peripheral integrated circuits operating abnormally among 2041 and 2042 are detected, the screens AA1 and AA2 are driven by the output of the spare peripheral integrated circuits. Hereinafter, it is assumed that the first controller 302 is a master controller and the second controller 304 is a slave controller. In addition, it is assumed that the 1-2 power supply unit 2022 and the 2-2 power supply unit 2042 are spare peripheral integrated circuits.

The second controller 304 ^{monitors the first operation result output from the first controller 302 through the common I 2} C wiring 312 to determine whether the first controller 302 has an error, When the error of the first controller 302 is confirmed, the control right of the peripheral integrated circuit is transferred from the first controller 302 .

The second controller 304 detects an error in the operation result transmitted to the 1-1 power supply unit 2021 and the 2-1 power supply unit 2041 through the common I2C wiring 312 . When an erroneous operation result is transmitted to the 1-1 power supply unit 2021 or the 1-2 power supply unit 2022 , the second controller 304 takes over the control right of the peripheral integrated circuit from the first controller 302 . The second controller 304 converted to the master controller in this way controls the MUXs 502 and 504 to select the output of the 1-2th power supply unit 2022 instead of the 1-2th power supply unit 2021, and 2-1 An output of the second-second power supply unit 2022 may be selected instead of the power supply unit 2021 .

While the second controller 304 has the control right, the first controller 302 ^{determines whether information transmitted through the common I 2} C wiring 312 is in error. ^{When there is an error in information transmitted through the common I 2} C wire 312 , the first controller 302 may transfer control to the second controller 304 again according to a recovery sequence. The first controller 304 may be restarted after reset as shown in FIG. 6 .

8 is a diagram showing transfer of control right to a peripheral integrated circuit according to a third embodiment of the present invention.

Referring to FIG. 8 , the controllers 302 and 304 may receive a feedback signal GFB from the gate drivers 122 and 124 through the feedback line 316 . The feedback wiring 316 connects the gate drivers 122 and 124 and the controllers 302 and 304 . A feedback wire 316 is connected to the controllers 302 and 304 on the PCB.

The display device of the present invention includes a MUX 506 that selects any one of the first and second gate timing signals GSIG1 and GSIG2 under the control of any one of the first and second controllers 302 or 304 having a control right. may include more. The first controller 302 generates a first gate timing control signal GSIG1 and supplies it to a first input terminal of the MUX 506 . The second controller 302 generates a second gate timing control signal GSIG1 and supplies it to a second input terminal of the MUX 506 .

In this embodiment, the method of transferring the control right of the peripheral integrated circuit based on data transmitted through the common I2C wiring 312 is substantially the same as in the above-described embodiments.

The first and second controllers 302 and 304 may count the feedback signal GFB and compare the count value with a preset reference value to determine whether the feedback signal GFB is in error. The first controller 302 set as the master controller transmits the first gate timing signal GSIG1 to the gate drivers 122 and 124 under the control of the first controller 302 when the feedback signal GFB is normal. supply to

When an error in the feedback signal GFB is detected, the first controller 302 controls the MUX 506 to select the second gate timing control signal GSIG2 output from the second controller 304 . At this time, the MUX 506 selects the second gate timing control signal GSIG2 under the control of the first controller 302 and supplies it to the gate drivers 122 and 124 .

While the second controller 304 has the control right, the first controller 302 determines whether information transmitted through the common I2C wiring 312 is in error. When there is an error in information transmitted through the common I2C wiring 312 , the first controller 302 may transfer control back from the second controller 304 according to a recovery sequence. The first controller 304 may be restarted after reset as shown in FIG. 6 .

9 is a diagram schematically showing a circuit configuration of a shift register in a gate driver. FIG. 10 is a view showing transistors connected to the first signal transfer unit shown in FIG. 9 . 11 is a waveform diagram illustrating a first control node voltage, a second control node voltage, and an output voltage of the first signal transfer unit illustrated in FIG. 10 . 12 is a waveform diagram showing a shift of a gate signal output from a gate driver.

9 to 12 , the shift registers of the gate drivers 122 and 124 include signal transfer units ST1 to STn that are dependently connected through a clock line and a carry line. The gate drivers 122 and 124 may output the gate signals Gout1 to Goutn in response to the gate timing signal GSIC and sequentially shift them. The gate timing signal GSIG may include a start pulse VST and shift clocks GCLK1 to GCLK4. The shift clocks GCLK1 to GCLK4 have been illustrated as four-phase clocks in the example of FIG. 9 , but are not limited thereto.

The shift register receives the start pulse VST or the carry signals CAR1 to CARn-1 received from the previous signal transfer unit as a start pulse and synchronizes with the rising edges of the shift clocks GCLK1 to GCLK4 to the gate signals Gout1 to Goutn. ) occurs.

Each of the signal transfer units of the shift register includes a first control node Q, a second control node QB, a pull-up transistor Tup controlled according to the voltage of the first control node Q, and a second control node QB. ) includes a pull-down transistor (Tdn) controlled according to the voltage of the. The pull-up transistor Tup is turned on when the voltage of the first control node Q is boosted to a voltage 2VGL lower than the gate-on voltage VGL and is turned on to convert the voltage of the output node to the gate-on voltage VGL. lower to The pull-down transistor Tdn is turned on when the voltage of the second control node QB is equal to or greater than the gate-on voltage VGL to increase the voltage of the output node to the gate-off voltage VGH.

The feedback signal GFB may be an n-th gate signal Goutn that is the last gate signal. The n-th gate signal Goutn may not be applied to the gate lines of the screens AA1 and AA2 . The n-th signal transfer unit STn may be a dummy signal transfer unit for resetting the previous stage.

13 is a flowchart showing step by step a control procedure of the method for controlling important information according to the first embodiment of the present invention. 14A and 14B are diagrams illustrating an example in which a display area of important information is changed due to an error occurring in a controller or a peripheral integrated circuit.

Referring to FIG. 13 , the controllers 302 and 304 ^{are connected to each other through a common I 2} C wiring 312 and also to peripheral integrated circuits.

The controllers 302 and 304 alternately transmit signals in a write mode and a read mode through IC communication in a horizontal/vertical blank period or a preset time period (S191). Here, the signal may be a signal including information for controlling the peripheral integrated circuit, or may be a signal including a preset code regardless of the peripheral integrated circuit control. The controllers 302 and 304 may determine the state of the counterpart controller based on the presence or absence of acknowledgment information (ACK) from the counterpart controller in each of the write mode and the read mode.

In the write mode (Write), the first controller 302 transmits a signal to a specific register area of the second controller 304, and the second controller 304 issues acknowledgment information (ACK) when the signal reception is confirmed. 1 It is transmitted to the controller 302 (S192, S193). When the acknowledgment information ACK is not received from the second controller 304 in the write mode, the first controller 302 determines that the state of the second controller 304 is abnormal and generates a flag signal AFLAG. occurs (S196). The flag signal AFLAG may be generated at a specific level, for example, a high level (high = 1).

In the read mode (Write), the second controller 304 transmits a signal including data stored in its specific register area to the first controller 302, and when the signal reception is confirmed, the first controller 302 confirms information (ACK) is transmitted to the second controller 304 (S194, S195). If the acknowledgment information ACK is not received from the first controller 302, the second controller 304 determines that the state of the first controller 302 is abnormal and generates a flag signal AFLAG ( S196). In step S196 , the generated flag signal AFLAG is transmitted to the host system 400 .

When the flag AFLAG is not received from the controllers 302 and 304, the host system 400 divides the pixel data of the input image into screen areas in a normal data format without changing the display area of the important information, so that the controllers It is distributed to (302, 304) and transmitted (S198). In this case, as shown in FIG. 14A , the display area of the important information 2000 is not changed on the screens AA1 and AA2 and the pixel data of the input image is normally displayed.

When the graphic processing unit of the host system 400 receives the flag AFLAG from the first controller 302 , the display area of the important information 2000 to be displayed on the second screen AA2 is moved into the first screen AA1 . The rearranged pixel data is rearranged as much as possible and the rearranged pixel data is transmitted to the first controller 302 (S199). In this case, the host system 400 may not transmit pixel data to the second controller 304 .

When the flag AFLAG is received from the second controller 302, the graphic processing unit of the host system 400 changes the display area of the important information 2000 to be displayed on the first screen AA1 to the second screen (as shown in FIG. 14B). AA2) rearranges the pixel data so as to be moved into the AA2) and transmits the rearranged pixel data to the second controller 304 (S199). In this case, the host system 400 may not transmit pixel data to the first controller 302 .

The controllers 302 and 304 may determine whether an image can be displayed on the screen by checking the states of other controllers and peripheral integrated circuits based on information transmitted through the ^{common I 2 C wiring 312 .} For example, when the data driver 112 , the gate driver 122 , and the like, which are controlled by the first controller 302 , cannot be driven normally, the first screen AA1 as shown in FIG. 14A is important to the input image. Information 2000 cannot be displayed. In this case, one of the controllers 302 and 304 that can normally drive the screen may transmit a flag signal to the host system 400 . The graphic processing unit of the host system 400 may rearrange the important information 2000 to a displayable screen position as shown in FIG. 14B in response to the flag signal, and transmit data including the important information 2000 to the controller that generated the flag signal. .

15 is a flowchart showing step by step a control procedure of a method for controlling important information according to a second embodiment of the present invention.

Referring to FIG. 15 , the controllers 302 and 304 display a flag indicating a no signal mode when a signal is not received from the host system 400 after the display device is powered on (Power ON). A signal BFLAG may be transmitted to the host system 400 . When any one of the first and second controllers 302 and 304 repeatedly generates the flag signal BFLAG, the host system 400 may determine that the controller is in an abnormal state.

The host system 400 may distribute and transmit the video signal to the controllers 302 and 304 for each screen area. Each of the controllers 302 and 304 checks whether data of the video signal is received (S211). Each of the controllers 302 and 304 generates a flag signal BFLAG at a specific level, for example, a high level (high = 1) when an image signal is not received (S212 and S213).

The host system 400 resets the data transmitted to the controller 302 or 304 that has generated the flag signal BLAG and then retransmits the data (S215 and S211).

The host system 400 determines that the controller is in an abnormal state when steps S211 to S215 are repeated and a flag signal is continuously received from the same controller N (N is a natural number equal to or greater than 2) times (S216). In this case, the graphic processing unit of the host system S216 does not generate the flag signal BFLAG by rearranging the pixel data so that the display area of the important information 2000 can be displayed on the displayable screen as shown in FIGS. 14A and 14B . It is transmitted to the controller in a normal state (S216 and S217).

The display device and the driving method thereof of the present invention can be described as follows.

Example 1: A display device converts pixel data of first image information to be displayed on a first screen AA1 into a first data voltage using a gamma reference voltage and supplies the first data lines to data lines of the first screen data driver 112; a second data driver 114 for converting pixel data of second image information to be displayed on a second screen AA2 into a second data voltage using the gamma reference voltage and supplying it to data lines of the second screen; a first controller 302 that generates a first operation result and transmits the first image information to the first data driver; a second controller 304 for generating a second operation result and transmitting the second image information to the second data driver; a first power supply unit 202 for receiving the first operation result or the second operation result from any one of the first controller and the second controller having a control right and outputting the gamma reference voltage; and a communication interface 312 that connects the first controller, the second controller, and the first power supply and transmits the first or second operation result.

When an error occurs in the first operation result received from the communication interface, the control right of the first power unit is transferred to the second controller.

Embodiment 2: The second controller transmits the second operation result to the first power supply unit through the communication interface after receiving the control right of the first power supply unit from the first controller.

Embodiment 3: The display device is connected to the communication interface, receives an operation result from any one of the first controller and the second controller having a control right, and supplies the pixels to the pixels of the first and second screens It further includes a second power supply for outputting the driving voltage.

When an error occurs in the first operation result received from the communication interface, the control right of the second power unit is transferred to the second controller.

Embodiment 4: The second controller transmits the second operation result to the second power supply unit through the communication interface after receiving the control right of the second power supply unit from the first controller.

Embodiment 5: The calculation result of each of the first and second controllers changes according to a change in at least one attribute of the brightness value of the input image, the image genre, the brightness mode, and the power consumption mode.

Embodiment 6: Further comprising a multi-chip interface wiring connecting the first and second controllers.

Embodiment 7: The first controller transfers control of the first and second power units to the second controller in response to error confirmation information generated from the second controller based on the monitoring of the first operation result.

Embodiment 8: The second controller is configured to provide the first and second controllers based on a comparison result of the first operation result and the second operation result received through the communication interface, and the register setting values of the first and second power supply units. 2 Generates error check information indicating whether the controller is in error.

Embodiment 9: The error confirmation information is transmitted through the multi-chip interface wiring.

Embodiment 10: The first controller is reset and restarted when an error of both the first and second controllers occurs.

Embodiment 11: In the display device, the first power supply unit 202 includes a 1-1 power supply unit and a 1-2 power supply unit outputting the gamma reference voltage.

The display device further includes a first multiplexer that selects an output of any one of the 1-1 power supply units under the control of any one of the first controller and the second controller having a control right.

Embodiment 12: The second power supply unit 204 includes a 2-1 th power supply unit and a 2-2 th power supply unit 2041 and 2042 for outputting the gamma reference voltage.

The display device further includes a second multiplexer that selects an output of any one of the 1-1 power supply units under the control of any one of the first controller and the second controller having a control right.

Embodiment 13: a gate driver sequentially supplying gate signals to the gate lines of the first and second screens under the control of any one of the first controller and the second controller having a control right; a feedback wire connecting the gate driver and the first and second controllers; and any one of a first gate timing control signal output from the first controller and a second gate timing control signal output from the second controller under the control of any one of the first controller and the second controller having a control right It further includes a multiplexer for supplying to the gate driver.

Embodiment 14: A controller having control right among the first controller and the second controller compares the feedback signal received from the gate driver through the feedback line with a preset reference value to check whether the feedback signal is in error.

The multiplexer supplies the first gate timing signal to the gate driver when the feedback signal is normal, and supplies the second gate timing signal to the gate driver when there is an error in the feedback signal.

Embodiment 15: The display device further includes a graphic processing unit 400 that transmits the pixel data of the first image information to the first controller and transmits the pixel data of the second image information to the second controller .

It generates a flag signal when the first controller sends a signal through the communication interface and no acknowledgment signal is received from the second controller.

It generates the flag signal when the second controller sends a signal through the communication interface and no acknowledgment signal is received from the first controller.

The graphic processing unit receives the flag signal and transmits an image information signal including preset important information data to a controller that has generated the flag signal.

Embodiment 16: The graphic processing unit moves the display area of the important information data and transmits the flag signal to the generated controller.

Embodiment 17: The display device further includes a graphic processing unit 400 that transmits the pixel data of the first image information to the first controller and transmits the pixel data of the second image information to the second controller .

Each of the first and second controllers generates a flag signal indicating a no-signal mode when pixel data of image information is not received.

The graphic processing unit blocks transmission of image information to a controller that continuously generates the flag signal N (N is a natural number greater than or equal to 2) consecutively, and transmits an image information signal including preset important information data to another controller.

Embodiment 18: The graphic processing unit moves the display area of the important information data and transmits it to the other controller.

Embodiment 19: The display device includes: a first controller 302 for receiving first image information to be displayed on a first screen AA1; a second controller 304 receiving second image information to be displayed on the second screen AA2; an integrated circuit 200 controlled by a controller having a control right among the first and second controllers to generate power and signals necessary for driving the first and second screens; and a communication interface 312 connecting the first controller, the second controller, and the integrated circuit.

The first and second controllers determine whether there is an error in the signal received from the communication interface, and when there is an error in the signal generated from the counterpart controller, the control right of the integrated circuit is transferred from the counterpart controller.

In the method of driving the display device, the first image information to be displayed on the first screen AA1 is transmitted to the first controller 302 , and the second image information to be displayed on the second screen AA2 is transmitted to the second controller 304 . ) to transmit; generating, by the integrated circuit 200 controlled by a controller having a control right among the first and second controllers, power and signals necessary for driving the first and second screens; determining, by the first and second controllers, whether a signal transmitted through a communication interface 312 connecting the first controller, the second controller, and the integrated circuit has an error; and transferring control right of an integrated circuit of a controller that has transmitted a signal through the communication interface among the first and second controllers to another controller.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 112, 114: data driver
122, 124: gate driver 200: power supply
302, 304: Controller 312: Common I2C wiring (communication interface)
400: host system 502, 504, 506: multiplexer (MUX)
2000: Important information

Claims (20)

a first data driver converting pixel data of first image information to be displayed on a first screen into a first data voltage using a gamma reference voltage and supplying the converted pixel data to data lines of the first screen;
a second data driver converting pixel data of second image information to be displayed on a second screen into a second data voltage using the gamma reference voltage and supplying it to data lines of the second screen;
a first controller that generates a first operation result and transmits the first image information to the first data driver;
a second controller that generates a second operation result and transmits the second image information to the second data driver;
a first power supply unit receiving the first operation result or the second operation result from any one of the first controller and the second controller having a control right and outputting the gamma reference voltage; and
and a communication interface connecting the first controller, the second controller, and the first power supply and transmitting the first or second operation result,
A display device in which control of the first power unit is transferred to the second controller when an error occurs in the first operation result received from the communication interface. The method of claim 1,
The second controller,
The display device transmits the second operation result to the first power supply unit through the communication interface after receiving control right of the first power supply unit from the first controller. The method of claim 1,
A second power supply unit connected to the communication interface to receive an operation result from any one of the first controller and the second controller having a control right and output a pixel driving voltage supplied to the pixels of the first and second screens further comprising,
A display device in which control of the second power unit is transferred to the second controller when an error occurs in the first operation result received from the communication interface. 4. The method of claim 3,
The second controller,
A display device configured to transmit the second operation result to the second power supply unit through the communication interface after receiving the control right of the second power supply unit from the first controller. The method of claim 1,
The calculation results of each of the first and second controllers are,
A display device that changes according to a change in at least one of the brightness value of the input image, the image genre, the brightness mode, and the power consumption mode. 4. The method of claim 3,
The display device further comprising a multi-chip interface wiring connecting the first and second controllers. 7. The method of claim 6,
The first controller,
A display device for transferring control rights of the first and second power units to the second controller in response to error confirmation information generated from the second controller based on the monitoring of the first calculation result. 7. The method of claim 6,
the second controller
An error indicating whether the first and second controllers are in error based on a comparison result of the first operation result received through the communication interface, the second operation result, and the register setting values of the first and second power supply units A display that generates confirmation information. 9. The method according to claim 7 or 8,
The error check information is transmitted through the multi-chip interface wiring. The method of claim 1,
The first controller,
A display device that is reset and restarted when an error occurs in both the first and second controllers. The method of claim 1,
The first power unit includes a 1-1 power supply unit and a 1-2 power supply unit outputting the gamma reference voltage,
The display device is
and a first multiplexer configured to select an output of any one of the 1-1 power supply units under the control of any one of the first controller and the second controller having a control right. 4. The method of claim 3,
The second power unit includes a 2-1 power supply unit and a 2-2 power supply unit outputting the gamma reference voltage,
The display device is
and a second multiplexer that selects an output of any one of the 1-1 power supply units under the control of any one of the first controller and the second controller having a control right. The method of claim 1,
a gate driver sequentially supplying gate signals to the gate lines of the first and second screens under the control of any one of the first controller and the second controller having a control right;
a feedback wire connecting the gate driver and the first and second controllers; and
Any one of a first gate timing control signal output from the first controller and a second gate timing control signal output from the second controller under the control of any one of the first controller and the second controller having a control right The display device further comprising a multiplexer for supplying the gate driver. 14. The method of claim 13,
A controller having a control right among the first controller and the second controller,
comparing the feedback signal received from the gate driver through the feedback wire with a preset reference value to check whether the feedback signal is in error;
The multiplexer supplies the first gate timing signal to the gate driver when the feedback signal is normal, and supplies the second gate timing signal to the gate driver when there is an error in the feedback signal. The method of claim 1,
Further comprising a graphic processing unit for transmitting the pixel data of the first image information to the first controller and transmitting the pixel data of the second image information to the second controller,
generating a flag signal when the first controller sends a signal through the communication interface and a confirmation signal is not received from the second controller;
generating the flag signal when the second controller sends a signal through the communication interface and no acknowledgment signal is received from the first controller;
The graphic processing unit receives the flag signal and transmits an image information signal including preset important information data to a controller that has generated the flag signal. 16. The method of claim 15,
The graphic processing unit moves the display area of the important information data and transmits the flag signal to a controller that has generated it. The method of claim 1,
Further comprising a graphic processing unit for transmitting the pixel data of the first image information to the first controller and transmitting the pixel data of the second image information to the second controller,
Each of the first and second controllers generates a flag signal indicating a no-signal mode when pixel data of image information is not received,
The graphic processing unit,
A display device that blocks transmission of image information to a controller that continuously generates the flag signal N (N is a natural number greater than or equal to 2) consecutively, and transmits an image information signal including preset important information data to another controller. 18. The method of claim 17,
The graphic processing unit moves the display area of the important information data and transmits it to the other controller. a first controller for receiving first image information to be displayed on a first screen;
a second controller for receiving second image information to be displayed on a second screen;
an integrated circuit controlled by a controller having a control right among the first and second controllers to generate power and signals necessary for driving the first and second screens;
a communication interface connecting the first controller, the second controller, and the integrated circuit;
The first and second controllers determine whether there is an error in the signal received from the communication interface, and when there is an error in the signal generated from the opposite controller, the control right of the integrated circuit is transferred from the opposite controller. transmitting the first image information to be displayed on the first screen to the first controller and transmitting the second image information to be displayed on the second screen to the second controller;
generating, by an integrated circuit controlled by a controller having a control right among the first and second controllers, power and signals necessary for driving the first and second screens;
determining, by the first and second controllers, whether there is an error in a signal transmitted through a communication interface connecting the first controller, the second controller, and the integrated circuit;
and transferring control right of an integrated circuit of a controller that has transmitted a signal through the communication interface among the first and second controllers to another controller.

Images