KR20210083818A - Display device - Google Patents

Abstract

A display device includes: a display panel including a plurality of pixels; a driving circuit, in synchronization with supplying a data voltage through data lines, supplying a first scan signal, a second scan signal, and a light emission signal through gate lines connected to pixels of each horizontal line of the display panel to drive the display panel, wherein the light emitting signal is repeated in an on-pulse section and an off-pulse section for a light emission period; and a timing controller for controlling the driving circuit by setting, to an even number, horizontal periods included in a vertical blank period constituting one frame, wherein the driving circuit can mutually synchronize an on-pulse period and an off-pulse period of a first light emission signal and a second light emission signal supplied to a first and a second display line, which are adjacent thereto and paired, during a light emission period. The present invention can improve the display quality and enhance user satisfaction.

Description

display device {DISPLAY DEVICE}

This specification relates to a display device, and more particularly, to a display device that adjusts a light emitting luminance of a light emitting device by adjusting a duty ratio of a light emitting signal.

The flat panel display includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), a quantum dot display panel (QD), and the like. . The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. Pixels of the organic light emitting diode display include organic light emitting diodes (OLEDs), which are light emitting devices that emit light by themselves, and emit light to display an image.

An active matrix type organic light emitting display panel including an OLED has an advantage in that a response speed is fast and luminous efficiency, luminance, and a viewing angle are large.

In an organic light emitting display device, pixels including an OLED and a driving transistor are arranged in a matrix form, and the luminance of an image implemented in the pixel is adjusted according to a gray level of video data. The driving transistor controls the driving current flowing through the OLED according to the voltage applied between its gate electrode and the source electrode. The amount of light emitted by the OLED is determined according to the driving current, and the brightness of the image is determined according to the amount of light emitted by the OLED.

In order to express a low grayscale image, light emission duty driving that adjusts a duty ratio of a light emission signal that controls light emission of an OLED may be applied. Even when the same data voltage is supplied to the pixel, the luminance can be finely adjusted according to the duty ratio of the emission signal.

However, when driving the emission duty, even when the same gray level is expressed on the entire screen, the luminance is changed in the vertical direction in which the data line proceeds, so that a problem occurs in that a band is recognized in the horizontal direction.

The embodiments disclosed in this specification take this situation into account, and an object of this specification is to provide a display device capable of driving light emitting duty without causing a horizontal band problem.

According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; In synchronization with supplying the data voltage through the data line, the first scan signal, the second scan signal, and the light emission signal are supplied through the gate line connected to the pixels of each horizontal line of the display panel to drive the display panel and emit light. a driving circuit for repeating the light emitting signal in an on pulse period and an off pulse period in a period; and a timing controller configured to control the driving circuit by setting an even number of horizontal periods included in the vertical blank period constituting one frame, wherein the driving circuit includes first and second adjacent and paired first and second periods during the light emission period. The on-pulse period and the off-pulse period of the first light-emitting signal and the second light-emitting signal supplied to the second display lines are synchronized with each other.

Even if the light emission duty driving is performed, the horizontal band becomes inconspicuous by eliminating the deviation between the display line that emits light and the display line that does not emit light according to the duty ratio, thereby improving display quality and enhancing user satisfaction.

1 is a comparison of light emission duty driving with general light emission driving,
2 is a diagram illustrating a phenomenon in which a horizontal band defect occurs when driving a light emitting duty,
3 illustrates an organic light emitting diode display as functional blocks;
4 shows a pixel circuit composed of six transistors and one capacitor,
5 shows signals related to driving of the pixel circuit of FIG. 4;
6 is a diagram illustrating signals related to driving when pixels in two consecutive display lines are duty driven;
7 shows an example of generating a light emitting signal by separating an odd line and an even line,
8A to 11B show a specific situation in which an odd-numbered line emission signal and an even-numbered line emission signal are synchronized so that they are out of phase with each other during the emission period when the emission duty is driven at a 50% duty ratio;
12A to 12C show a specific situation in which an odd-numbered line emission signal and an even-numbered line emission signal are synchronized with each other when the emission duty is driven at a 25% duty ratio;
13 shows a light emission start signal and a light emission duty driving result for generating a light emission signal with a 50% duty ratio;
14 illustrates a light emission start signal and a light emission duty driving result for generating a light emission signal with a 25% duty ratio.

Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the contents of this specification may unnecessarily obscure or obstruct the understanding of the contents, the detailed description thereof will be omitted.

1 is a comparison of light emission duty driving with general light emission driving.

In normal driving, the light emitting luminance is adjusted by varying the data voltage applied to the pixel while the light emitting signal EM of the turn-on level is supplied to the pixel.

For example, when the data voltage (Vdata) is supplied to the pixel at 3V, the brightness is 140nits, when the data voltage (Vdata) is supplied to the pixel at 2V, the brightness is 50nits, and when the data voltage (Vdata) is supplied to the pixel at 1V, the brightness is 15nits. , set the light emission signal to a turn-off level so that the pixel does not emit light. In normal light emission driving, pixels continuously emit light during one frame period.

In EM Duty Driving, the same value, for example, 3V, is supplied to the pixel as the data voltage (Vdata), and the light emitting signal (EM) is turned on while repeating the turn-on level and turn-off level. By varying the duty ratio of the level period and the turn-off level period, the luminance of light emitted by the pixel may be different.

In the figure on the right of Fig. 1, when the light emission signal is at the turn-on level continuously during the frame, the brightness of 140 nits comes out, when the duty ratio of the light emission signal is about 50%, the brightness of 50 nits comes out, and when the duty ratio of the light emission signal is lower than 50% As the luminance of 15 nits is obtained, the longer the turn-on level period of the light emitting signal, the higher the luminance, and the shorter the turn-on level period, the lower the luminance.

In the right figure of FIG. 1, since the light emitting signal repeats the turn-on level and the turn-off level, the black section where the pixel stops emitting light and the white section where the pixel emits light are repeated on the time axis (horizontal axis), and the light emitting signal Since the display line is shifted as it progresses (progressing in the vertical direction), the black band and the white band corresponding to the black section and the white section alternately progress to the lower right.

Since the change in data voltage and the change in luminance do not form a linear relationship and the slope, which indicates the degree of the linear relationship, becomes lower when the data voltage is lowered, changing the duty ratio of the light emitting signal rather than adding or subtracting the data voltage is to fine-tune the luminance of the pixel. can be adjusted to

In FIG. 1 , a vertical blank period is provided between frames. During the vertical blank period, a data voltage is not supplied to a pixel, but a light emitting signal is continuously supplied, so that the pixel continues to emit light.

2 illustrates a phenomenon in which a horizontal band defect occurs when driving a light emitting duty.

In the case of driving the emission duty, if the ON period of the emission signal for emitting pixels overlaps the vertical blank period, a region not actually driven is generated, and the number of pixels that are turned on at each timing may vary.

2 , the light emitting signal drives the display panel with a light emitting signal having a 50% duty ratio that emits light on five display lines in succession and does not emit light on five display lines in succession, and the vertical active period of the display panel is an example For example, it consists of 18 display lines, and the vertical blank period consists of 2 horizontal lines.

Here, that the vertical blank period consists of two horizontal lines means that when one display line is converted into one horizontal period (1H) on the time axis, the vertical blank period corresponds to 2H, which is two horizontal periods.

When the light emitting signal repeats the turn-on and turn-off levels at a predetermined duty ratio for each display line, the pixel does not actually emit light even if the light emitting signal reaches the turn-on level during the vertical blank period.

As shown in the left figure of FIG. 2 , when a light emitting signal of a turn-off level is output during the vertical blank blank period, the number of light emitting display lines or light emitting pixels On_PXLs is 10 in the vertical direction.

On the other hand, as shown in the right figure in FIG. 2 , when a light-emitting signal of a turn-on level is output during the vertical blank period, the number of light-emitting display lines or light-emitting pixels On_PXLs is eight in the vertical direction.

As described above, as the horizontal period progresses, the number of pixels emitting light from the display panel is not constant but changes, and thus, a horizontal band defect according to the emission duty driving is inevitable.

In the example of FIG. 2 , since the number of display lines included in the vertical active region is not a multiple of the length of the on-level section of the light emitting signal (the off-level section does not need to be considered because the duty ratio is 50%), The number of pixels (or display lines) that emit light among pixels (or display lines) changes over time.

On the other hand, when the number of display lines included in the vertical active region is a multiple of the length of the on-level section of the light emitting signal, the number of pixels emitting light in the vertical active period may not change over time.

However, if the duty ratio of the light emitting signal is changed to change the output luminance, the number of display lines included in the vertical active region may not be a multiple of the length of the on-level section of the light emitting signal or the length of the off-level section of the light emitting signal. , in this case, the number of pixels emitting light among pixels included in the vertical active period is inevitably changed over time, and a horizontal band phenomenon, which is a problem of light emission duty driving, inevitably occurs.

In order to solve the light emission duty driving problem, the light emission driver generating a light emission signal generates an odd light emission driver generating an odd light emission signal controlling light emission of the odd display lines and generating an even light emission signal controlling light emission of the even display lines. It is possible to separate the light emission driver into an even-numbered light emission driver, and to synchronize the light emission timing and the non-emission time of the two neighboring light emission signals, but to have the light emission signal have the opposite phase in some or all sections.

In addition, in order to make the number of light-emitting display lines constant among display lines belonging to the vertical active period of the display panel, one frame may be configured such that the vertical blank period is an even number of horizontal periods.

As described above, by changing the generation of the emission signal and adjusting the vertical blank period, the horizontal band problem caused by the emission duty driving can be solved.

3 is a block diagram of an organic light emitting diode display. The display device of FIG. 1 may include a display panel 10 , a timing controller 11 , a data driving circuit 12 , a gate driving circuit 13 , and a power supply unit 16 .

In the display device, the pixel circuit and the gate driving circuit may include at least one of an N-channel transistor (NMOS) and a P-channel transistor (PMOS). A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from source to drain. In the case of an N-channel transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an N-channel transistor, the direction of current flows from drain to source. In the case of a P-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

A scan signal (or gate signal) applied to the pixels swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of the N-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the P-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

Each of the pixels of the organic light emitting diode display includes an OLED, which is a light emitting device, and a driving device for driving the OLED by supplying a current to the OLED according to a gate-source voltage (Vgs). An OLED includes an anode, a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (Electron Injection layer, EIL) and the like, but is not limited thereto. When a current flows in the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) can emit visible light. have.

The driving device may be implemented as a transistor such as a metal oxide semiconductor field effect transistor (MOSFET). Although the driving transistor should have uniform electrical characteristics among the pixels, there may be differences between the pixels due to process variations and device characteristics variations, and may change with the lapse of display driving time. In order to compensate for the deviation in the electrical characteristics of the driving transistor, an internal compensation method and/or an external compensation method may be applied to the organic light emitting diode display. In the following examples, the internal compensation method is applied.

The timing controller 11 , the data driving circuit 12 , the gate driving circuit 13 , and the power supply unit 16 of FIG. 3 may be all or partly integrated in the drive IC, and the data driving circuit 12 and the gate driving circuit (13) may be merged to form one driving circuit.

On the screen on which the input image is displayed on the display panel 10 , a plurality of data lines 14 arranged in a column direction (or a vertical direction) and a plurality of data lines 14 arranged in a row direction (or a horizontal direction) are arranged on the screen on which the input image is displayed. The gate lines 15 intersect each other, and pixels PXL are arranged in a matrix form in each intersecting area to form a pixel array.

The gate line 15 applies a data voltage supplied to the data line 14 to the pixels, and supplies a scan signal, a light emitting signal, and the like for emitting light to the pixels.

The display panel 10 supplies a first power line for supplying the pixel driving voltage (or high potential power voltage) VDD to the pixels PXL and the low potential power voltage VSS to the pixels PXL. It may further include a second power line to initialize the pixel circuit, an initialization voltage line for supplying an initialization voltage Vini for initializing the pixel circuit, and the like. The first/second power line and the initialization voltage line are connected to the power source 16 . The second power line may be formed in the form of a transparent electrode covering the plurality of pixels PXL.

Touch sensors may be disposed on the pixel array of the display panel 10 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors are on-cell type or add-on type, in-cell type touch disposed on the screen AA of the display panel PXL or embedded in a pixel array. It can be implemented with sensors.

In the pixel array, pixels PXL arranged on the same horizontal line are connected to any one of the data lines 14 and any one (or two or more) of the gate lines 15 to form a pixel line or a display line. .

The pixel PXL is electrically connected to the data line 14 in response to the scan signal and the emission signal applied through the gate line 15 , receives a data voltage, and emits the OLED with a current corresponding to the data voltage. The pixels PXL disposed on the same pixel line simultaneously operate according to the scan signal and the emission signal applied from the same gate line 15 .

One pixel unit may be composed of three sub-pixels including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or four sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. , but not limited thereto. Each subpixel may be implemented as a pixel circuit including an internal compensation circuit. Hereinafter, a pixel may mean a sub-pixel in some cases.

The pixel PXL receives the pixel driving voltage VDD, the initialization voltage Vini, and the low-potential power supply voltage VSS from the power source 16 , and includes a driving transistor, an OLED, and an internal compensation circuit as shown in FIG. 4 . can

The timing controller 11 supplies the image data RGB transmitted from the external host system to the data driving circuit 12 . The timing controller 11 receives timing signals, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DCLK) from the host system, and includes the data driving circuit 12 and Control signals for controlling the operation timing of the gate driving circuit 13 are generated. The control signals include a gate control signal GCS for controlling an operation timing of the gate driving circuit 13 and a data control signal DCS for controlling an operation timing of the data driving circuit 12 .

Also, the timing controller 11 adjusts the time length of the vertical blank period constituting one frame, and may be set to have an even number of horizontal periods in the vertical blank period.

The data driving circuit 12 samples digital video data RGB input from the timing controller 11 based on the data control signal DCS, latches it, and converts it into parallel data, and through channels according to the gamma reference voltage It is converted into an analog data voltage, and the data voltage is supplied to the pixels PXL through an output channel and data lines 14 . The data voltage may be a value corresponding to the gray level to be expressed by the pixel. The data driving circuit 12 may include a plurality of source driver ICs.

Each source drive IC constituting the data driving circuit 12 may include a shift register, a latch, a level shifter, a DAC, and a buffer. The shift register shifts the clock input from the timing controller 11 to sequentially output the clock for sampling, and the latch samples digital video data or pixel data at the timing of the sampling clock sequentially input from the shift register and latches it. The sampled pixel data is output simultaneously, the level shifter shifts the voltage of the pixel data input from the latch into the input voltage range of the DAC, and the DAC converts the pixel data from the level shifter into a data voltage based on the gamma compensation voltage. and the data voltage output from the DAC is supplied to the data line 14 through the buffer.

The gate driving circuit 13 generates a scan signal and a light emission signal based on the gate control signal GCS, but generates the scan signal and the light emission signal in a row-sequential manner during the active period to generate a gate line 15 connected to each pixel line. are provided sequentially. The scan signal and the light emission signal of the gate line 15 are synchronized with the supply of the data voltage of the data line 14 . The scan signal and the emission signal swing between the gate-on voltage VGL and the gate-off voltage VGH.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel, an output buffer, and the like. have. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 using a GIP (Gate Drive IC in Panel) method. In the case of the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10 .

The gate driving circuit 13 may include a scan signal generator generating a scan signal and a light emission signal generator generating a light emission signal, respectively. In addition, the gate driving circuit 13 may separate the light emission signal generator from the odd light emission signal generation unit for generating the odd light emission signal to be supplied to the odd display line and the even light emission signal generation unit for generating the even light emission signal to be supplied to the even display line. .

The odd-numbered and even-numbered emission signal generators may generate the emission signal so that the odd-numbered emission signal and the even-numbered emission signal have different waveforms. The odd light emission signal and the even light emission signal that are paired with each other are generated at the same timing as the first edge changing from the off level to the on level and the second edge changing from the on level to the off level are synchronized with each other during duty driving do.

That is, the odd-numbered and even-numbered light-emitting signal generating unit is configured to simultaneously generate at least one timing during one period in which the sum of the on-level period and the off-level period is one period, and one of the adjacent and paired odd-numbered light-emitting signals and even-numbered light-emitting signals An odd-numbered light-emitting signal and an even-numbered light-emitting signal are generated so as to change to a turn-on level and the other to a turn-off level.

Therefore, when the duty ratio of the light emission signal is 50%, the odd light emission signal and the even light emission signal that are paired with each other change the level twice simultaneously in opposite directions during one cycle period, and the light emission signals of opposite phases are do.

In addition, when the duty ratio of the light emission signal is different from 50%, the odd light emission signal and the even light emission signal that are paired with each other have two antiphase periods in which the phases are opposite to each other during one cycle period, and are in phase with each other have one period.

The power supply unit 16 adjusts the DC input voltage provided from the host using a DC-DC converter to adjust the gate-on voltage required for the operation of the data driving circuit 12 and the gate driving circuit 13 . (VGL). A gate-off voltage VGH is generated, and a pixel driving voltage VDD, an initialization voltage Vini, and a low-potential power supply voltage VSS required for driving the pixel array are generated.

The host system may be an application processor (AP) in a mobile device, a wearable device, a virtual/augmented reality device, and the like. Alternatively, the host system may be a main board such as a television system, a set-top box, a navigation system, a personal computer, and a home theater system, but is not limited thereto.

4 illustrates a pixel circuit including six transistors and one capacitor, and includes an internal compensation circuit.

The pixel circuit of FIG. 4 includes a driving transistor DT, an OLED, five switching transistors T1 to T5, and a storage capacitor Cst. In the pixel circuit of FIG. 4 , the transistor is implemented as a P-channel transistor, but is not limited thereto.

Since it is a P-channel transistor, the gate-on voltage that turns on the transistor is the gate low voltage VGL, and the gate-off voltage that turns off the transistor is the gate high voltage VGH.

The driving transistor DT is used to generate a current for emitting an OLED corresponding to the data voltage Vdata, a gate electrode is connected to the first node N1, and any one of the first electrode and the second electrode is a pixel. It is connected to the first power line supplying the driving voltage VDD and the other is connected to the third node N3 .

The first switching transistor T1 controls the connection with the data line 14 to supply the data voltage Vdata, and the gate electrode receives the first scan signal SCAN1 from the first gate line, One of the first electrode and the second electrode is connected to the data line 14 and the other is connected to the second node N2 .

The second switching transistor T1 is for detecting a threshold voltage by diode-connecting the driving transistor DT. The gate electrode receives the second scan signal SCAN2 from the second gate line, and the first electrode and the second One of the electrodes is connected to the first node N1 and the other electrode is connected to the third node N3.

The third switching transistor T3 is for supplying the initialization voltage Vini to the second node N2 , and the gate electrode receives the light emission signal EM from the third gate line, and the first electrode and the second electrode One of them is connected to the second node N2 and the other is connected to an initialization voltage line supplying the initialization voltage Vini.

The fourth switching transistor T3 is for connecting the driving transistor DT and the OLED, the gate electrode receives the light emitting signal EM from the third gate line, and any one of the first electrode and the second electrode 3 is connected to node N3 and the other is connected to the anode electrode of the OLED.

The fifth switching transistor T3 is for supplying the initialization voltage Vini to the anode electrode of the OLED, the gate electrode receiving the second scan signal SCAN2 from the second gate line, the first electrode and the second electrode One of them is connected to the anode electrode of the OLED and the other is connected to the initialization voltage line supplying the initialization voltage Vini.

The storage capacitor Cst stores the threshold voltage Vth of the driving transistor DT and reflects the data voltage Vdata to the first node N1 that is the gate electrode of the driving transistor DT. It is connected between the (N1) and the second node (N2).

The OLED emits light according to the current generated by the driving transistor DT. The anode electrode is connected to the electrodes of the fourth and fifth transistors T4 and T5 and the cathode electrode is the second second supplying the low potential power voltage VSS. connected to the power line.

FIG. 5 shows signals related to driving of the pixel circuit of FIG. 4 . The pixel circuit of FIG. 4 is controlled by the first and second scan signals SCAN1 and SCAN2 and the emission signal EM.

The timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13 to set one frame to an initialization period t1, a data writing and sensing period t2, a hold period t3, and a light emission period. (t4) to drive the pixel circuit of FIG. Since the vertical blank period is a period in which data is not written to the pixel, it occurs in the light emission period t4 of the pixel.

In the initialization period t1, in the state in which the OLED of the pixel is emitting light with the data voltage Vdata(t-1) of the previous frame, the main configuration of the pixel is to receive the data voltage Vdata(t) of the current frame. This is the period for initializing the element.

In the initialization period t1 , the first scan signal SCAN1 maintains the gate high voltage VGH which is the gate-off voltage, and the second scan signal SCAN2 is gate-on at the gate high voltage VGH which is the gate-off voltage. The voltage is changed to the gate low voltage VGL, and the emission signal EM maintains the gate low voltage VGL, which is the gate-on voltage.

Accordingly, the first switching transistor T1 maintains the turn-off state, the second and fifth switching transistors T2 and T5 change from the turn-off state to the turn-on state, and the third and fourth switching transistors T2 and T5 are switched from the turn-off state to the turn-on state. Transistors T3 and T4 remain turned on.

In the initialization period t1, the first node N1 is connected to the initialization voltage line that supplies the initialization voltage Vini by the fifth, fourth, and second switching transistors T5, T4, and T2 in the turned-on state. It is connected to become the initialization voltage Vini, and the second node N2 maintains the initialization voltage Vini as it is by the third switching transistor T3 that maintains a turned-on state.

The data writing and sensing period t2 is a period for storing the data voltage Vdata(t) of the current frame and the threshold voltage Vth of the driving transistor DT across the storage capacitor Cst.

In the data writing and sensing period t2 , the first scan signal SCAN1 is changed from the gate high voltage VGH which is the gate-off voltage to the gate low voltage VGL which is the gate-on voltage, and the second scan signal SCAN2 is The gate low voltage VGL, which is the gate-on voltage, is maintained, and the light emitting signal EM varies from the gate-low voltage VGL, which is the gate-on voltage, to the gate-high voltage VGH, which is the gate-off voltage, to the gate low voltage (VGH), which is the gate-on voltage. VGL).

Accordingly, the first switching transistor T1 changes from the turn-off state to the turn-on state, the second and fifth switching transistors T2 and T5 maintain the turn-on state, and the third and fourth switching transistors T2 and T5 maintain the turn-on state. Transistors T3 and T4 change from a turn-on state to a turn-off state.

In the data writing and sensing period t2 , the second switching transistor T2 diode-connects the driving transistor DT and the driving transistor DT is turned on, so that the first node N1 and the third node N3 are turned on. ) is increased to a voltage VDD-Vth obtained by subtracting the pixel driving voltage VDD by the threshold voltage Vth of the driving transistor DT. The second node N2 is connected to the data line 14 by the first switching transistor T1 in the turned-on state and is charged with the data voltage Vdata(t).

The hold period t3 is a period in which the voltage of the main node of the pixel circuit is maintained as it is while the states of the first and second scan signals SCAN1 and SCAN2 are changed, and the first and second scan signals SCAN1 and SCAN2 are The gate-on voltage VGL is changed to the gate-high voltage VGH, which is the gate-off voltage, and the emission signal EM maintains the gate-high voltage VGH, which is the gate-off voltage.

Accordingly, the first, second, and fifth switching transistors T1, T2, and T5 are changed from the turn-on state to the turn-off state, and the third and fourth switching transistors T3 and T4 are turned off. to keep

In the hold period t3 , the first and second nodes N1 and N2 maintain the last state of the data writing and sensing period t2 as they are, so that the voltage VDD-Vth and the data voltage Vdata(t) are respectively applied. keep

In the light emission period t4, the data voltage Vdata(t) is set at the gate electrode of the driving transistor DT, and the driving transistor DT and the OLED are connected to form an OLED as a voltage between the source and the gate of the driving transistor DT. is the period in which the light is emitted.

In the light emission period t4 , the first and second scan signals SCAN1 and SCAN2 maintain a gate high voltage VGH which is a gate-off voltage, and the light emission signal EM maintains a gate high voltage VGH which is a gate-off voltage. is changed to the gate-low voltage VGL, which is the gate-on voltage.

Accordingly, the first, second, and fifth switching transistors T1, T2, and T5 maintain a turn-off state, and the third and fourth switching transistors T3 and T4 are turned on in the turn-off state. change to state

In the light emission period t4, the second node N2 is changed from the data voltage Vdata(t) to the initialization voltage Vini by the third switching transistor T3 that is turned on, and the first node in a floating state (N1) becomes (VDD-Vth)-(Vdata(t)-Vini) by reflecting the voltage change of the second node N2 connected to the other terminal of the storage capacitor DT.

The potential of the source electrode of the driving transistor DT is the pixel driving voltage VDD, and the potential of the first node N1, which is the gate electrode, is ((VDD-Vth)-(Vdata(t)-Vini)) of the source electrode. The potential is higher than the potential of the gate electrode, so that the driving transistor DT is turned on. In addition, a current path between the driving transistor DT and the OLED is formed by the turned-on fourth switching transistor T4 , and a current proportional to the voltage difference between the source electrode and the gate electrode N1 of the driving transistor DT will flow through the OLED.

The source-gate voltage Vsg of the driving transistor DT becomes (Vdata(t)-Vini+Vth), and the driving current I_OLED flowing from the driving transistor DT to emit OLED light is the source-gate voltage Vsg ) is proportional to the square of a value obtained by subtracting the threshold voltage Vth, and can be expressed as Equation 1 below.

As shown in Equation 1, since the threshold voltage Vth component of the driving transistor DT is erased in the relational expression of the driving current I_OLED, the threshold voltage is compensated even if the threshold voltage of the driving transistor DT is changed. The OLED may emit light with a current corresponding to the data voltage Vdata(t) input through the data line.

The hold period t3 may be omitted. In this case, when the light emission period t4 starts after the data writing and sensing period t2, the first and second scan signals SCAN1 and SCAN are gate-on voltages at the same time. The low voltage VGL may be changed to a gate high voltage VGH, which is a gate-off voltage, and the emission signal EM may be changed from a gate high voltage VGH, which is a gate-off voltage, to a gate low voltage, VGL, which is a gate-on voltage. .

In addition, although the initialization period t1 is shorter than one horizontal period 1H in FIG. 5 , the pulse width of the second scan signal SCAN2 may be lengthened by two horizontal periods 2H so that it becomes one horizontal period.

6 illustrates signals related to driving when pixels in two consecutive display lines are duty-driven, and the hold period t3 is omitted.

During the emission period t4, the emission signal EM repeats the gate high voltage VGH, which is the gate-off voltage, and the gate low voltage VGL, which is the gate-on voltage, at a duty ratio of 50%. The voltage period is referred to as an off pulse period P_off and an on pulse period P_on, respectively.

Also, a waveform when the emission signal EM becomes the gate-on voltage VGL, which is the gate-on voltage, in the initialization period t1 is referred to as an initialization pulse Pi, and the gate-off voltage in the data writing and sensing period t2. The waveform when it becomes the in-gate high voltage VGH is called a sensing pulse Ps.

The emission signal EM(i+1) of the (i+1)-th display line is delayed by one horizontal period 1H from the emission signal EM(i) of the i-th display line. In addition, the shape of the light emitting signal before the initialization period t1 may be changed according to the state of the light emitting signal before the initialization period t1 and whether it is the off pulse period P_off or the on pulse period P_on.

In FIG. 6 , since the on pulse period P_on is one horizontal period before the initialization period t1 , the light emitting signal EM changes from the gate high voltage VGH to the gate low voltage VGL at the initial stage of the initialization period t1 . is changed to

7 illustrates an example of generating a light emitting signal by separating an odd line and an even line.

In the light emission period t4, for example, when the light emission duty is driven at a duty ratio of 50%, the light emission signal generating unit is configured to have an even line in order to make two light emission signals to be supplied to the adjacent and paired odd and even display lines have opposite phases. and can be separated from each other for odd lines.

In FIG. 7 , odd stages EM_Odd to supply light emission signals to odd horizontal lines are dependently connected, and even stages EM_Even to supply light emission signals to even horizontal lines are dependently connected to odd and even stages EM_Odd and EM_Even. ) is supplied with the gate clock CLKs.

The first odd stage EM_Odd1 receives the odd start signal EVST_Odd, generates the first light emission signal EM( 1 ), is supplied to the first display line, and starts the second odd stage EM_Odd2 . supplied as a signal.

Similarly, the second odd stage EM_Odd2 uses the first light emission signal EM( 1 ) of the first odd stage EM_Odd1 as a start signal to generate a third light emission signal EM( 3 ) to display the third display. line, and also supply it as a start signal to the third odd stage (EM_Odd(3)).

Similarly, the first even-numbered stage EM_Even1 receives the even-numbered start signal EVST_Even, generates the second light-emitting signal EM( 2 ), is supplied to the second display line, and also transmits the same to the second even-numbered stage EM_Even2 . is supplied as a start signal to

Similarly, the second even stage EM_Even2 uses the second light emission signal EM( 2 ) of the first even stage EM_Even1 as a start signal to generate a fourth light emission signal EM( 4 ) for a fourth display. line, and also supplies it as a start signal to the third even stage (EM_Even(3)).

The odd-numbered start signal EVST_Odd supplied to the first odd-numbered stage EM_Odd1 and the even-numbered start signal EVST_Even supplied to the first even-numbered stage EM_Even1 are in the initialization period t1 when the light emission duty is driven at 50% duty. In the data writing and sensing period (t2), the phase is delayed by one horizontal period (1H), but in the light emission period (t4), the on-pulse period (P_on) and the off-pulse period (P_off) are repeated in antiphase synchronization, Accordingly, the odd-numbered light-emitting signal and the even-numbered light-emitting signal supplied to adjacent and paired horizontal lines are also output as signals that are synchronized with each other in the opposite phase during the light-emitting period t4.

8A to 11B illustrate a specific situation in which an odd-numbered line emission signal and an even-numbered line emission signal are synchronized to be out of phase with each other during the emission period when the emission duty is driven at a 50% duty ratio.

8A to 11B , the (i+1)th emission signal EM_Even(i+1) supplied to the even (i+1)-th display line has an initialization period t1 and a data writing and sensing period ( At t2), it is delayed by one horizontal period (1H) from the ith emission signal EM_Odd(i) supplied to the odd-numbered ith display line.

However, from the light emission period t4 of the i-th display line, which is an odd number, the i-th light-emitting signal EM_Odd(i) and the (i+1)-th light-emitting signal EM_Even(i+1) are out of phase in synchronization with each other. That is, the on pulse period P_on of the ith emission signal EM_Odd(i) corresponds to the off pulse period P_off of the (i+1)th emission signal EM_Even(i+1), and the ith emission signal EM_Odd(i)). The off-pulse period (P_off) of the signal (EM_Odd(i)) corresponds to the on-pulse period (P_on) of the (i+1)th emission signal (EM_Even(i+1)).

To this end, the (i+1)th emission signal EM_Even(i+1) supplied to the even (i+1)-th display line has a sensing pulse period Ps having a gate-high voltage VGH, which is a gate-off voltage. ), without changing to the gate low voltage VGL, which is the gate on voltage (without the level transition (Tc)), and maintaining the gate high voltage VGH as it is to form an off pulse period P_off, but the ith light emitting signal When (EM_Odd(i)) ends the on-pulse period P_on and changes to the off-pulse period P_off, it is synchronized with the gate-on voltage, which is the gate-low voltage VGL.

Thereafter, the i-th emission signal EM_Odd(i) and the (i+1)-th emission signal EM_Even(i+1) are synchronized while having different on-pulse periods P_on and off-pulse periods P_off from each other. to switch As shown in FIGS. 8A to 11B , the i-th emission signal EM_Odd(i) and the (i+1)-th emission signal EM_Even(i+1) transition at the same timing during the emission period t4. ⓣ) occurs and the level changes in opposite directions.

In other words, the (i+1)th emission signal EM_Even(i+1) supplied to the even (i+1)-th display line is immediately generated when the sensing pulse Ps starts after the initialization pulse Pi. It enters the off pulse period P_off and corresponds to the on pulse period P_on of the ith light emitting signal EM_Odd(i) supplied to the odd ith display line.

In the case of driving the emission duty at a 50% duty ratio, the on pulse period P_on and the off pulse period P_off have the same length, and the i-th emission signal EM_Odd(i) and the (i+1)-th emission signal EM_Even(i) have the same length. +1))), when the sum of the on pulse period (P_on) and the off pulse period (P_off) is one period of the duty emission, the transition occurs in the opposite direction twice at the same time in one period .

In FIGS. 8A to 11B , when the light emission duty is driven at a 50% duty ratio, the transition (ⓣ) timing occurring in the light emission period t4 and the timing of initializing to supply the data voltage of the next frame are i-th The waveforms of the emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even(i+1) are different.

The number of horizontal periods included in one frame (or the number of display lines in the vertical direction), the number of horizontal periods included in the vertical blank period, and the sum of the on pulse period P_on and the off pulse period P_off (duty light emission) 1 period), the timing of the transition ⓣ occurring twice in one period and the timing of the initialization period t1 of the i-th display line may vary.

8A to 11B, the start timings of the initialization period t1, the data writing and sensing period t2, and the light emission period t4 of the i-th display line are respectively referred to as 3, 4, and 5, respectively, and the light emission period t4. When the transition (ⓣ) timings of the 50% duty ratio light emitting signal occurring at are respectively ②, ③, ④, and ⑤, the i-th light-emitting signal (EM_Odd(i)) and the (i+1)th light-emitting signal (EM_Even( The waveform of i+1)) is shown.

In FIGS. 8A and 8B , a transition (ⓣ) of a light emission signal having a 50% duty ratio occurs at timing ②. ② At the timing, in FIG. 8A , the ith emission signal EM_Odd(i) changes from the on pulse period P_on to the off pulse period P_off, and the (i+1)th emission signal EM_Even(i+1)) is The off pulse period (P_off) is changed to the on pulse period (P_on), and in FIG. 8B, on the contrary, the i-th light emission signal EM_Odd(i) is changed from the off pulse period (P_off) to the on pulse period (P_on) and changed to the (i+)th 1) The light emission signal EM_Even(i+1) is changed from the on pulse period P_on to the off pulse period P_off.

In FIG. 8A , the ith light emitting signal EM_Odd(i) is the pulse-off period P_off at the timing ③ when the initialization period t1 of the ith display line starts. In the initialization period t1 , the light emission signal EM must be the gate low voltage VGL, which is the gate-off level, so the i-th light emission signal EM_Odd(i) in the pulse-off period P_off at timing 3 is gate high. Transition from the voltage VGH to the gate low voltage VGL is required, so that a transition operation must be inserted (Ti). An initialization pulse Pi corresponds to the ith light emitting signal EM_Odd(i) maintaining the gate low voltage VGL in the form of a pulse between timing ③ and timing ④.

The (i+1)th emission signal EM_Even(i+1) in the pulse-on period P_on, which is the gate low voltage VGL, is generated during the initialization period t1 of the (i+1)-th display line. ④ It is enough to keep the gate low voltage (VGL) as it is at timing.

In FIG. 8A , the ith emission signal EM_Odd(i) is changed from the gate low voltage VGL to the gate high voltage VGH at the timing ④ when the data writing and sensing period t2 of the i-th display line starts. , the gate high voltage (VGH) to the gate low voltage (VGL) is changed from the gate high voltage (VGH) to the gate low voltage (VGL) at timing ⑤ when the light emission period (t4) of the i-th display line starts, and a pulse of the gate high voltage (VGH) is sensed between timing ④ and timing ⑤ It corresponds to the pulse (Ps).

In FIG. 8A , the ith emission signal EM_Odd(i) is changed to the gate low voltage VGL at timing ⑤ when the emission period t4 of the i-th display line starts, and becomes the on-pulse period P_on. However, at timing ⑥ when the light emission period t4 of the (i+1)-th display line starts, the (i+1)th light emission signal EM_Even(i+1) becomes the i-th light emission signal EM_Odd(i) ), the off pulse period P_off is maintained while maintaining the gate high voltage VGH without changing from the gate high voltage VGH to the gate low voltage VGL in synchronization with the on pulse period P_on. That is, the (i+1)th emission signal EM_Even(i+1) omits the transition at timing ⑥ (Tc).

The (i+1)th light emission signal EM_Even(i+1) is generated at timing 5, which is the start timing of the light emission period t4 of the i-th display line, during the data writing and sensing period of the (i+1)-th display line. The off pulse period P_off for driving the emission duty starts while transitioning from the gate low voltage VGL to the gate high voltage VGH for the start of (t3).

That is, the off pulse period P_off starting with the sensing pulse Ps of the (i+1)th light emission signal EM_Even(i+1) is the on pulse period P of the i-th light emission signal EM_Odd(i)) It is synchronized with the on-pulse period P_on of P_on).

In FIG. 8B , a transition occurs between the ith emission signal EM_Odd(i) and the ith emission signal EM_Odd(i) at timing ②, and the transition direction is opposite to that of FIG. 8A . In FIG. 8B , the ith emission signal EM_Odd(i) is the pulse-on period P_on at the timing ③ when the initialization period t1 of the i-th display line starts, and the emission signal EM during the initialization period t1 Since is the gate low voltage VGL, which is the gate-off level, the i-th emission signal EM_Odd(i) in the pulse-on period P_off at timing 3 maintains the gate low voltage VGL as it is. Also, the i-th light emission signal EM_Odd(i) enters the on-pulse period P_on at timing ⑤ after outputting the sensing pulse Ps at timing ④.

In FIG. 8B , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)th emission signal EM_Even(i+1) in the off pulse period P_off is Since the gate high voltage VGH needs to transition to the gate low voltage VGL, a transition operation is inserted (Ti). The (i+1)th light emission signal EM_Even(i+1)) outputs an initialization pulse Pi between timing ④ and timing ⑤, outputs a sensing pulse Ps at timing ⑤, and transitions to timing ⑥ is omitted (Tc) and the gate high voltage (VGH) is maintained. That is, the (i+1)th light emission signal EM_Even(i+1) enters the off pulse period P_off starting with the sensing pulse Ps at timing ⑤, and the i-th light emission signal EM_Odd(i) It is synchronized with the on pulse period (P_on).

As shown in FIGS. 8A and 8B, when the transition period of the on/off pulse period (P_on/P_off) occurs two horizontal periods (H) earlier than the timing at which the initialization period (t1) of the i-th horizontal line starts, When the initialization period t1 starts, a transition operation is inserted into the ith emission signal EM_Odd(i) or the (i+1)th emission signal EM_Even(i+1) to become the gate low voltage VGH.

In FIGS. 9A and 9B , the transition (ⓣ) of the 50% duty ratio light emission signal occurs at the timing 3 , that is, the initialization period t1 of the ith light emission signal EM_Odd(i) starts. ③ At the timing, in FIG. 9A , the ith emission signal EM_Odd(i) is changed from the on pulse period P_on to the off pulse period P_off, and the (i+1)th emission signal EM_Even(i+1) is The off pulse period P_off changes to the on pulse period P_on, and in FIG. 9B , the ith light emitting signal EM_Odd(i) changes from the off pulse period P_off to the on pulse period P_on and changes to the (i+1)th light emitting signal EM_Odd(i). ) The light emission signal EM_Even(i+1) is changed from the on pulse period P_on to the off pulse period P_off.

In FIG. 9A, at the timing ③ with the transition ⓣ, the ith light emitting signal EM_Odd(i) changes from the on pulse period P_on to the off pulse period P_off and there must be a transition, but ③ timing is set during the initialization period ( Since t1) is the starting point, the transition is omitted (Tc) because it must be the gate low voltage VGL. Thereafter, the waveform of the ith emission signal EM_Odd(i) is as shown in FIG. 8A .

In FIG. 9A , the (i+1)th emission signal EM_Even(i+1) in the pulse-on period P_on is at the timing ④ when the initialization period t1 of the (i+1)-th display line starts. The gate low voltage VGL may be maintained as it is. Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIG. 8A .

In FIG. 9B , a transition (ⓣ) occurs between the i-th emission signal EM_Odd(i) and the (i+1)-th emission signal EM_Even(i+1) at timing ③, and the transition direction and The opposite is true. In FIG. 9B , at the timing ③ when the initialization period t1 starts, the ith emission signal EM_Odd(i) starts the off pulse period P_off, which is the gate low voltage VGL, and a gate required for the initialization period t1. It corresponds to the low voltage (VGL). Thereafter, the waveform of the ith emission signal EM_Odd(i) is as shown in FIG. 8B .

In FIG. 9B , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)th emission signal EM_Even(i+1) in the off pulse period P_off is Since it should be the gate low voltage VGL, a transition operation is inserted (Ti). Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIG. 8B .

10A and 10B, the transition (ⓣ) of the light emission signal with a 50% duty ratio is scheduled to occur at the timing ④, that is, at the beginning of the data writing and sensing period t2 of the i-th light emission signal EM_Odd(i). to be. However, ④ timing overlaps the initialization and data writing timing of the next frame, and the transition of the emission signal from the on pulse period (P_on) to the off pulse period (P_off) or from the off pulse period (P_off) to the on pulse period (P_on) is it doesn't happen

In FIG. 10A , at the timing ③ when the initialization period t1 of the i-th display line starts, the ith emission signal EM_Odd(i) belongs to the pulse-on period P_on and is the gate low voltage VGL, so the transition insertion Ti ) or transition omission (Tc) is not required, and the level of the previous timing may be maintained as it is. Thereafter, the i-th light emission signal EM_Odd(i) is generated between the ④ timing and the ⑤ timing, and enters the on-pulse period P_on at the ⑤ timing.

In FIG. 10A , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)th emission signal EM_Even(i+1) is turned on in the off pulse period P_off. A transition ⓣ occurs in the pulse period P_on, which naturally becomes the gate low voltage VGL required for the initialization period t1. Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIG. 8A or FIG. 9A .

In FIG. 10B , at the timing ③ when the initialization period t1 of the i-th display line starts, the ith emission signal EM_Odd(i) belongs to the pulse-off period P_off and is the gate high voltage VGH, so the gate low voltage ( VGL), a transition is required, resulting in transition insertion (Ti). Thereafter, the i-th light emission signal EM_Odd(i) is generated between the ④ timing and the ⑤ timing, and enters the on-pulse period P_on at the ⑤ timing.

In FIG. 10B , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)-th emission signal EM_Even(i+1) is turned off in the on-pulse period P_on. Although the transition ⓣ should occur in the pulse period P_off, the transition is omitted in order to maintain the gate low voltage VGH required for the initialization period t1 (Tc). Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIG. 8B or FIG. 9B .

In FIGS. 11A and 11B , the transition (ⓣ) of the light emission signal having a 50% duty ratio is scheduled to occur at timing ⑤, that is, when the light emission period t4 of the ith light emission signal EM_Odd(i) starts. However, ⑤ timing overlaps with the data writing and emission timing of the next frame, so that the transition of the emission signal from the on pulse period (P_on) to the off pulse period (P_off) or from the off pulse period (P_off) to the on pulse period (P_on) is it doesn't happen

11A , as in FIG. 10A , at the timing ③ when the initialization period t1 of the i-th display line starts, the ith light emitting signal EM_Odd(i) belongs to the pulse-on period P_on and is a gate low voltage VGL. There is no need for transition insertion (Ti) or transition omission (Tc), and the level of the previous timing may be maintained as it is. Thereafter, the i-th light emission signal EM_Odd(i) is generated between the ④ timing and the ⑤ timing, and enters the on-pulse period P_on at the ⑤ timing.

In FIG. 11A , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)-th emission signal EM_Even(i+1) belongs to the off-pulse period P_off. , a transition is inserted to the gate low voltage VGL required for the initialization period t1 (Ti). Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIG. 8A or FIG. 9A .

In FIG. 11B , as shown in FIG. 10B , at the timing ③ when the initialization period t1 of the i-th display line starts, the ith light emitting signal EM_Odd(i) belongs to the pulse-off period P_off and is the gate high voltage VGH. A transition to the gate low voltage (VGL) is required, so that a transition insertion (Ti) occurs. Thereafter, the i-th light emission signal EM_Odd(i) is generated between the ④ timing and the ⑤ timing, and enters the on-pulse period P_on at the ⑤ timing.

In FIG. 11B , at the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)-th emission signal EM_Even(i+1) belongs to the on-pulse period P_on. The gate low voltage VGH required for the initialization period t1 is maintained as it is. Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is as shown in FIGS. 8B to 10B .

As described with reference to FIGS. 8A to 11B , an on pulse period P_on and an off pulse period (P_on) of the light emitting signal EM supplied to two adjacent and paired display lines when the light emission duty is driven at a 50% duty ratio P_off) and output in synchronization with each other in reverse phase, the light emission signal can be adjusted in consideration of the pixel initialization/sensing period.

12A to 12C show a specific situation in which an odd-numbered line emission signal and an even-numbered line emission signal are synchronized with each other when the emission duty is driven at a 25% duty ratio.

12A to 12C , the on pulse period P_on and the off pulse period P_off of the light emitting signal EM are 3H and 9H, respectively, and correspond to light emission duty driving with a duty ratio of 25%.

The ith emission signal EM_Odd(i) starts at timing ⑤ when the emission period t4 of the i-th display line having an odd on pulse period P_on has a gate low voltage for 3 horizontal periods 3H. After maintaining (VGL), a transition occurs (to) to the gate high voltage (VGH) to enter the off pulse period (P_off). Thereafter, the ith emission signal EM_Odd(i) maintains the gate high voltage VGH for the ninth horizontal period 9H and then transitions to the gate low voltage VGL (tc) in the on pulse period P_on. enter

The (i+1)th emission signal EM_Even(i+1) is generated by outputting the sensing pulse Ps at the timing ⑤ when the emission period t4 of the odd-numbered i-th display line starts, thereby causing the off pulse period P_off , the gate high voltage VGH is maintained for 9 horizontal periods 9H, and then a transition occurs te to the gate low voltage VGL to enter the on-pulse period P_on. After that, the (i+1)th emission signal EM_Even(i+1) maintains the gate low voltage VGL for 3 horizontal periods 3H and then transitions to the gate high voltage VGH (tc) to turn off A pulse period (P_off) is entered.

⑤ The transition that occurs 3H after the timing occurs in the ith emission signal EM_Odd(i) supplied to the i-th display line, which is an odd number, so it is called to as an odd transition, and the transition that occurs 9H after the timing is Since it occurs in the (i+1)th emission signal EM_Even(i+1) supplied to the even (i+1)-th display line, it is referred to as te in the sense of even transition, ⑤ Transition occurring 12H after the timing Since the ith emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even(i+1) commonly occur, it is referred to as tc in the sense of a common transition.

In FIGS. 12A to 12C , since the emission duty is 25%, which is less than 50%, an odd transition (to) occurs before the even transition (te) after the common transition (tc), but is common when the emission duty is greater than 50%. After the transition tc, the even transition te occurs before the odd transition to.

In FIG. 12A , when the common transition tc occurs at the timing ③ when the initialization period t1 of the i-th display line starts, the ith emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even (i+1)) is shown.

In FIG. 12A , the ith emission signal EM_Odd(i) naturally enters the on-pulse period P_on from the off-pulse period P_off due to a common transition tc occurring at timing ③, and naturally during the initialization period t1 ) is the gate low voltage VGL. Thereafter, the waveform of the ith emission signal EM_Odd(i) is the same as described with reference to FIGS. 8 to 11 .

In addition, the (i+1)th light emission signal EM_Even(i+1)) enters the off pulse period P_off from the on pulse period P_on due to a common transition tc occurring at the timing ③, and (i) At the timing ④ when the initialization period t1 of the +1)-th display line begins, the (i+1)-th light emission signal EM_Even(i+1) belongs to the off-pulse period P_off, so that in the initialization period t1, the (i+1)-th emission signal EM_Even(i+1) belongs to the off-pulse period P_off. A transition is inserted (Ti) to the required gate low voltage (VGL). Thereafter, the waveform of the (i+1)th emission signal EM_Even(i+1) is the same as described with reference to FIGS. 8 to 11 .

When the common transition tc occurs at timings ② to ⑤, the waveforms of the ith emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even(i+1) before the initialization period t1 is the same as described with reference to FIGS. 8B, 9B, 10B, and 11B.

In FIGS. 12B and 12C , the odd transition (to) and the even transition (te), respectively, are, for example, at the timing ②, which is one horizontal period (1H) ahead of the timing ③ at which the initialization period t1 of the i-th display line starts. When generated, the ith emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even(i+1) are shown.

In FIG. 12B , the ith emission signal EM_Odd(i) at timing ② enters the off pulse period P_off due to an odd transition (to) to become the gate high voltage VGH, and at timing ③ the ith emission signal Since (EM_Odd(i)) needs to be changed to the gate low voltage VGL required for the initialization period t1 of the i-th display line, a transition is inserted (Ti).

In FIG. 12B , the (i+1)th light-emitting signal EM_Even(i+1) supplied to the even-numbered display line at the timing ② does not generate a transition and belongs to the off pulse period P_off to increase the gate high voltage VGH. keep At the timing ④ when the initialization period t1 of the (i+1)-th display line starts, the (i+1)th emission signal EM_Even(i+1) belongs to the off pulse period P_off, and thus the initialization period t1 ), a transition is inserted to the gate low voltage VGL (Ti).

In FIG. 12C, the i-th light emitting signal EM_Odd(i) supplied to the odd-numbered display line at timing ② belongs to the off pulse period P_off and does not make a transition and maintains the gate high voltage VGH, and at timing ③ Since the ith emission signal EM_Odd(i) needs to be changed to the gate low voltage VGL required for the initialization period t1 of the ith display line, a transition is inserted (Ti).

In FIG. 12C , at the timing ②, the (i+1)th emission signal EM_Even(i+1) enters the on-pulse period P_on by an even transition te and becomes the gate low voltage VGH, ( At the timing ④ when the initialization period t1 of the i+1)-th display line starts, the (i+1)-th emission signal EM_Even(i+1) belongs to the on-pulse period P_on, so the gate low voltage VGL is keep as it is

When the odd transition (to) and the even transition (te) occur at the timings ③, ④, ⑤, the i-th emission signal EM_Odd(i) and the (i+1)-th emission signal EM_Even(i+1)) Waveforms can be inferred in a similar way.

12A to 12C , timing ⑤ at which the emission period t4 of the i-th display line starts is the ith emission signal EM_Odd(i) and the (i+1)th emission signal EM_Even(i+1)) It corresponds to the common transition (tc) timing at which the transition occurs in common.

When the 25% duty light emission of FIG. 12 is performed, one cycle of duty becomes 12H, which is the sum of 3H, which is the on pulse period (P_on), and 9H, which is the off pulse period (P_off), a common transition (tc) occurs once during one period, , odd transitions (to) and even transitions (te) occur once.

Comparing FIGS. 8 to 11 having a duty ratio of 50% and FIG. 12 having a duty ratio of 25%, the i-th light emitting signal EM_Odd(i) and A common transition occurs at least once in the (i+1)th emission signal EM_Even(i+1), and the common transition occurs at a timing when the emission period t4 of the i-th display line starts.

FIG. 13 shows a light emission start signal and a light emission duty driving result for generating a light emission signal with a 50% duty ratio. The waveform of the light emission signal for initialization and sensing is the same as that of FIG. 9b, and the light emission signal as shown in FIG. 9b is generated. Corresponds to the light emission start signal to

The light emission start signal of FIG. 13 has an on pulse period of 6H and an off pulse period of 6H to enable 50% duty driving, and is turned on/off for a predetermined horizontal period prior to a common transition for pixel initialization and data writing/sensing. Off drive is required.

In FIG. 13 , the active area of the display panel includes, for example, 20 display lines, and one frame includes 20 horizontal periods and vertical blank periods corresponding to four horizontal periods.

Light-emitting signals having opposite on-pulse periods and off-pulse periods are supplied to adjacent odd-numbered display lines and even-numbered display lines that are paired with each other. For example, the adjacent first display line and the second display line are paired with each other. Thus, when the light-emitting signal of the on-pulse section is supplied to the first display line, the light-emitting signal of the off-pulse section is supplied to the second display section, and when the light-emitting signal of the off-pulse section is supplied to the first display line, the second display In the section, the light emission signal of the on-pulse section is supplied.

As the two display lines advance, the light emission signal is shifted by two horizontal periods (2H). The light emitting signals supplied to two display lines that are adjacent and paired at the same timing belong to one and the other of the on-pulse period and the off-pulse period, respectively.

In addition, since the vertical blank period included in one frame corresponds to an even number of horizontal periods, the sum of the lengths of the on-pulse period and the off-pulse period included in the light emitting signal supplied to the vertical blank period when transitioning from the current frame to the next frame is Similarly, there is no change in the number of light-emitting pixels in the vertical active period.

As shown in FIG. 13 , 10 display lines emitting light in the vertical active section at each timing from 1 to 24 on the horizontal axis are fixed, and the number of pixels emitting light in the entire display panel does not change.

FIG. 14 shows the emission start signal and the emission duty driving result for generating the emission signal with a 25% duty ratio. The waveform of the emission signal for initialization and sensing is the same as that of FIG. 12A, and the emission signal as shown in FIG. 12A is generated. Corresponds to the light emission start signal to

The light emission start signal of FIG. 14 has an on pulse period of 3H and an off pulse period of 9H to enable 25% duty driving, and is turned on/off for a predetermined horizontal period prior to a common transition for pixel initialization and data writing/sensing. Off drive is required.

14 and 13 , the active area of the display panel includes, for example, 20 display lines, and one frame includes 20 horizontal periods and vertical blank periods corresponding to four horizontal periods.

A light emitting signal in which an on pulse section and an off pulse section intersect is supplied to the odd and even display lines that are paired with each other, for example, to the first light emitting signal of the first adjacent display line. A first on pulse section of 3 horizontal periods and a first off pulse section of 9 horizontal periods are successively generated, and the second light emitting signal of the second display line includes a second off pulse section of 9 horizontal periods and a second off pulse section of 3 horizontal periods. Two on-pulse sections are continuously generated, and start timings of the first on-pulse section of the first light-emitting signal and the second off-pulse section of the second light-emitting signal can be synchronized.

Then, in the first light emitting signal and the second light emitting signal, the on-pulse section and the off-pulse section transition in opposite directions at the same timing at least once during the 12 horizontal period.

As in FIG. 13 , in FIG. 14 as well, since the vertical blank period included in one frame includes an even number of horizontal periods and the first and second light emitting signals have the same length of on-pulse sections, light emitting pixels in the vertical active period does not change the number of Also, the number of display lines emitting light in the vertical active section at each timing from 1 to 24 on the horizontal axis is fixed to 10, so that the number of pixels emitting light in the entire display panel does not change.

In this way, the length of the vertical blank period is adjusted to correspond to an even number of horizontal periods, and the on-pulse period of one of the first/second light emitting signals that are adjacent and paired at at least one timing during one duty period and the other By generating the light emitting signals so that the off pulse sections are synchronized with each other and transition in opposite directions, the number of display lines that emit light at each timing can be prevented from changing during the vertical active period.

Accordingly, the horizontal band phenomenon does not occur despite the light emission duty driving.

In addition, in order to synchronize the transition timing at which the on-pulse section and the off-pulse section transition, when driving adjacent and paired display lines, the start timing of the light emission period of the first display line is set as the common transition timing, and the second display The light emission timing may be delayed by omitting the transition at the start timing of the light emission period of the line.

Accordingly, by synchronizing light emission and non-emission of two adjacent display lines and making the light emission period and the non-emission period equal to each other, the sum of the number of light emission lines in the entire display panel can be constant at each timing.

The display device described in the specification may be described as follows.

According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; In synchronization with supplying the data voltage through the data line, the first scan signal, the second scan signal, and the light emission signal are supplied through the gate line connected to the pixels of each horizontal line of the display panel to drive the display panel and emit light. a driving circuit for repeating the light emitting signal in an on pulse period and an off pulse period in a period; and a timing controller configured to control the driving circuit by setting an even number of horizontal periods included in the vertical blank period constituting one frame, wherein the driving circuit includes first and second adjacent and paired first and second periods during the light emission period. The on-pulse period and the off-pulse period of the first light-emitting signal and the second light-emitting signal supplied to the second display lines are synchronized with each other.

In one embodiment, during the light emission period, within one duty period corresponding to the sum of the on pulse period and the off pulse period, the 1-1 transition and the on pulse period in which the first light emission signal is changed from the off pulse period to the on pulse period At least one of the 1-2 transitions in which the light emitting signal is changed from the OFF pulse interval to the OFF pulse interval is the 2-1 transition in which the second light emission signal is changed from the OFF pulse interval to the ON pulse interval and the 2-2 transition in which the ON pulse interval is changed to the OFF pulse interval. It can happen at the same time as one.

In an embodiment, the timing at which the 1-1 th transition and the 2-2 th transition occur may be the same.

In an embodiment, when the lengths of the on-pulse section and the off-pulse section are the same, timings at which the 1-2 th transition and the 2-1 th transition occur may be the same.

In an embodiment, when the lengths of the on pulse period and the off pulse period are different from each other, timings at which the 1-2 th transition and the 2-1 th transition occur may be different from each other.

In an embodiment, the timing controller divides one frame into an initialization period, a data writing/sensing period, and a light emission period to drive pixels of the first and second display lines, and the first light emission signal is a light emission period of the first display line. At this starting first timing, the on-pulse period is started by transitioning from the off level to the on level, and the second light emitting signal transitions from the on level to the off level at the timing when the data writing and sensing period of the second display line starts. Off pulse period can be started.

In an exemplary embodiment, the transition of the second light emitting signal from the off level to the on level may be omitted at the timing when the light emitting period of the second display line starts.

In an embodiment, the first light emitting signal has a turn-on level and a turn-off level, respectively, in the initialization period and the data writing/sensing period of the first display line, and the initialization period and the data writing/sensing period of the second display line The second light emitting signal may have a turn-on level and a turn-off level, respectively.

In an embodiment, in the first and second light emitting signals, a transition from an off level to an on level is inserted when the initialization period belongs to the off pulse period, and the timing at which the initialization period starts is changed from the on pulse period to the off pulse period When the first transition coincides with the changed first transition, the first transition may be omitted.

In an embodiment, the driving circuit may separately include a first light emitting signal generating circuit for generating a first light emitting signal and a second light emitting signal generating circuit for generating a second light emitting signal.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line
16: power generation unit

Claims (10)

a display panel including a plurality of pixels;
The display panel is driven by supplying a first scan signal, a second scan signal, and a light emitting signal through a gate line connected to pixels of each horizontal line of the display panel in synchronization with supplying a data voltage through the data line, , a driving circuit for repeating the light emitting signal in an on pulse period and an off pulse period in the light emission period; and
and a timing controller for controlling the driving circuit by setting an even number of horizontal periods included in a vertical blank period constituting one frame,
and the driving circuit synchronizes an on pulse period and an off pulse period of the first light emitting signal and the second light emitting signal supplied to adjacent and paired first and second display lines during the light emission period. display device. According to claim 1,
During the light emission period, within one duty period corresponding to the sum of the on pulse period and the off pulse period, a 1-1 transition in which the first light emission signal is changed from the off pulse period to the on pulse period and the on At least one of the 1-2 transitions in which the pulse period changes to the off pulse period is a 2-1 transition in which the second light emitting signal changes from the off pulse period to the on pulse period and the off pulse period in the on pulse period A display device, characterized in that it occurs at the same timing as one of the 2-2 transitions that change to . 3. The method of claim 2,
The display device according to claim 1, wherein the 1-1 transition and the 2-2 transition occur at the same timing. 4. The method of claim 3,
The display device of claim 1 , wherein when the lengths of the on-pulse period and the off-pulse period are equal to each other, timings at which the 1-2 th transition and the 2-1 th transition occur are the same. 4. The method of claim 3,
The display device of claim 1 , wherein when the lengths of the on pulse period and the off pulse period are different from each other, timings at which the 1-2 th transition and the 2-1 th transition occur are different from each other. According to claim 1,
the timing controller divides the one frame into an initialization period, a data writing/sensing period, and the light emission period to drive pixels of the first and second display lines;
The first light emitting signal transitions from an off level to an on level at a first timing when the light emitting period of the first display line starts to start the on pulse period, and the second light emitting signal is the data of the second display line The display device of claim 1, wherein the off-pulse period is started by transitioning from the on level to the off level at a timing when a writing and sensing period starts. 7. The method of claim 6,
and omitting the transition from the off level to the on level in the second light emission signal at a timing when the light emission period of the second display line starts. 7. The method of claim 6,
In the initialization period and the data writing/sensing period of the first display line, the first light emitting signal has the turn-on level and the turn-off level, respectively, and the initialization period and the data writing/sensing period of the second display line and the second light emitting signal has the turn-on level and the turn-off level, respectively. 9. The method of claim 8,
In the first and second light emitting signals, a transition from the off level to the on level is inserted when the initialization period belongs to the off pulse period, and the timing at which the initialization period starts is the off in the on pulse period The display device of claim 1 , wherein the first transition is omitted when it coincides with the first transition changed into a pulse period. According to claim 1,
and the driving circuit separately includes a first light emitting signal generating circuit for generating the first light emitting signal and a second light emitting signal generating circuit for generating the second light emitting signal.

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