KR20210082034A - Pixel Sensing Device And Method And Electroluminescence Display Device Including The Same - Google Patents

Abstract

According to an embodiment of the present invention, a pixel sensing device includes: a current integrator comprising an integrator amplifier having an inverting input terminal connected to an integrator capacitor and a non-inverting input terminal to which an integrator reference voltage is input, wherein both ends of the integrator capacitor are initialized to the integrator reference voltage; a line initialization switch for initializing a sensing line connected to at least one pixel and a line capacitor connected to the sensing line to a low potential voltage different from the integrator reference voltage through a sensing channel terminal; and a connection switch connected between the sensing channel terminal and the inverting input terminal. Accordingly, it is possible to prevent abnormal light emission of the light emitting device during a sensing operation.

Description

Pixel Sensing Device And Method And Electroluminescence Display Device Including The Same

The present invention relates to an electroluminescent display device.

In an active matrix type electroluminescent display device, pixels each including a light emitting element and a driving element are arranged in a matrix form, and the luminance of an image implemented in the pixels is adjusted according to a gray level of image data. The driving element controls the pixel current flowing through the light emitting element according to a voltage applied between its gate electrode and its source electrode (hereinafter, referred to as “gate-source voltage”). The amount of light emitted by the light emitting device and the luminance of the screen are determined according to the pixel current.

Since the threshold voltage and electron mobility of the driving element determine the driving characteristics of the pixel, they should be the same in all pixels. However, driving characteristics may vary between pixels due to various causes, such as process characteristics and time-varying characteristics. Such a difference in driving characteristics causes a luminance deviation, which is a limitation in realizing a desired image. In order to compensate for a luminance deviation between pixels, an external compensation technique for sensing driving characteristics of pixels and correcting input image data based on the sensing result is known.

External compensation technology senses the pixel current flowing through the pixel through a current integrator. The integrator output voltage, which is the result of sensing the pixel current, is input to an analog digital converter (ADC) and converted into a digital value. The external compensation technology initializes the output terminal of the current integrator and a specific node of the pixel (the source node of the driving device connected to the anode electrode of the light emitting device) to the integrator reference voltage before sensing the pixel current. The integrator reference voltage is determined in consideration of the sensing range of the ADC and the turn-on voltage of the light emitting device.

During the sensing operation, since the light emitting device must maintain a turned-off state, the specific node must be initialized with a sufficiently low integrator reference voltage. This is especially true in the case of a model in which the turn-on voltage of the light emitting device is low. However, as the integrator reference voltage is set lower, the sensing range of the ADC may be reduced and sensing performance may deteriorate.

Accordingly, the present invention provides a pixel sensing device and method capable of preventing abnormal light emission of a light emitting device and improving sensing performance during a sensing operation, and an electroluminescent display device including the same.

A pixel sensing device according to an embodiment of the present invention includes an integrator amplifier having an inverting input terminal connected to an integrator capacitor and a non-inverting input terminal to which an integrator reference voltage is input, wherein both ends of the integrator capacitor are initialized to the integrator reference voltage current integrator; a line initialization switch configured to initialize a sensing line connected to at least one pixel and a line capacitor connected to the sensing line to a low potential voltage different from the integrator reference voltage through a sensing channel terminal; and a connection switch connected between the sensing channel terminal and the inverted input terminal. The connection switch is turned off in a first period in which the current integrator and the line capacitor are independently initialized, and in a second period in which a pixel current flowing through the pixel following the first period is charged in the line capacitor; After the second period, it is turned on in a third period in which current movement occurs between the inverting input terminal and the line capacitor.

A pixel sensing method according to an embodiment of the present invention is a pixel sensing method using a current integrator including an integrator amplifier having an inverting input terminal connected to an integrator capacitor and a non-inverting input terminal to which an integrator reference voltage is input. initializing both ends of an integrator capacitor to the integrator reference voltage, and initializing a sensing line connected to at least one pixel and a line capacitor connected to the sensing line to a lower potential voltage different from the integrator reference voltage through a sensing channel terminal; charging the line capacitor with a pixel current flowing through the pixel in a state in which a connection switch connected between the sensing channel terminal and the inverting input terminal is turned off during a second period following the first period; and generating an integrator output voltage of the current integrator that changes due to a current movement between the inverting input terminal and the line capacitor in a state in which the connection switch is turned on during a third period following the second period.

The present invention can prevent abnormal light emission of the light emitting device during sensing operation by lowering the initializing voltage (low potential voltage) of the pixel than the initializing voltage (integrator reference voltage) of the current integrator by separating and initializing the pixel and the current integrator. have.

In the present invention, after the pixel current is stored in the line capacitor of the sensing line, the line capacitor is connected to the current integrator. Since the charging voltage of the line capacitor is set lower than the initialization voltage (integrator reference voltage) of the current integrator, a current movement occurs from the current integrator to the line capacitor. In the present invention, since the integrator output voltage is generated by sensing the current drawn from the current integrator to the line capacitor, there is no need to reduce the ADC sensing range. That is, in the present invention, since the current integrator can be configured as a current draw type, the integrator output voltage can satisfy the ADC sensing range even if the integrator reference voltage is set as low as possible within a range greater than the maximum charging voltage of the line capacitor. can increase

In the present invention, power consumption of the sensing unit can be reduced by setting the integrator reference voltage low.

Since the present invention can cut off the connection between the current integrator and the pixel during the operation of sensing the current drawn from the current integrator to the line capacitor, it prevents the noise component of the panel from being mixed into the integrator output voltage in advance to further improve the sensing accuracy. can be raised

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a pixel array included in the display panel of FIG. 1 .
3 is a diagram illustrating a configuration of a data driver connected to the pixel array of FIG. 2 .
FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3 .
5 is a diagram illustrating a connection configuration between a pixel sensing device and a pixel according to an embodiment of the present invention.
6 is a diagram illustrating driving waveforms of the pixel sensing device and the pixel of FIG. 5 .
FIG. 7A is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the first period of FIG. 6 .
FIG. 7B is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the second period of FIG. 6 .
FIG. 7C is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the third period of FIG. 6 .
8 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention.

Advantages and features of the present specification and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of the present specification complete, and common knowledge in the art to which this specification belongs It is provided to fully inform those who have the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. When 'including', 'having', 'consisting of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

In the present specification, the pixel circuit formed on the substrate of the display panel may be implemented as a TFT having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure or as a TFT having a p-type MOSFET structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In contrast, in the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET may be changed according to an applied voltage.

Meanwhile, in the present specification, the semiconductor layer of the TFT may be implemented as at least one of an oxide device, an amorphous silicon device, and a polysilicon device.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a view showing an electroluminescent display device according to an embodiment of the present invention. And, FIG. 2 is a view showing an example of a pixel array provided in the display panel of FIG. 1 .

1 and 2 , an electroluminescent display device according to an embodiment of the present invention includes a display panel 10 , a driver IC (D-IC) 20 , a compensation IC 30 , and a host system 40 . , a storage memory 50 , and a power circuit 60 may be included. The panel driver for driving the display panel 10 includes a gate driver 15 provided in the display panel 10 and a data driver 25 built in a driver IC (D-IC) 20 .

The display panel 10 is provided with a plurality of pixel lines PNL1 to PNL4, and each pixel line is provided with a plurality of pixels PXL and a plurality of signal lines. The “pixel line” described in the present invention does not mean a physical signal line, but an aggregate of adjacent pixels PXL and signal lines along the extension direction of the gate line. The signal lines are the data lines 140 for supplying the data voltage VDIS for display and the data voltage VSEN for sensing to the pixels PXL, and the pixel reference voltage VREF to the pixels PXL. reference voltage lines 150 for supplying a gate signal to the pixels PXL, gate lines 160 supplying a gate signal to the pixels PXL, and high potential power lines PWL for supplying a high potential pixel voltage to the pixels PXL. may include.

The pixels PXL of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel PXL included in the pixel array of FIG. 2 is connected to any one of the data lines 140 , any one of the reference voltage lines 150 , and to any one of the high potential power lines PWL, And it may be connected to any one of the gate lines 160 . Each pixel PXL included in the pixel array of FIG. 2 may be connected to a plurality of gate lines 160 . In addition, each pixel PXL included in the pixel array of FIG. 2 may be further supplied with a low-potential pixel voltage from the power circuit 60 . The power circuit 60 may supply a low potential pixel voltage to the pixel PXL through a low potential power line or a pad part.

A gate driver 15 may be built in the display panel 10 .

The gate driver 15 may include a plurality of gate stages connected to the gate lines 160 of the pixel array of FIG. 2 . The gate stages may generate a gate signal for controlling the switch elements of the pixels PXL and supply it to the gate lines 160 .

The driver IC (D-IC) 20 may include a timing controller 21 and a data driver 25 , but is not limited thereto. The timing controller 21 may not be included in the driver IC (D-IC) 20 but may be mounted on the control board together with the driver IC (D-IC) 20 . The data driver 25 may include a sensing unit 22 and a driving voltage generator 23 , but is not limited thereto.

The timing controller 21 refers to timing signals input from the host system 40 , for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. The gate timing control signal GDC for controlling the operation timing of the raw gate driver 15 and the data timing control signal DDC for controlling the operation timing of the data driver 25 may be generated.

The data timing control signal DDC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the driving voltage generator 23 . The source sampling clock is a clock signal that controls the sampling timing of data based on a rising or falling edge. The source output enable signal controls the output timing of the driving voltage generator 23 .

The gate timing control signal GDC may include, but is not limited to, a gate start pulse, a gate shift clock, and the like. A gate start pulse is applied to the gate stage that produces the first gate output to activate the operation of that stage. The gate shift clock is commonly input to the gate stages and is a clock signal for shifting the gate start pulse.

The timing controller 21 controls the operation timing of the panel driving circuit, thereby driving characteristics of the pixels PXL in at least one of a power-on period, a vertical active period of each frame, a vertical blank period of each frame, and a power-off period. can be sensed. Here, the power-on period is a period from when the system power is applied to before the screen is turned on, and the power-off period is a period from when the screen is turned off until the system power is released. The vertical active period is a period in which image data is written in the display panel 10 for screen reproduction, and the vertical blank period is a period between adjacent vertical active periods in which image data writing is stopped. The driving characteristics of the pixels PXL include threshold voltages and electron mobility of driving elements included in the pixels PXL.

The timing controller 21 may implement display driving and sensing driving by controlling the sensing driving timing and the display driving timing for the pixel lines PNL1 to PNL4 of the display panel 10 according to a predetermined sequence.

The timing controller 21 may generate the timing control signals GDC and DDC for driving the display and the timing control signals GDC and DDC for driving the sensing differently. The sensing driving writes the sensing data voltage VSEN to the pixels PXL included in the sensing target pixel line to sense the driving characteristics of the corresponding pixels PXL, and the corresponding pixel based on the sensing result data SDATA. This means updating a compensation value for compensating for a change in the driving characteristics of the PXLs. In addition, the display driving corrects digital image data to be input to the corresponding pixels PXL based on the updated compensation value, and applies the display data voltage VDIS corresponding to the corrected image data CDATA to the corresponding pixel. It means to display the input image by applying to the PXL.

The driving voltage generator 23 is implemented as a digital-to-analog converter (hereinafter referred to as a DAC) that converts a digital signal into an analog signal. The driving voltage generator 23 generates a sensing data voltage VSEN required for sensing driving and a display data voltage VDIS required for driving a display, and supplies it to the data lines 140 . The data voltage VDIS for display is a digital-analog conversion result of the digital image data CDATA corrected by the compensation circuit 30 , and the size of the display data voltage VDIS may be changed in units of pixels according to a grayscale value and a compensation value. The sensing data voltage VSEN may be set differently in units of R (red), G (green), B (blue), and W (white) pixels in consideration of different driving characteristics of the driving device for each color.

For sensing driving, the sensing unit 22 may sense driving characteristics of the pixels PXL, for example, a threshold voltage and electron mobility of a driving device through sensing lines. The sensing lines may be implemented as reference voltage lines 150, but is not limited thereto. The sensing lines may be implemented as data lines 140 . The sensing unit 22 may be implemented as a current sensing type that senses the pixel current IPIX flowing through each pixel PXL. The sensing unit 22 may be initialized independently of the pixel PXL by including a current integrator, an initialization switch, a connection switch, and the like. In order to prevent abnormal light emission of the pixel PXL during the sensing operation, the low potential voltage VSS for initializing the pixel PXL and the sensing line may be lower than the integrator reference voltage CVref for initializing the current integrator. have. The sensing unit 22 may be connected to the sensing line after the pixel current IPIX is charged in the line capacitor connected to the sensing line. Since the charging time of the pixel current IPIX is set so that the maximum charging voltage of the line capacitor becomes lower than the voltage of the inverting input terminal of the current integrator connected to the sensing line, that is, the maximum charging voltage of the line capacitor compared to the integrator reference voltage, the current moves from the current integrator to the line capacitor this happens The sensing unit 22 generates an integrator output voltage that changes due to the extraction of current, and the pixel current IPIX may be calculated from the integrator output voltage. Meanwhile, the integrator output voltage rises from the integrator reference voltage due to the withdrawal of the current. Accordingly, even if the integrator reference voltage is set as low as possible within a range greater than the maximum charging voltage of the line capacitor, the integrator output voltage may satisfy the ADC sensing range, and thus sensing performance may be secured. A more detailed description thereof is presented through FIGS. 5 to 7C .

The sensing unit 22 may simultaneously process a plurality of analog sensed values in parallel using a plurality of analog-digital converters (ADCs), or sequentially process a plurality of analog sensed values in series using one ADC. . The ADC converts analog sensing values into digital sensing result data SDATA according to a predetermined sensing range, and then supplies them to the storage memory 50 .

The storage memory 50 stores digital sensing result data SDATA input from the sensing unit 22 during sensing operation. The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

The compensation IC 30 may include a compensation unit 31 and a compensation memory 32 . The compensation memory 32 transmits the digital sensing result data SDATA read from the storage memory 50 to the compensation unit 31 . The compensation memory 32 may be a random access memory (RAM), for example, a double date rate synchronous dynamic RAM (DDR SDRAM), but is not limited thereto. The compensator 31 calculates a compensation offset and a compensation gain for each pixel based on the digital sensing result data SDATA read from the storage memory 50, and adds the calculated compensation offset and compensation gain to each pixel. Accordingly, the image data input from the host system 40 is corrected, and the corrected image data CDATA is supplied to the driver IC 20 .

The power circuit 60 may generate a pixel reference voltage VREF, an integrator reference voltage CVref, and a low potential voltage VSS, and supply them to the driver IC 20 . The pixel reference voltage VREF, the integrator reference voltage CVref, and the low potential voltage VSS may have different voltage levels. In particular, the integrator reference voltage CVref and the low potential voltage VSS are lower than the turn-on voltage of the light emitting device included in the pixel having the smallest degree of degradation. The deterioration of the light emitting element of the pixel may be detected through a separate deterioration sensing process. Since the turn-on voltage of the light emitting device is lower as the pixel deterioration is small, when the integrator reference voltage CVref and the low potential voltage VSS are set based on the pixel having the smallest degree of deterioration, operation safety may be secured. Moreover, when the low potential voltage VSS is set lower than the integrator reference voltage CVref, abnormal light emission of the pixel PXL can be effectively prevented during the sensing operation.

FIG. 3 is a diagram illustrating a configuration of the data driver 25 connected to the pixel array of FIG. 2 . The data driver 25 of FIG. 3 is to sense the driving characteristics of the pixels PXL through the reference voltage lines 150 .

Referring to FIG. 3 , the data driver 25 is connected to the first node (connected to the gate electrode of the driving element) of the pixel PXL through the data line 140 and the pixel ( PXL) may be connected to a second node (connected to the source electrode of the driving element). Since the pixel current IPIX flows through the second node of the pixel PXL, the reference voltage line 150 connected to the second node through the second switch element may be used as a sensing line. A line capacitor CSO for storing the pixel current IPIX is connected to the reference voltage line 150 serving as a sensing line.

The data driving unit 25 may include a sensing unit 22 , a driving voltage generating unit 23 , and a power voltage transmitting unit PTC and 24 . The sensing unit 22 and the power supply voltage transmitting unit PTC, 24 may be selectively connected to the reference voltage line 150 through the switch array SARY.

The driving voltage generator 23 may be implemented as a digital-to-analog converter (DAC) that generates a data voltage VSEN for sensing and a data voltage VDIS for display. The driving voltage generator 23 supplies the sensing data voltage VSEN and the display data voltage VDIS to the data line 140 of the display panel 10 through the data channel terminal DCH.

The power supply voltage transfer unit PTC 24 supplies the pixel reference voltage VREF input from the power circuit 60 to the reference voltage line 150 through the switch array SARY and the sensing channel terminal SCH when the display is driven. do. The pixel reference voltage VREF may be supplied to the second node of the pixel PXL in a programming period when the display is driven.

The power supply voltage transmitting unit PTC 24 supplies the integrator reference voltage CVref and the low potential voltage VSS input from the power circuit 60 to the sensing unit 22 during sensing driving.

The sensing unit 22 is connected to the sensing channel terminal SCH through the switch array SARY.

The switch array SARY includes an initialization switch (ISW of FIG. 5) and a connection switch (CSW of FIG. 5) connected between the sensing unit 22 and the sensing channel terminal SCH, and a power supply voltage transfer unit PTC, 24 ) and the sensing channel terminal SCH and further includes a reference voltage supply switch (not shown) for transferring the pixel reference voltage VREF.

FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3 .

Referring to FIG. 4 , one pixel PXL using the reference voltage line 150 as a sensing line includes a light emitting element EL, a driving TFT DT, switch TFTs ST1 and ST2, and a storage capacitor Cst. ) is included. The driving TFT DT and the switch TFTs ST1 and ST2 may be implemented as NMOS, but are not limited thereto.

The light emitting element EL is a light emitting element that emits light with an intensity corresponding to the pixel current received from the driving TFT DT. The light emitting device EL may be implemented as an organic light emitting diode including an organic light emitting layer or as an inorganic light emitting diode including an inorganic light emitting layer. The anode electrode of the light emitting element EL is connected to the second node N2 , and the cathode electrode is connected to the input terminal of the low-potential pixel voltage EVSS.

The driving TFT DT is a driving element that generates a pixel current in response to a gate-source voltage. The gate electrode of the driving TFT DT is connected to the first node N1, the first electrode is connected to the input terminal of the high potential pixel voltage EVDD through the high potential power line PWL, and the second electrode is connected to the second electrode 2 is connected to the node N2.

The switch TFTs ST1 and ST2 are switch elements that set a gate-source voltage of the driving TFT DT and connect the second electrode of the driving TFT DT and the reference voltage line 150 .

The first switch TFT ST1 is connected between the data line 140 and the first node N1 and is turned on according to the gate signal SCAN from the gate line 160 . The first switch TFT ST1 is turned on during programming for display driving or sensing driving. When the first switch TFT ST1 is turned on, the sensing data voltage VSEN or the display data voltage VDIS is applied to the first node N1 . The gate electrode of the first switch TFT ST1 is connected to the gate line 160 , the first electrode is connected to the data line 140 , and the second electrode is connected to the first node N1 .

The second switch TFT ST2 is connected between the reference voltage line 150 and the second node N2 and is turned on according to the gate signal SCAN from the gate line 160 . The second switch TFT ST2 is turned on during programming for display driving or sensing driving to apply a pixel reference voltage VREF or a low potential voltage VSS to the second node N2 . Also, the second switch TFT ST2 is turned on during the sensing operation after programming to supply the pixel current generated by the driving TFT DT to the reference voltage line 150 . The gate electrode of the second switch TFT ST2 is connected to the gate line 160 , the first electrode is connected to the reference voltage line 150 , and the second electrode is connected to the second node N2 .

The storage capacitor Cst is connected between the first node N1 and the second node N2 to maintain the gate-source voltage of the driving TFT DT for a predetermined period of time. The gate-source voltage of the driving TFT DT for driving the display becomes a differential voltage between the display data voltage VDIS and the pixel reference voltage VREF, and between the gate-source of the driving TFT DT for sensing driving. The voltage is a difference voltage between the sensing data voltage VSEN and the low potential voltage VSS.

5 is a diagram illustrating a connection configuration between a pixel sensing device and a pixel according to an embodiment of the present invention.

The pixel sensing device according to an embodiment of the present invention may be implemented as the sensing unit 22 . The sensing unit 22 includes a current integrator CI, an initialization switch ISW, and a connection switch CSW as shown in FIG. 5 , and may further include a sample and hold unit SH and an ADC.

The current integrator CI may be implemented with an integrator amplifier AMP, an integrator capacitor CFB, and a reset switch RST. The integrator amplifier AMP has an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The integrator capacitor CFB and the reset switch RST are connected in parallel between the inverting input terminal (-) and the output terminal.

The integrator amplifier AMP is implemented as a negative feedback type in which current can flow out/in into the inverting input terminal (-). The sensing output CI-OUT of the integrator amplifier AMP varies depending on the current inflow type and the current outflow type. In the current inflow type, as current flows into the integrator capacitor CFB through the inverting input terminal (-), the sensing output CI-OUT of the integrator amplifier AMP is lowered from the integrator reference voltage CVref. Conversely, in the case of the current outflow type, as the current flows from the integrator capacitor CFB through the inverting input terminal (-), the sensing output CI-OUT of the integrator amplifier AMP becomes higher from the integrator reference voltage CVref. do.

In the case of the current inflow type, since the falling slope of the sensing output (CI-OUT), which is lowered from the integrator reference voltage (CVref), increases in proportion to the amount of the incoming current, the integrator reference voltage (CVref) must be high in consideration of the ADC sensing range. do. Otherwise, the ADC output value may under-flower to the lower limit of the sensing range. When the integrator reference voltage CVref is high, power consumption of the sensing unit 22 may increase.

On the other hand, in the case of the current outflow type, since the rising slope of the sensing output CI-OUT, which rises from the integrator reference voltage CVref, increases in proportion to the amount of the outflow current, it is sufficient even if a low integrator reference voltage CVref is used. The sensing range can be satisfied, and it is easy to reduce the power consumption of the sensing unit 22 .

In the pixel sensing device of the present invention, the charging voltage VSIO of the line capacitor CSO connected to the sensing line SL is lower than the integrator reference voltage CVref charged in the inverting input terminal (-) of the integrator amplifier AMP. By setting the charging period of the line capacitor CSO, the current integrator CI may be operated in a current outflow type. The initialization switch ISW and the connection switch CSW are components necessary to operate the current integrator CI in a current outflow type.

The initialization switch ISW is connected between the input terminal of the low potential voltage VSS and the sensing channel terminal SCH. The initialization switch ISW serves to initialize the sensing line SL connected to the pixel PXL and the line capacitor CSO connected to the sensing line SL to the low potential voltage VSS through the sensing channel terminal SCH. do Meanwhile, by the connection switch CSW, the current integrator CI is independently initialized from the sensing line SL and the line capacitor CSO. Both ends of the integrator capacitor CFB, that is, the inverting input terminal (-) and the output terminal of the integrator amplifier AMP are initialized to the integrator reference voltage CVref.

The connection switch CSW is connected between the sensing channel terminal SCH and the inverting input terminal (-) of the integrator amplifier AMP to turn on/off the current flow. In the connection switch CSW, the first period in which the current integrator CI and the line capacitor CSO are independently initialized, and the pixel current IPIX flowing through the pixel PXL following the first period is applied to the line capacitor CSO. It is turned off in the second period of being charged. Then, the connection switch CSW is turned on in the third period in which current movement occurs between the inverting input terminal (-) of the integrator amplifier AMP and the line capacitor CSO following the second period.

Since the charging voltage VSIO of the line capacitor CSO at the start time of the third period is lower than the integrator reference voltage CVref charged in the inverting input terminal (-) of the integrator amplifier AMP, the integrator amplifier during the third period A current shift occurs from the inverting input terminal (-) of (AMP) to the line capacitor (CSO). Due to this current movement, the integrator output voltage CI-OUT applied to the output terminal of the current integrator CI rises from the integrator reference voltage CVref.

The sample and hold unit SH serves to sample the integrator output voltage CI-OUT rising from the integrator reference voltage CVref according to the sampling signal SAM. The sample and hold unit SH includes a sampling switch operating according to the sampling signal SAM, a sampling capacitor storing a sampled voltage when the sampling switch is turned on, and a sampling capacitor stored in the sampling capacitor when the sampling signal SAM is turned off. It may include a holding switch that outputs the sampling voltage to the ADC. The ADC converts the sampling voltage to analog-to-digital according to the sensing range.

FIG. 6 is a driving waveform diagram of the pixel sensing device and the pixel of FIG. 5 . FIG. 7A is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the first period of FIG. 6 . FIG. 7B is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the second period of FIG. 6 . And, FIG. 7C is a diagram for explaining the operation of the pixel sensing device and the pixel performed in the third period of FIG. 6 .

Referring to FIG. 6 , the sensing driving according to the embodiment of the present invention is performed in the order of a first period (①), a second period (②), and a third period (③). The pixel sensing device of FIG. 5 and the pixel PXL of FIG. 4 will be described as follows.

Referring to FIGS. 6 and 7A , the initialization operation of the current integrator CI by the connection switch CSW in the off state in the first period (①) and the initialization operation of the sensing line SL and the line capacitor CSO This is done independently.

In the first period (①), the inverting input terminal (-) and the output terminal of the integrator amplifier AMP are initialized to the integrator reference voltage CVref by the reset switch RST in the on state.

In the first period (①), the sensing line SL and the line capacitor CSO are initialized to the low potential voltage VSS by the initialization switch ISW in the on state. At this time, the low potential voltage VSS is also charged to the second node N2 of the pixel PXL by turning on the second switch TFT ST2 according to the on-level gate signal SCAN.

In the first period (①), the charging voltage VSIO of the line capacitor CSO is “0V”, and the integrator output voltage CI-OUT becomes the integrator reference voltage CVref.

6 and 7B , the sensing data voltage VSEN is applied to the first node N1 of the pixel PXL via the first switch TFT ST1 in the on state in the second period (②). and a pixel current IPIX corresponding to the gate-source voltage VSEN-VSS of the driving TFT DT flows through the driving TFT DT. Since the initialization switch ISW is turned off in the second period (②), the pixel current IPIX is charged in the line capacitor CSO through the second switch TFT ST2 and the sensing line SL in the on state.

In the second period (②), the current integrator CI maintains the initialized state by the off-state connection switch CSW.

In the second period (②), the charging voltage VSIO of the line capacitor CSO rises from “0V” to “VCHG” due to the accumulation of the pixel current IPIX, and the integrator output voltage CI-OUT is based on the integrator The voltage CVref is maintained.

On the other hand, when the length Tsen1 of the second period (②) increases, the accumulation time of the pixel current IPIX increases, so that the level of the charging voltage VSIO of the line capacitor CSO increases. However, in order to operate the current integrator CI in a current outflow type in the third period (③), the charging voltage VSIO of the line capacitor CSO at the start of the third period (③) is the integrator reference voltage (CVref) should be lower than

To this end, the length Tsen1 of the second period (②) is the length of the display panel 10 under the same programming condition (ie, a condition in which the gate-source voltage VSEN-VSS of the driving TFT DT is equal). It is set based on the largest pixel current among the pixel currents IPIX flowing through the pixels PXL. In other words, the length Tsen1 of the second period ② is set based on the maximum charging voltage of the line capacitor CSO under the same programming condition. Even if the programming conditions are the same, the sizes of the pixel currents IPIX flowing through the pixels PXL may vary due to a threshold voltage deviation of the driving TFT DT. The magnitude of the pixel current is greatest in a pixel in which the threshold voltage of the driving TFT DT is most shifted in the negative direction, and the smallest in a pixel in which the threshold voltage of the driving TFT DT is most shifted in the positive direction.

Referring to FIGS. 6 and 7C , current movement occurs between the inverting input terminal (-) of the integrator amplifier AMP and the line capacitor CSO by the connection switch CSW in the on state in the third period (③). . Since the integrator reference voltage CVref charged to the inverting input terminal (-) is higher than “VCHG”, which is the maximum charging voltage VSIO of the line capacitor CSO, and the on-state connection switch CSW serves as a resistor, the second During the 3 period (③), a current moves from the inverting input terminal (-) to the line capacitor CSO, and the reset switch RST in the OFF state and the integrator applied to the output terminal of the current integrator CI due to the current movement The output voltage CI-OUT rises from the integrator reference voltage CVref.

The integrator output voltage CI-OUT that rises from the integrator reference voltage CVref during the third period (③) is stored in the sample and hold unit SH. Then, the sampling voltage ΔV is output to the ADC at a sampling point in time when the sampling signal SAM changes from an on level to an off level.

The sampling voltage ΔV may be converted into a current i moved in the third period (③) by Equation 1 below. In Equation 1, "Tsen2" means the length of the third period (③).

[Equation 1]

And, the charging voltage VSIO of the line capacitor CSO may be calculated by Equation 2 below.

[Equation 2]

Then, the pixel current IPIX flowing through the pixel PXL may be calculated by Equation 3 below.

[Equation 3]

As a result, since the pixel current IPIX can be derived through the sampling voltage ΔV, it is possible to sense a change in the driving characteristic of the pixel PXL. Calculations according to Equations 1 to 3 may be performed in the compensation IC 30 of FIG. 1 .

Meanwhile, since the second switch TFT ST2 is turned off by the off-level gate signal SCAN in the third period (③), the current integrator CI is disconnected from the pixel PXL. Accordingly, the common noise component of the panel is not reflected in the integrator output voltage CI-OUT, and thus the accuracy of sensing is increased.

8 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention.

Referring to FIG. 8 , in the pixel sensing method according to the embodiment of the present invention, the initialization operation of the integrator amplifier AMP included in the current integrator CI and the initialization operation of the sensing line SL and the line capacitor CSO are performed. It proceeds independently (S101). In other words, this sensing method initializes both ends of the integrator capacitor to the integrator reference voltage during the first period, and sets the sensing line connected to at least one pixel and the line capacitor connected to the sensing line to the integrator reference voltage through the sensing channel terminal Initialize to low potential voltage.

Referring to FIG. 8 , in the pixel sensing method according to an embodiment of the present invention, during a second period following the first period, the pixel is in a state in which a connection switch connected between the sensing channel terminal and the inverting input terminal is turned off. The line capacitor is charged with the pixel current flowing in (S102).

Referring to FIG. 8 , in the pixel sensing method according to an embodiment of the present invention, during a third period following the second period, in a state in which the connection switch is turned on, the change due to current movement between the inverting input terminal and the line capacitor An integrator output voltage of the current integrator is generated (S103, S104).

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 15: gate driver
20: driver IC 21: timing control unit
22: sensing unit

Claims (15)

a current integrator comprising an integrator amplifier having an inverting input terminal connected to the integrator capacitor and a non-inverting input terminal to which an integrator reference voltage is input, wherein both ends of the integrator capacitor are initialized to the integrator reference voltage;
a line initialization switch configured to initialize a sensing line connected to at least one pixel and a line capacitor connected to the sensing line to a low potential voltage different from the integrator reference voltage through a sensing channel terminal; and
and a connection switch connected between the sensing channel terminal and the inverted input terminal,
The connection switch is
a first period in which the current integrator and the line capacitor are independently initialized, and a second period in which a pixel current flowing through the pixel following the first period is charged in the line capacitor;
The pixel sensing device is turned on in a third period in which current movement occurs between the inverting input terminal and the line capacitor following the second period. The method of claim 1,
A charging voltage of the line capacitor at a start time of the third period is lower than the integrator reference voltage of the inverting input terminal. 3. The method of claim 2,
During the third period, a current moves from the inverting input terminal to the line capacitor, and an integrator output voltage applied to an output terminal of the current integrator increases from the integrator reference voltage due to the current movement. The method of claim 1,
and the current integrator is disconnected from the pixel during the third period. The method of claim 1,
The low potential voltage and the integrator reference voltage are respectively lower than a turn-on voltage of a light emitting device included in the pixel. 6. The method of claim 5,
The low potential voltage is lower than the integrator reference voltage. 3. The method of claim 2,
the length of the second period is set based on the pixel current so that the charging voltage of the line capacitor is lower than the integrator reference voltage at the start time of the third period;
The pixel current is the largest value among the plurality of pixel currents flowing through the plurality of pixels under a programming condition. A pixel sensing method using a current integrator including an integrator amplifier having an inverting input terminal connected to an integrator capacitor and a non-inverting input terminal to which an integrator reference voltage is input,
During a first period, both ends of the integrator capacitor are initialized to the integrator reference voltage, and a sensing line connected to at least one pixel and a line capacitor connected to the sensing line are set to a low potential voltage different from the integrator reference voltage through a sensing channel terminal. initializing;
charging the line capacitor with a pixel current flowing through the pixel in a state in which a connection switch connected between the sensing channel terminal and the inverting input terminal is turned off during a second period following the first period; and
and generating an integrator output voltage of the current integrator that changes due to a current movement between the inverting input terminal and the line capacitor while the connection switch is turned on during a third period following the second period. 9. The method of claim 8,
The charging voltage of the line capacitor at the start time of the third period is lower than the integrator reference voltage of the inverting input terminal. 10. The method of claim 9,
During the third period, a current is moved from the inverting input terminal to the line capacitor, and an integrator output voltage applied to an output terminal of the current integrator increases from the integrator reference voltage due to the current movement. 9. The method of claim 8,
and the current integrator is disconnected from the pixel during the third period. 9. The method of claim 8,
The low potential voltage and the integrator reference voltage are each lower than a turn-on voltage of a light emitting device included in the pixel. 13. The method of claim 12,
wherein the low potential voltage is lower than the integrator reference voltage. 10. The method of claim 9,
the length of the second period is set based on the pixel current so that the charging voltage of the line capacitor is lower than the integrator reference voltage at the start time of the third period;
The pixel current is the largest value among the plurality of pixel currents flowing through the plurality of pixels. a display panel including a sensing line connected to at least one pixel and a line capacitor connected to the sensing line;
a data driver supplying a data voltage for sensing to a data line connected to the one pixel;
a gate driver supplying a gate signal synchronized with the sensing data voltage to a gate line connected to the one pixel; and
The electroluminescent display device including the pixel sensing device of any one of claims 1 to 7, which senses the driving characteristic of the pixel through the sensing line.

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